The Way Things Were
Total Page：16
File Type：pdf, Size：1020Kb
Load more
Recommended publications
-
Lecture 27 Semiconductor Memory: DRAM and Non-Volatile Memory Administrivia
Lecture 27 Semiconductor Memory: DRAM and Non-Volatile Memory Digital Integrated Circuits Interconnect © Prentice Hall 2000 Administrivia l Today: Project phase 3 announcement. l Poster Session Tu 5/8 1-4pm » Location BWRC, 2108 Allston Way l Last lecture on Th 5/3 will cover issues in IC design Digital Integrated Circuits Interconnect © Prentice Hall 2000 1 Lectures Last l ROM and SRAM Today l Introducing the project phase III l DRAM and Non-volatile Digital Integrated Circuits Interconnect © Prentice Hall 2000 Project Phase III A proposed SRAM cell! w/ Control Circuit Digital Integrated Circuits Interconnect © Prentice Hall 2000 2 Tasks l Explain the behavior of the cell in its global contents. Provide transient simulations to illustrate. l Identify weakness of the cell in terms of signal integrity and power dissipation. Quantify your statements. l Propose an implementation that improves power dissipation. Digital Integrated Circuits Interconnect © Prentice Hall 2000 Report l Report » Comparison, Selection, Electrical Design » Cell Layout, Timing Waveforms in SRAM, Simulation » Power and Estimation and Proposal for SRAM power reduction l 3 slides on poster, each of which represents one of the tasks of the previous slide » Explanation of cell operation, comparison, design » Cell Operation in SRAM, Waveforms, Simulation » Proposal of improved SRAM implementation (from a power perspective) Digital Integrated Circuits Interconnect © Prentice Hall 2000 3 SEMICONDUCTOR MEMORIES Digital Integrated Circuits Interconnect © Prentice Hall 2000 3-Transistor DRAM Cell BL1 BL2 WWL WWL RWL RWL X X M3 VDD-VT M2 M1 VDD BL1 CS BL2 VDD-VT DV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = VWWL-VTn Digital Integrated Circuits Interconnect © Prentice Hall 2000 4 3T-DRAM — Layout BL2 BL1 GND RWL M3 M2 WWL M1 Digital Integrated Circuits Interconnect © Prentice Hall 2000 1-Transistor DRAM Cell BL WL Write "1" Read "1" WL 1 M C X S GND VDD-VT V BL DD VDD/2 VDD/2 CBL sensing Write: CS is charged or discharged by asserting WL and BL. -
Nanotechnology Trends in Nonvolatile Memory Devices
IBM Research Nanotechnology Trends in Nonvolatile Memory Devices Gian-Luca Bona [email protected] IBM Research, Almaden Research Center © 2008 IBM Corporation IBM Research The Elusive Universal Memory © 2008 IBM Corporation IBM Research Incumbent Semiconductor Memories SRAM Cost NOR FLASH DRAM NAND FLASH Attributes for universal memories: –Highest performance –Lowest active and standby power –Unlimited Read/Write endurance –Non-Volatility –Compatible to existing technologies –Continuously scalable –Lowest cost per bit Performance © 2008 IBM Corporation IBM Research Incumbent Semiconductor Memories SRAM Cost NOR FLASH DRAM NAND FLASH m+1 SLm SLm-1 WLn-1 WLn WLn+1 A new class of universal storage device : – a fast solid-state, nonvolatile RAM – enables compact, robust storage systems with solid state reliability and significantly improved cost- performance Performance © 2008 IBM Corporation IBM Research Non-volatile, universal semiconductor memory SL m+1 SL m SL m-1 WL n-1 WL n WL n+1 Everyone is looking for a dense (cheap) crosspoint memory. It is relatively easy to identify materials that show bistable hysteretic behavior (easily distinguishable, stable on/off states). IBM © 2006 IBM Corporation IBM Research The Memory Landscape © 2008 IBM Corporation IBM Research IBM Research Histogram of Memory Papers Papers presented at Symposium on VLSI Technology and IEDM; Ref.: G. Burr et al., IBM Journal of R&D, Vol.52, No.4/5, July 2008 © 2008 IBM Corporation IBM Research IBM Research Emerging Memory Technologies Memory technology remains an -
Introduction Mainframes
LL I I I I Introduction . 11.. V ZI i ..O. There is little question that the current enthusiasm in personal computing was catalyzed by the introduction of the MITS Altair computer kit in January 1975. This computer kit demonstrated by its cost (originally less than $400) that individuals could now afford a computer. And by its design the Altair established a standard bus structure for the personal computing industry. Less than six months after MITS announced the Altair computer, other manufacturers were announcing com- patible memory boards, interface boards, and peripherals. Within the year bus-compatible mainframes were also introduced. Today over 50 manufacturers support what is known as the Standard 100 or S-100 bus derived from the 100-wire bus used in the original Altair computer. Over 20,000 mainframes using the S-100 bus are now in the field. One key reason for the rapid growth of the personal computer industry can be found in the widespread adoption of a standard microcomputer bus. A second key reason can be found in the design innovations in mainframes, memories, and I/O interfaces designed for the S-100 bus. Figure 1. The basic personal computer can accept a number of standard 5" x 10" cards designed for the industry standard S-100 microcomputer bus. A large selection of CPU, memory, and interface cards offers a great deal of flexibility in system Mainframes design. The basic personal computer mainframe consists of a CPU, computer bus, and power supply. Most mainframes are sold in kit form (Figure 1). Without exception in the personal computing industry of manufacturer support for the S-100 bus, no fewer than a microprocessor serves as the CPU. -
Timeline of Computer History
Timeline of Computer History By Year By Category Search AI & Robotics (55) Computers (145)(145) Graphics & Games (48) Memory & Storage (61) Networking & The Popular Culture (50) Software & Languages (60) Bell Laboratories scientist 1937 George Stibitz uses relays for a Hewlett-Packard is founded demonstration adder 1939 Hewlett and Packard in their garage workshop “Model K” Adder David Packard and Bill Hewlett found their company in a Alto, California garage. Their first product, the HP 200A A Called the “Model K” Adder because he built it on his Oscillator, rapidly became a popular piece of test equipm “Kitchen” table, this simple demonstration circuit provides for engineers. Walt Disney Pictures ordered eight of the 2 proof of concept for applying Boolean logic to the design of model to test recording equipment and speaker systems computers, resulting in construction of the relay-based Model the 12 specially equipped theatres that showed the movie I Complex Calculator in 1939. That same year in Germany, “Fantasia” in 1940. engineer Konrad Zuse built his Z2 computer, also using telephone company relays. The Complex Number Calculat 1940 Konrad Zuse finishes the Z3 (CNC) is completed Computer 1941 The Zuse Z3 Computer The Z3, an early computer built by German engineer Konrad Zuse working in complete isolation from developments elsewhere, uses 2,300 relays, performs floating point binary arithmetic, and has a 22-bit word length. The Z3 was used for aerodynamic calculations but was destroyed in a bombing raid on Berlin in late 1943. Zuse later supervised a reconstruction of the Z3 in the 1960s, which is currently on Operator at Complex Number Calculator (CNC) display at the Deutsches Museum in Munich. -
FF7W Sponsors ACR Standards Meeting and from There to the Factory It Is Just a Short Walk
HITS MOVING TO EXPANDED FACILITY by David Bunnell tentatively scheduled for March, Altairs to Albuquerque for demonstra- 1976. All Altair owners will be in- tion purposes. Prizes worth several By the end of January, 1976, it vited to attend this convention. thousand dollars will be awarded to is hoped that MITS will be in its the best demonstrations in each of new facility near the Albuquerque While formal plans for this an undetermined number of catagories. Airport. Internal construction has convention have not been finalized, (We will be looking for unique ap- been in progress for several weeks $ an outline of this event calls for a plications as well as well-developed and plans call for moving the pro- weekend of seminars and demonstra- traditional applications.) duction department before Christmas. tions. The seminars will be con- Administrative departments will move ducted by MITS engineers and software writers and will cover a wide range during January. Since the new MITS plant is of topics of interest to Altair users. located close to the Albuquerque In connection with this move, Airport, it will be very convenient there will be a combined open-house, Hobby clubs and individual Al- for out-of-town Altair users to at- World Altair Computer Convention, tair owners are asked to bring their tend the convention. Hotel reserva- tions can be made at the Albuquerque Airport Marina Hotel across the street from the terminal building, FF7W Sponsors ACR Standards Meeting and from there to the factory it is just a short walk. Users and manufacturers of audio The rest of the meeting was cassette data recording hardware at- spent primarily on discussion of mod- tended a symposium sponsored by BYTE ulation techniques. -
Periodical Guide for Computerists 1977
PERIODICAL GUIDE FOR COMPUTERISTS An Index of Magazine Articles for Computer Hobbyists January - December 1977 PERIODICAL GUIDE FOR COMPUTERISTS 1977 TABLE OF CONTENTS AMATEUR RADIO---------------------- 3 MICROCOMPUTERS ANALOG HARDWARE AND CIRCUITS------- 3 GENERAL------------------------- 36 APPLICATIONS, GENERAL-------------- 4 FUNDAMENTALS AND DESIGN--------- 37 ART--------------------------------5 SELECTION GUIDE----------------- 38 ASTRONOMY--------------------------6 AL TAI R 8800 & 680--------------- 38 BAR CODES--------------------------6 APPLE---------------------------39 BIORYTHMS--------------------------6 DI GIT AL GROUP------------------- 39 BIO FEEDBACK------------------------ 6 ELF & VIP ( COSMAC)-------------- 39 BOOKS AND PUBLICATIONS-------------6 HEATHKIT------------------------ 39 BUSINESS AND ACCOUNTING------------ 7 IMSAI--------------------------- 39 CALCULATORS------------------------ 8 INTERCEPT IM6100---------------- 39 CLUBS AND ORGANIZATIONS------------ 9 KIM----------------------------- 39 CLOCKS-----------------------------·9 PET----------------------------- 40 COMMUNICATION---------------------- 10 RADIO SHACK--------------------- 40 CONSTRUCTION----------------------- 10 SOL----------------------------- 40 CONTROL---------------------------- 11 SPHERE-------------------------- 40 CON VE RS ION, CODE------------------- 11 SWTPC--------------------------- 40 CONVERSION, NUMBER BASE------------ 11 WAVE MATE----------------------- 40 DEBUG------------------------------ 12 OTHER MICROCOMPUTERS------------ 41 -
Memory We Have Already Mentioned That Digital Computer Works on Stored Programmed Concept Introduced by Von Neumann
www.getmyuni.com Memory We have already mentioned that digital computer works on stored programmed concept introduced by Von Neumann. We use memory to store the information, which includes both program and data. Due to several reasons, we have different kind of memories. We use different kind of memory at different level. The memory of computer is broadly categories into two categories: . Internal and . external Internal memory is used by CPU to perform task and external memory is used to store bulk information, which includes large software and data. Memory is used to store the information in digital form. The memory hierarchy is given by: . Register . Cache Memory . Main Memory . Magnetic Disk . Removable media (Magnetic tape) Register: This is a part of Central Processor Unit, so they reside inside the CPU. The information from main memory is brought to CPU and keep the information in register. Due to space and cost constraints, we have got a limited number of registers in a CPU. These are basically faster devices. Cache Memory: Cache memory is a storage device placed in between CPU and main memory. These are semiconductor memories. These are basically fast memory device, faster than main memory. We cannot have a big volume of cache memory due to its higher cost and some constraints of the CPU. Due to higher cost we cannot replace the whole main memory by faster memory. Generally, the most recently used information is kept in the cache memory. It is brought from the main memory and placed in the cache memory. Now days, we get CPU with internal cache. -
VLSI Memory Lecture-Nahas-181025.Pdf
Introduction to CMOS VLSI Design Semiconductor Memory Harris and Weste, Chapter 12 25 October 2018 J. J. Nahas and P. M. Kogge Modified from slides by Jay Brockman 2008 [Including slides from Harris & Weste, Ed 4, Adapted from Mary Jane Irwin and Vijay Narananan, CSE Penn State adaptation of Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.] Semiconductor Memory Slide 1 Outline Memory features and comparisons Generic Memory Architecture – Architecture Overview – Row and Column Decoders – Redundancy and Error Correction Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM) Flash (EEPROM) Memory Other Memory Types Semiconductor MemoryCMOS VLSI Design Slide 2 1 Memory Features and Comparisons Semiconductor MemoryCMOS VLSI Design Slide 3 Memory Characteristics Read/Write Attributes – Read-Only Memory (ROM): Programmed at manufacture • Being phased out of use in favor of Flash – Read-Write Memory: Can change value dynamically • SRAM, DRAM – Read-Mostly: Can write, but much more slowly than read • EEPROM (Electrically Eraseable, Programable Read Only Memory) (pronounced “Double E Prom”) • Flash (A form of EEPROM) Volatility: sensitivity to losing power – Volatile: loses contents when power turned off – Non-volatile: does not lose contents Semiconductor MemoryCMOS VLSI Design Slide 4 2 Memory Characteristics Addressability – Random-Access: provide address to access a “word” of data • No correlation between successive addresses – Block oriented: read and write large blocks of data at a time – Content-addressable: -
17. Semiconductor Memories
17. Semiconductor Memories Institute of Microelectronic Systems Overview •Introduction • Read Only Memory (ROM) • Nonvolatile Read/Write Memory (RWM) • Static Random Access Memory (SRAM) • Dynamic Random Access Memory (DRAM) •Summary Institute of Microelectronic 17: Semiconductor Memories Systems 2 Semiconductor Memory Classification Non-Volatile Memory Volatile Memory Read Only Memory Read/Write Memory Read/Write Memory (ROM) (RWM) Random Non-Random Mask-Programmable EPROM Access Access ROM E2PROM SRAM FIFO Programmable ROM FLASH DRAM LIFO Shift Register EPROM - Erasable Programmable ROM SRAM - Static Random Access Memory E2PROM - Electrically Erasable DRAM - Dynamic Random Access Memory Programmable ROM FIFO - First-In First-Out LIFO - Last-In First-Out Institute of Microelectronic 17: Semiconductor Memories Systems 3 Random Access Memory Array Organization Memory array • Memory storage cells • Address decoders Each memory cell • stores one bit of binary information (”0“ or ”1“ logic) • shares common connections with other cells: rows, columns Institute of Microelectronic 17: Semiconductor Memories Systems 4 Read Only Memory - ROM • Simple combinatorial Boolean network which produces a specific output for each input combination (address) • ”1“ bit stored - absence of an active transistor • ”0“ bit stored - presence of an active transistor • Organized in arrays of 2N words • Typical applications: • store the microcoded instructions set of a microprocessor • store a portion of the operation system for PCs • store the fixed programs for -
Semiconductor Memories
SEMICONDUCTOR MEMORIES Digital Integrated Circuits Memory © Prentice Hall 1995 Chapter Overview • Memory Classification • Memory Architectures • The Memory Core • Periphery • Reliability Digital Integrated Circuits Memory © Prentice Hall 1995 Semiconductor Memory Classification RWM NVRWM ROM Random Non-Random EPROM Mask-Programmed Access Access 2 E PROM Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM Digital Integrated Circuits Memory © Prentice Hall 1995 Memory Architecture: Decoders M bits M bits S S0 0 Word 0 Word 0 S1 Word 1 A0 Word 1 S2 Storage Storage s Word 2 Word 2 d Cell A1 Cell r r o e d W o c N AK-1 e S D N-2 Word N-2 Word N-2 SN_1 Word N-1 Word N-1 Input-Output Input-Output (M bits) (M bits) N words => N select signals Decoder reduces # of select signals Too many select signals K = log2N Digital Integrated Circuits Memory © Prentice Hall 1995 Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2L-K Bit Line Storage Cell AK r e d Word Line AK+1 o c e D AL-1 w o R M.2K Sense Amplifiers / Drivers Amplify swing to rail-to-rail amplitude A 0 Column Decoder Selects appropriate AK-1 word Input-Output (M bits) Digital Integrated Circuits Memory © Prentice Hall 1995 Hierarchical Memory Architecture Row Address Column Address Block Address Global Data Bus Control Block Selector Global Circuitry Amplifier/Driver I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings Digital Integrated Circuits Memory © Prentice Hall 1995 Memory Timing: Definitions -
Introduction to Advanced Semiconductor Memories
CHAPTER 1 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES 1.1. SEMICONDUCTOR MEMORIES OVERVIEW The goal of Advanced Semiconductor Memories is to complement the material already covered in Semiconductor Memories. The earlier book covered the fol- lowing topics: random access memory technologies (SRAMs and DRAMs) and their application to specific architectures; nonvolatile technologies such as the read-only memories (ROMs), programmable read-only memories (PROMs), and erasable PROMs in both ultraviolet erasable (UVPROM) and electrically erasable (EEPROM) versions; memory fault modeling and testing; memory design for testability and fault tolerance; semiconductor memory reliability; semiconductor memories radiation effects; advanced memory technologies; and high-density memory packaging technologies [1]. This section provides a general overview of the semiconductor memories topics that are covered in Semiconductor Memories. In the last three decades of semiconductor memories' phenomenal growth, the DRAMs have been the largest volume volatile memory produced for use as main computer memories because of their high density and low cost per bit advantage. SRAM densities have generally lagged a generation behind the DRAM. However, the SRAMs offer low-power consumption and high-per- formance features, which makes them practical alternatives to the DRAMs. Nowadays, a vast majority of SRAMs are being fabricated in the NMOS and CMOS technologies (and a combination of two technologies, also referred to as the mixed-MOS) for commodity SRAMs. 1 2 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES MOS Memory Market ($M) Non-Memory IC Market ($M) Memory % of Total IC Market 300,000 40% 250,000 30% 200,00U "o Q 15 150,000 20% 2 </> a. o 100,000 2 10% 50,000 0 0% 96 97 98 99 00 01* 02* 03* 04* 05* MOS Memory Market ($M) 36,019 29,335 22,994 32,288 49,112 51,646 56,541 70,958 94,541 132,007 Non-Memory IC Market ($M) 78,923 90,198 86,078 97,930 126,551 135,969 148,512 172,396 207,430 262,172 Memory % of Total IC Market 31% . -
A Study About Non-Volatile Memories
Preprints (www.preprints.org) | NOT PEER-REVIEWED | Posted: 29 July 2016 doi:10.20944/preprints201607.0093.v1 1 Article 2 A Study about Non‐Volatile Memories 3 Dileep Kumar* 4 Department of Information Media, The University of Suwon, Hwaseong‐Si South Korea ; [email protected] 5 * Correspondence: [email protected] ; Tel.: +82‐31‐229‐8212 6 7 8 Abstract: This paper presents an upcoming nonvolatile memories (NVM) overview. Non‐volatile 9 memory devices are electrically programmable and erasable to store charge in a location within the 10 device and to retain that charge when voltage supply from the device is disconnected. The 11 non‐volatile memory is typically a semiconductor memory comprising thousands of individual 12 transistors configured on a substrate to form a matrix of rows and columns of memory cells. 13 Non‐volatile memories are used in digital computing devices for the storage of data. In this paper 14 we have given introduction including a brief survey on upcoming NVMʹs such as FeRAM, MRAM, 15 CBRAM, PRAM, SONOS, RRAM, Racetrack memory and NRAM. In future Non‐volatile memory 16 may eliminate the need for comparatively slow forms of secondary storage systems, which include 17 hard disks. 18 Keywords: Non‐volatile Memories; NAND Flash Memories; Storage Memories 19 PACS: J0101 20 21 22 1. Introduction 23 Memory is divided into two main parts: volatile and nonvolatile. Volatile memory loses any 24 data when the system is turned off; it requires constant power to remain viable. Most kinds of 25 random access memory (RAM) fall into this category.