Chapter 3 Semiconductor Memories

Chapter 3 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline  Introduction  Random Access Memories  Content Addressable Memories  Read Only Memories  Flash Memories <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">2</li></ul>Advanced Reliable Systems (ARES) Lab. Overview of Memory Types Semiconductor Memories Read/Write Memory or Random Access Memory (RAM) Read Only Memory (ROM) Random Access Memory (RAM) Non-Random Access Memory (RAM) •Mask (Fuse) ROM •Programmable ROM (PROM) •Erasable PROM (EPROM) •Electrically EPROM (EEPROM) •Flash Memory •Ferroelectric RAM (FRAM) •Magnetic RAM (MRAM) •FIFO/LIFO •Shift Register •Content Addressable Memory (CAM) •Static RAM (SRAM) •Dynamic RAM (DRAM) •Register File <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">3</li></ul>Advanced Reliable Systems (ARES) Lab. Memory Elements – Memory Architecture  Memory elements may be divided into the following categories Random access memory Serial access memory Content addressable memory  Memory architecture 2m+k bits row decoder row decoder 2n-k words row decoder row decoder column decoder kcolumn mux, sense amp, write buffers n-bit address 2m-bit data I/Os <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">4</li></ul>Advanced Reliable Systems (ARES) Lab. 1-D Memory Architecture S0 S0 S1 S2 S3 Word0 Word0 S1 S2 S3 Word1 Word2 Word1 Word2 A0 A1 Ak-1 Sn-2 Sn-1 Sn-2 Sn-1 Storage element Wordn-2 Wordn-1 Wordn-2 Wordn-1 m-bit m-bit Input/Output Input/Output n select signals are reduced to k address signals: A0-Ak-1 n select signals: S0-Sn-1 <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">5</li></ul>Advanced Reliable Systems (ARES) Lab. Memory Architecture S0 Word0 Wordi-1 S1 A0 A1 Ak-1 Sn-1 Wordni-1 A0 Aj-1 Column Decoder Sense Amplifier Read/Write Circuit m-bit Input/Output <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">6</li></ul>Advanced Reliable Systems (ARES) Lab. Hierarchical Memory Architecture Input/Output <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">7</li></ul>Advanced Reliable Systems (ARES) Lab. SRAM Block Diagram [A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.] <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">8</li></ul>Advanced Reliable Systems (ARES) Lab. Conceptual 2-D Memory Organization Address Memory Cell Column decoder Data I/Os <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">9</li></ul>Advanced Reliable Systems (ARES) Lab. Memory Elements – RAM Generic RAM circuit Clocks Bit line conditioning RAM Cell n-1:k Write Sense Amp, Column Mux, Write Buffers k-1:0 Clocks Address <ul style="display: flex;"><li style="flex:1">write data </li><li style="flex:1">read data </li></ul><ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">10 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – SRAM Cells 6-T SRAM cell word line <ul style="display: flex;"><li style="flex:1">bit </li><li style="flex:1">- bit </li></ul>4-T SRAM cell word line <ul style="display: flex;"><li style="flex:1">bit </li><li style="flex:1">- bit </li></ul><ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">11 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – DRAM Cells 4-T dynamic RAM (DRAM) cell word line <ul style="display: flex;"><li style="flex:1">bit </li><li style="flex:1">- bit </li></ul>3-T DRAM cell Read Write Read data Write data <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">12 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – DRAM Cells 1-T DRAM cell <ul style="display: flex;"><li style="flex:1">word line </li><li style="flex:1">word line </li></ul>Vdd or <ul style="display: flex;"><li style="flex:1">bit </li><li style="flex:1">bit </li></ul>Vdd/2 Layout of 1-T DRAM (right) Vdd word line bit <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">13 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – DRAM Retention Time Write and hold operations in a DRAM cell WL=1 WL=0 +-on +-off <ul style="display: flex;"><li style="flex:1">Cs </li><li style="flex:1">Vs </li></ul>+-<ul style="display: flex;"><li style="flex:1">Cs </li><li style="flex:1">Vs </li></ul>Input Vdd <ul style="display: flex;"><li style="flex:1">Write Operation </li><li style="flex:1">Hold </li></ul>Vs Vmax VDD Vtn Qmax  Cs (VDD Vtn ) <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">14 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – DRAM Retention Time Charge leakage in a DRAM Cell Vs(t) Vmax V1 WL=0 IL Minimum logic 1 voltage +-off Cs Vs(t) tth dQs IL  ( ) dt dVs dt IL  Cs ( ) Vs IL  Cs ( ) t Cs th| t | ( )Vs IL <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">15 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – DRAM Refresh Operation As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the hold time is 501015 <ul style="display: flex;"><li style="flex:1">th </li><li style="flex:1">1 0.5s </li></ul>1109 Memory units must be able to hold data so long as the power is applied. To overcome the charge leakage problem, DRAM arrays employ a refresh operation where the data is periodically read from every cell, amplified, and rewritten. The refresh cycle must be performed on every cell in the array with a minimum refresh frequency of about 1f refres h 2th <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">16 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – DRAM Read Operation WL=1 IL +-on <ul style="display: flex;"><li style="flex:1">Cbit </li><li style="flex:1">Cs </li><li style="flex:1">Vs </li><li style="flex:1">Vf </li></ul>+-Vbit Vf Qs  CsV s Qs  CsVf  CbitVf Cs Cs  Cbit Vf  ( )Vs This shows that Vf<Vs for a store logic 1. In practice, Vf is usually reduced to a few tenths of a volt, so that the design of the sense amplifier becomes a critical factor <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">17 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – SRAM Read Operation Vdd precharge precharge bit, -bit precharge word line word data - bit bit data <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">18 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – SRAM Read Operation Vdd-Vtn precharge precharge bit, -bit precharge word line Vdd word data - bit bit data <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">19 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – SRAM Read Operation bit, -bit word data <ul style="display: flex;"><li style="flex:1">- bit </li><li style="flex:1">bit </li></ul>load V2 pass sense - sense + V1 pulldown sense common <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">20 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Write Operation N5 N6 write data word write word <ul style="display: flex;"><li style="flex:1">N3 </li><li style="flex:1">N4 </li></ul>bit, -bit <ul style="display: flex;"><li style="flex:1">- bit </li><li style="flex:1">bit </li></ul><ul style="display: flex;"><li style="flex:1">N1 </li><li style="flex:1">N2 </li></ul>write cell, -cell write data <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">21 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Write Operation <ul style="display: flex;"><li style="flex:1">- bit </li><li style="flex:1">bit </li></ul>Pbit -cell cell 0V 5V - write write Nbit <ul style="display: flex;"><li style="flex:1">ND </li><li style="flex:1">PD </li></ul>write-data <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">22 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Read Stability [A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.] <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">23 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Write Stability [A. Pavlov and M. Sachdev, “Power-Aware SRAM Design and Test”, 2008, Springer.] <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">24 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Row Decoder word<3> word<2> word<1> word<0> word<0> word<1> word<2> word<3> <ul style="display: flex;"><li style="flex:1">a<0> </li><li style="flex:1">a<0> </li></ul><ul style="display: flex;"><li style="flex:1">a<1> </li><li style="flex:1">a<1> </li></ul><ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">25 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Row Decoder word a1 <ul style="display: flex;"><li style="flex:1">a0 </li><li style="flex:1">a0 </li><li style="flex:1">a1 </li><li style="flex:1">a2 </li><li style="flex:1">a3 </li></ul>Complementary AND gate Pseudo-nMOS gate <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">26 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Row Decoder Symbolic layout of row decoder output <ul style="display: flex;"><li style="flex:1">Vss </li><li style="flex:1">Vdd </li></ul>Vss <ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">27 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Row Decoder Symbolic layout of row decoder Vdd output Vss <ul style="display: flex;"><li style="flex:1">a3 </li><li style="flex:1">-a3 </li><li style="flex:1">a2 </li><li style="flex:1">-a2 </li><li style="flex:1">a1 </li><li style="flex:1">-a1 </li><li style="flex:1">a0 </li></ul><ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">28 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Row Decoder Predecode circuit word<7> word<6> word<5> word<4> word<3> word<2> word<1> word<0> <ul style="display: flex;"><li style="flex:1">a2 </li><li style="flex:1">a1 </li><li style="flex:1">a0 </li></ul><ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">29 </li></ul>Advanced Reliable Systems (ARES) Lab. RAM – Row Decoder Actual implementation a0 a4 a3 a2 word a1 -a0 clk Pseudo-nMOS example <ul style="display: flex;"><li style="flex:1">a0 </li><li style="flex:1">word </li></ul><ul style="display: flex;"><li style="flex:1">a1 </li><li style="flex:1">a2 </li><li style="flex:1">en </li></ul><ul style="display: flex;"><li style="flex:1">Jin-Fu Li, EE, NCU </li><li style="flex:1">30 </li></ul>Advanced Reliable Systems (ARES) Lab.

Chapter 3 Semiconductor Memories

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