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Emerging Memory Technologies As the Way to Better Computing

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Emerging Memory Technologies As the Way to Better Computing TTIC, 2017, Vol.1, 61-67 Emerging Memory Technologies as the way to better Computing Subhendu Mondal Department of Electronics and Communication Engineering, Techno India University, EM-4, Salt Lake City, Sector V, Kolkata, West Bengal 700091 ABSTRACT memory subsystem. The memory subsystem has a well-known memory hierarchy: Today static This article will introduce the reader to the random-access memory (SRAM), dynamic emerging non-volatile memory (NVM) random-access memory (DRAM), and flash are the technologies, such as MRAM, PCRAM. NVM mainstream memory technologies serving as cache, technologies combine the density of DRAM,the main memory, and storage memory. Though, these speed of SRAM,and the non-volatility of Flash emerging NVM technologies face challenges from memory, these technologies are very attractive to aspects of process compatibility, manufacturing future generation universal memories. Emerging yield, performance variability, and reliability, these NVM cell characteristics are summarized in this different emerging NVM devices have different article. The ideal characteristics for a memory application spaces in the memory hierarchy due to device include fast write/read speed (<ns), low their unique characteristics. Beyond the operation voltage(<1 V), low energy consumption conventional memory applications, aerospace (~fJ/b for write/read), long data retention time electronics applications, embedded applications are (>10 years), long write/read cycling endurance also using emerging NVM. (>1017 cycles), and excellent scalability (<10 nm)[1]. Nevertheless, it is almost impossible to 2. Different NVMs in today’s world satisfy all of these ideal characteristics in a single These emerging NVM technologies have some “universal” memory device. Several resistance- common features: these are non-volatile two- based emerging NVM technologies have been terminal devices, and the different states are pursued toward achieving part of these ideal obtained by the switching between a high characteristics. The emerging NVM candidates resistance state (HRS) or “off state” and a low include STT-MRAM [2],PCRAM [3], RRAM [4], resistance state (LRS) or “on state”. The switching N-RAM, SONOS and FRAM. from “off state” to “on state” is called “set,” and the switching from “on state” to “off state” is called Keywords: NVM, CB RAM, SONOS, STTMRAM, “reset.” The transition between the two states can RRAM, N-RAM, PCM, PRAM, FRAM, MRAM, Van be triggered by an electric voltage or current pulse der Waals. change. However, the detailed switching physics is 1. Introduction different for different NVMs. As for example, STT-MRAM relies on the parallel configuration This article introduces the basics of emerging and antiparallel configuration of two ferromagnetic non-volatile memory (NVM) technologies layers separated by a thin tunnelling insulator layer. including conductive bridging RAM (CBRAM), The parallel configuration corresponds to LRS and Silicon-Oxide-Nitride- Oxide Silicon SONOS), anti-parallel configuration corresponds to HRS. spin-transfer-torque magnetic random-access PCRAM relies on chalcogenide materials to switch memory (STTMRAM), phase-change random between the crystalline phaseand the amorphous access memory (PCRAM), Nano-RAM, phase. The crystalline phase corresponds to LRS Ferroelectric RAM, Magnetic random-access and the amorphous phase corresponds to HRS, memory (MRAM) and resistive random-access where RRAM relies on the formation and the memory (RRAM). The functionality and rupture of conductive filaments in the insulator performance of today’s computing system are between two electrodes. increasingly dependent on the characteristics of the 61 TTIC, 2017, Vol.1, 61-67 Fig1: A sample pictorial view of a NVM. As compared to SRAM, STTMRAM has an (enraging) of a metallic conductive filament advantage of a smaller cell area, while STT- between the two terminals of the cell. MRAM has maintained low programming voltage, fast write/read speed, and long endurance. Thus, (a) Filament formation: PMC rely on the STT-MRAM is attractive as a replacement for formation of a metallic conductive filament to embedded memories (e.g., SRAM or embedded transition to a low resistance state (LRS). The DRAM) in the last-level cache [5]. As compared to filament is created by applying a +ve voltage flash, PCRAM/RRAM is attractive due to its lower bias(V) to the anode contact (active metal) while programming voltage and faster write/read speed. grounding the cathode contact (inert metal). The Thus, the PCRAM/RRAM is attractive as a +ve bias oxidizes the active metal (M): replacement for NOR flash for code storage and, M --> M+ + e- more ambitiously, to replace NAND flash for data The applied bias generates an electric field storage [6]. between the metal contacts. The ionised (oxidized) Conductive Bridging RAM (CBRAM) metal ions migrate along the electric field towards the cathode contact. At Cathode contact, the metal The programmable metallization cell, or PMC is ions are reduced: a non-volatile computer memory developed at M+ + e- --> M Arizona State University, Infineon Technologies As the active metal deposits on the cathode, the refers to it as conductive bridging RAM or electric field increases between the anode and CBRAM, developed to replace the widely used deposit (E= -V/d). The filament will grow to Flash Memory. connect to anode within a few nanoseconds. Once Its characteristics are: the voltage is removed, the conductive filament 1. PMC/CBRAM is a two terminal resistive will remain, leaving the device in LRS. memory technology. It is an electrochemical metallization memory that relies on redox reactions Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) to form and dissolve a conductive filament. 2. The states of the device are determined by the It is a type of non-volatile computer memory resistance across the two terminals. The existence (NVM) closely related to Flash RAM. It is one of of a filament between the terminals produces low charge trap flash variant. Where the mainstream resistance state (LRS) while the absence of a flash memory uses polysilicon for charge storage filament results in a high resistance state (HRS). material, SONOS uses of Silicon nitride (Si3N4) 3. A PMC device is made of two solid for the charge storage material. electrodes, one relatively inert(eg., tungsten or nickel), the other electronically active (e.g..,silver A SONOS memory cell is formed from a or copper) with thin film of solid electrolyte standard polysilicon N-channel MOSFET transistor between them. with the addition of a small silicon nitride layer Now let us have a brief overview of the different inside the transistor gate oxide. The oxide/nitride NVMs introduced above. sandwich typically consists of a 2 nm thick oxide lower layer, a 5 nm thick silicon nitride middle Device Operation: layer and 5-10 nm oxide upper layer. The resistance state of PMC is controlled by the formation (Programming) and dissolution 62 TTIC, 2017, Vol.1, 61-67 Table 1: Device characteristics of mainstream and emerging memory technology [7] When the polysilicon control gate is biased Resistive Random-Access Memory (RRAM) positively, electrons from the transistor source and drain regions tunnel though the oxide layer and get Resistive random-access memory (RRAM or trapped in the silicon nitride. This results an energy ReRAM) is a type of non-volatile random-access barrier between the drain and the source, raising the computer memory (NVM) that works by changing threshold voltage Vt. By applying a negative bias the resistance across a dielectric solid-state material on the control gate, the electrons can be removed often referred to as a memristor. This technology again. After storing or removing electrons from the has some similarities with conductive-bridging cell, the controller can measure the state of the cell RAM (CBRAM) and Phase-change memory by giving a small voltage across the source-drain (PCM). nodes; If current is seen in the cell, it must be in the CBRAM involves one electrode providing ions ‘NO TRAPPED ELECTRONS” state, which is that dissolve readily in an electrolyte material, considered as logical “1”. If no current flows, the while PCM involves generally sufficient Joule cell must be in the “TRAPPED ELECTRONS” heating to effect amorphous-to-crystalline or state, which is considered as logical “0” state. The crystalline-to-amorphous phase change. On the needed voltages are normally about 2 V for erased other hand, RRAM involves generally defects in a state and around 4.5 V for the programmed state. thin oxide layer, known as “OXYGEN VACANCIES”, which can subsequently change and drift under an electric field. The motion of oxygen ions and vacancies in the in the oxide would be analogous to the motion of electrons and holes in semiconductor. A dielectric us used which is normally insulating. Application of a sufficiently high voltage, the dielectric can be made to conduct through a filament or conduction path. The filament (i.e., the conduction path) can arise from different Fig 2: Schematic drawing of a SONOS memory mechanisms including vacancy or metal defect cell migration. Once the conduction path is formed, it Nano-RAM/NRAM 63 TTIC, 2017, Vol.1, 61-67 Nano-RAM or NRAM is a type of non-volatile may be reset (broken, causing high resistance in random-access computer memory (NVM) based on the dielectric) or set (re-formed, causing low the position of carbon nanotubes (CNTs) deposited resistance in the dielectric) by another voltage. on a chip-like substrate. The small size of the nanotubes. Nantero also refers to it as NRAM. Phase-change memory/PCM/PRAM Initially, NRAM technology was a three-terminal Phase-change memory is a type of non-volatile semiconductor device. A third terminal was there to random-access computer memory (NVM). PRAMs switch the memory cell between memory states. exploit the unique behaviour of chalcogenide glass. The second generation NRAM technology is a two- In the older generation of PCM, a heating element terminal memory cell. generally made of TiN, would use.
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