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Scalability and Reliability of Phase Change Memory SCALABILITY AND RELIABILITY OF PHASE CHANGE MEMORY A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY SangBum Kim Aug 2010 © 2010 by SangBum Kim. All Rights Reserved. Re-distributed by Stanford University under license with the author. This work is licensed under a Creative Commons Attribution- Noncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/ This dissertation is online at: http://purl.stanford.edu/kk866zc2173 ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Philip Wong, Primary Adviser I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Yi Cui I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Yoshio Nishi Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost Graduate Education This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives. iii Abstract Various memory devices are being widely used for a wide range of applications. There has not been any universal memory device so far because each memory device has a unique set of features. Large performance gaps in various dimensions of features between memory devices and a new set of features required by new electronic systems such as portable electronics open up new opportunities for new memory devices to emerge as mainstream memory devices. Besides, the imminent scaling limit for existing mainstream memory devices also motivates development and research of new memory devices which can meet the increasing demand for large memory capacity. Phase change memory (PCM) is one of the most promising emerging memory devices. It has the potential to combine DRAM-like features such as bit alteration, fast read and write, and good endurance and Flash-like features such as non-volatility and a simple structure. PCM is expected to be a highly scalable technology extending beyond scaling limit of existing memory devices. Prototypical PCM chips have been developed and are being tested for targeted memory applications. However, understanding of fundament physics behind PCM operation is still lacking because the key material in PCM devices, the chalcogenide, is relatively new for use in solid state devices. Evaluation and development of PCM technology as successful mainstream memory devices require more study on PCM devices. This thesis focuses on issues relevant to scalability and reliability of PCM which are two of the most important qualities that new emerging memory devices should iv demonstrate. We first study basic scaling rule based on thermoelectric analysis on the maximum temperature in a PCM cell and show that both isotropic and non-isotropic scaling result in constant programming voltage. The minimum programming voltage is determined by material properties such as electrical resistivity and thermal conductivity regardless of the device size. These results highlight first-order principles governing scaling rules. In the first-order scaling rule analysis, we assume that material properties are constant regardless of its physical size. However, when materials are scaled down to the nanometer regime, material properties can change because the relative contribution from the surface property to the overall system property increases compared to that from the bulk property. We study scaling effect on material property and device characteristics using a novel device structure – a PCM cell with a pseudo electrode. With the pseudo electrode PCM cell, we can accurately relate the observed properties to the amorphous region size. We show that threshold switching voltage scales linearly with thickness of the amorphous region and threshold switching field drifts in time after programming. We also show that the drift coefficient for resistance drift stays the same for scaled devices. These property scaling results provide not only estimates for scaled device characteristics but also clues for modeling and understanding mechanisms for threshold switching and drift. To make scaled memory cells in an array form, not only memory device elements but also selection devices need to be scaled. PCM requires relatively large programming current, which makes it challenging to scale down selection devices. We integrate Ge nanowire diodes as selection devices in search for new candidates for high density v PCM. Ge nanowire diode provides on/off ratio of ~100 and small contact area of 40 nm in diameter which results in programming current below 200 µA. The processing temperature for Ge nanowire diode is below 400 ºC, which makes Ge nanowire diode a potential enabler for 3D integration. As memory devices are scaled down, more serious reliability issues arise. We study the reliability of PCM using a novel structure – micro-thermal stage (MTS). The high- resistance-state (RESET) resistance and threshold switching voltage are important device characteristics for reliable operation of PCM devices. We study the drift behavior of RESET resistance and threshold switching voltage and its temperature dependence using the MTS. Results show that the drift coefficient increases proportionally to annealing temperature until it saturates. The analytical drift model for time-varying annealing temperature that we derive from existing phenomenological drift models agrees well with the measurement results. The analytical drift model can be used to estimate the impact of thermal disturbance (program disturbance) on RESET resistance and threshold switching voltage. Thermal disturbance is a unique disturbance mechanism in PCM which is caused by thermal diffusion from a cell being programmed. The MTS can effectively emulate the short heat pulse, enabling detailed study on thermal disturbance impact on cell characteristics. We show that random thermal disturbance can result in at least 25 and 100 % variations in RESET resistance and threshold switching voltage. The existing model on how to add up the impact of thermal disturbance on crystallization is experimentally verified using the MTS. Based on measurement and modeling results, vi we propose a new programming scheme to improve stability of PCM with a short-time annealing pulse. vii Acknowledgments The work presented in this dissertation is made possible by eager support from various people and close and productive collaboration with numerous researchers. I deeply appreciate the fact that I was able to meet these professors, advisors, colleagues, friends, and companions while I was pursuing the Ph.D. degree at Stanford University. First of all, I feel deeply grateful to my academic advisor, Prof. H.-S. Philip Wong for his support and leadership. He has been guiding me to the right direction to find answers for complicated problems and provided valuable and essential resources required for the in-depth research. Especially, he encouraged me and devoted himself to participate in a multidisciplinary collaborative research. This was extremely beneficial for research projects on phase change memory, which is the main subject of this dissertation because the phase change memory research requires a broad range of knowledge spanning electrical engineering, material science, and thermal physics. I am very proud of myself for being one of his first seven students since he had launched the Nanoelectronics group at Stanford University in 2004. I also would like to acknowledge Prof. Yoshio Nishi for not only being on my dissertation reading committee but also helping me to begin my research in the semiconductor device area. During my first summer quarter in Stanford, he generously allowed me, who had no experience in the device fabrication at the time, to work on the plasma-activated wafer bonding project, which lead me to learn the nature of semiconductor research and generated more interest in me to be determined for the viii semiconductor device research. Since then, he has been very willing to provide many valuable ideas and advise on the projects that I worked on. I would like to thank Prof. Yi Cui and Prof. Kenneth Goodson for enlightening me on important aspects of phase change memory which were little known to me at the beginning. Their knowledge and expertise in thermal transport and material science were crucial for understanding all the details of phase change memory. I wish to acknowledge the significant contribution and collaboration of various scientists and researchers on work presented in this dissertation. Dr. Mehdi Asheghi introduced the importance and usefulness of the micro-thermal stage in the phase change memory research and provided constructive suggestions in designing the micro-thermal stage. Dr. Byoung-Jae Bae proposed the novel idea for 1D thickness scaling study and collaborated on the project. Yuan Zhang collaborated on fabrication and characterization of the phase change memory cell with a nanowire diode. As the closest colleague in the same research group, intellectual interaction with her was an indispensable resource for most
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