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208 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure Ki-Tae Park, Myounggon Kang, Soonwook Hwang, Doogon Kim, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jaehoon Jang, Han-Soo Kim, Yeong-Taek Lee, Soon-Moon Jung, and Changhyun Kim, Senior Member, IEEE

Abstract—A 3-dimensional double stacked 4 Giga-bit multi-level NAND device by using conventional linear scaling method cell NAND flash memory device with shared bitline structure will face severe scaling barriers such as increasing cell-to-cell have successfully developed. The device is fabricated by 45 nm interference and decreasing coupling ratio at under 20 nm tech- floating-gate CMOS and single-crystal Si layer stacking technologies. To support fully compatible device performance and nology node [3]. Therefore, a new innovated and breakthrough characteristics with conventional planar device, shared bit- technology to solve these issues is deadly required. As one of line architecture including Si layer-dedicated decoder and Si the potential solutions, three-dimensional (3-D) memories have layer-compensated control schemes are also developed. By using regained attention for recent several years. the architecture and the design techniques, a memory cell size of 0.0021 mP bit per unit feature area which is smallest cell size So far, many 3-D memory technologies have been proposed and 2.5 MB/s program throughput with 2 kB page size which is and evaluated. They can be simply categorized into two dif- almost equivalent performance compared to conventional planar ferent technologies as follows, in terms of cost and performance. device are realized. One is package-based wafer or chip stacking 3-D memory tech- Index Terms—Layer-compensated control, NAND flash, shared nologies that is able to provide high performance and is fully bitline architecture, Si layer-dedicated decoder, single-crystal Si compatible with conventional planar device [4], [5]. However, layer stacking, 3-dimensional device. this 3-D technology is difficult to realize high density memory while serving low cost due to decreasing number of die on the I. INTRODUCTION wafer. On the other hand, thin-film based cell stacking technology such as laser-crystallized poly-Si based 3-D device has a HE ever increasing demand for NAND flash memory has great potential to realize both high density and low cost [6]–[8]. T lead to ever scaled down in NAND technology which But it is hard to provide compatible performance to conven- has achieved with double density every year in recent year. tional NAND device due to its inherent low electrical charac- Fig. 1 shows mass-produced NAND technology node and used teristics of thin-film memory cell device. Among the proposed lithography technology which have traced for past several 3-D memory technologies, the recently developed single-crystal years. As further scaling NAND device with the current scaling Si layer stacking is a very attractive method which satisfies both pace, however, two big challenges to overcome scaling NAND device performance and fabrication cost [9], [10]. A 3-D double are expected in near future [1]. One is uncertainty of future stacked NAND flash memory cell implemented by the single- lithography technology. So far, lithography for each generation crystal Si layer stacking was successfully demonstrated using has been available by improving its patter resolution with phase 63 nm CMOS technology [10]. shift mask (PSM) and optical proximity correction (OPC) tech- In this paper, we present a 3-D double stacked 4 Gb MLC niques. For recent 50 nm and 40 nm node NAND device, ArF (Multi-Level Cell) NAND flash memory device with shared lithography technology with immersion technique has been BL (Bit Line) structure, which realized a memory cell size used, and for 30 nm node NAND device, another technique of 0.0021 m bit per unit feature area [11]. The device like self-aligned double pattering (SADP) using the ArF lithog- is designed to support 3-D stacking and fabricated by the raphy was proposed [2]. However, to pattern under-30 nm node single-crystal Si layer stacking and 45 nm floating-gate CMOS NAND device, a new lithography technology like Extreme technologies. By using special design techniques such as Ultraviolet (EUV) should be available. But, we expect it is Si-layer-dedicated decoder and layer-compensated control still uncertain when it will be available. The other challenge is scheme, the 3-D device is able to increase double density uncertainty of NAND device scaling itself. It is expected that physically without performance degradation compared to conventional planar NAND flash device. This paper is organized as follows. 3-D stacked NAND Manuscript received March 24, 2008; revised June 24, 2008. Current version device and its chip architecture are described in Section II. published December 24, 2008. Some important circuit designs for 3-D NAND are presented The authors are with the Semiconductor R&D Center, Memory Business, in Section III and its performances based on measured results Samsung Electronics Co., Ltd., Gyeonggi-Do 445-701, Korea (e-mail: kt21c. [email protected]). are described in Section IV. Finally, the conclusion is given in Digital Object Identifier 10.1109/JSSC.2008.2006437 Section V.

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Fig. 1. NAND technology node and used lithography technology.

Fig. 2. Cross-sectional view and top layout view of the 3-D stacked NAND string.

II. THREE-DIMENSIONAL STACKED NAND AND CHIP ARCHITECTURE Fig. 2 shows a cross-sectional view and a top layout view of the 3-D stacked NAND string. The NAND cell on the second Si layer which is identical to NAND cell on the first Si layer is formed after fabricating NAND cell on the first Si layer. All metals including not only bitline (BL) and common source line (CSL) but also 2 aluminum metals for interconnecting are formed on the second Si layer as shown in the figure. Because two memory cells are stacked vertically, simply twice memory density can be realized within unit feature size. In addition, the memory cell on the second Si layer is also formed on single-crystal Si layer so that its electrical characteristics is equivalent to that of conventional planar NAND cell. Due to its higher height between BL and surface of first Si layer compared to conventional planar NAND device, however, a relative larger Fig. 3. Micrograph of the fabricated 3-D stacked 4 Gb MLC NAND flash. contact-via on the second Si layer is required. Fig. 3 shows a micrograph of the 3-D stacked 4 Gb MLC NAND flash memory chip. The chip was fabricated by 45 nm decoders which are placed at both sides of the memory array are floating-gate NAND and the single-crystal Si layer stacking dedicated to each MAT. A 2 kB page buffer, which is shared by technologies. The device is composed of two stacked Si layers, the two MATs, is located at the bottom side of memory array. each Si layers containing a 2 Gb MLC memory array (MAT1 Except MAT2 that was fabricated on the second Si layer, MAT1 for first Si layer, MAT2 for second Si layer) consisting of 1 k and all peripheral circuitry including high voltage generation blocks with a page size of (2 kB 64). Two word-line (WL) circuits are formed on the first Si layer.

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Fig. 5. Simpliﬁed chip architecture.

Fig. 4. NAND string with dummy cells ([14]).

As shown in the Fig. 4, 32-cell string with 2 dummy cells is used to reduce abnormal disturbances of edge memory cells ( and in Fig. 4) which are adjacent to select transistors in NAND string in the 3-D stacked NAND device. The abnormal disturbances are caused by hot electron injec- tion induced by band-to-band tunneling at junction of the select transistor [12] and boosted channel potential leakage due to WL-WL capacitive coupling noise [13]. By inserting additional memory cell used as dummy between the select transistor and edge memory cell and applying proper bias voltages on the Fig. 6. (a) Single WL-decoder, (b) Si-layer dedicated WL-decoder. dummy cell during operations, the abnormal disturbances can be reduced signiﬁcantly [14]. The architecture of the chip is shown in Fig. 5. Basically, (CSL) and wells of memory arrays are electrically connected memory array is formed on each Si layer and all peripheral cir- between the MATs and driven by CSL and well driver circuits, cuitry are formed on the bulky ﬁrst Si layer. BL of the memory respectively. cells are formed on the MAT2 and shared with MAT1 using con- By using the shared BL structure, the page buffer is able to tact-vias which are formed through the second Si layer. WL of access both MAT1 and MAT2 so that the BL loading of the memory cells is each formed on the MAT. Common source lines 3-D device is almost comparable to the loading of conventional

Fig. 7. 3-D block and column redundancy scheme.

planar device. The extra loading due to the 3-D stacking of the III. DESIGN FOR THREE-DIMENSIONAL STACKED NAND memory arrays is less than 3% of the total BL loading. There- fore, no performance penalty caused by the BL loading arises Fig. 8 shows operation bias conditions of the 3-D stacked in the 3-D stacked NAND device. On the other hand, a perfor- NAND flash memory cell. One basic design consideration of the mance of erase operation of 3-D device can be degraded by an 3-D stacked NAND device is how to apply the same bias volt- increased parasitic well capacitance of 3-D stacking memory ages as unselected blocks of conventional planar cells to unse- compared to conventional NAND planar device. However, its lected 3-D stacked memory cells. During read and program op- degradation which is a range of several hundreds micro-second erations, the required bias voltages are applied only to selected can be relatively negligible because of a long erase time which blocks of MATs while string select lines (SSL) of unselected is typically a range of several millisecond. blocks, including all blocks of the unselected MAT are biased to WLs of memory arrays of both MAT1 and MAT2 are driven ground. Particularly during erase, since wells of memory arrays by the layer-dedicated WL decoder. It also provides comparable of both MAT1 and MAT2 are electrically connected together, a performance associated with WL loading to the conventional high voltage like 18 V is applied to both selected and unselected planar device. As another benefit of the structure, no additional MATs. To avoid unwanted Fowler-Nordheim (F-N) erasing for program and read disturbances caused by 3-D stacked can be the unselected MAT, all WLs of the unselected MAT are floated, performed. In the case of single WL-decoder structure, addi- just like the WLs of unselected blocks in the selected MAT. This tional electrical program and read voltage stresses are applied can be performed by the layer-dedicated WL decoder which is to unselected memory string as shown in Fig. 6(a). It directly able to control voltages to each MAT independently. As a con- causes to degradation of characteristics of memory cell. On the sequence, the same block size as for conventional planar devices other hands, in the Si-layer dedicated WL-decoder structure, no can be obtained in the 3-D stacked NAND device. additional disturbances occurs during program and read oper- Since the 3-D stacked memory cells of the device are each ations because that only selected memory cells are electrically formed on different Si layers, the memory cell characteristics stressed as same as the conventional planar NAND device, as shown in Fig. 6(b). such as program, erase, and natural cell distribution may be dif- Thanks to the shared BL structure and the Si-layer dedicated ferent across Si layers due to process integration difference be- WL-decoder, conventional redundancy scheme used in planar tween the Si layers [10]. Fig. 9 shows a typical Vth distribu- NAND device can be easily implemented in the 3-D stacked tion of the 3-D stacked NAND device after applying a single NAND device without any extra redundancy area. Fig. 7 shows program pulse. Two different Vth distributions that belong to concept diagram of 3-D redundancy scheme used in the device. each Si layer can be seen. Together, they cause a widening of As conventional planar device, defected memory cells of both the total Vth distribution of the 3-D device. This eventually re- block and column of each MAT are repaired individually (Case sults in a large degradation of program performance with con- ‘A’ in Fig. 7). In addition, the 3-D stacked NAND device also ventional program method. This is because the start voltage of supports interchange block repair between MATs (Case ‘B’ in ISPP (Incremental Step Program Pulse) [15] is typically deter- Fig. 7) to improve block repair efficiency. However, due to the mined by the fastest cell, which is located at rightmost side of shared BL structure, interchange column repair between MATs the Vth distribution. Thus, it causes an increase in the required is not implemented. number of ISPP, which is linearly proportional to the Vth

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Fig. 8. Basic cell operations in 3-D stacked device.

program bandwidth can be simply expended to over 10 MB/s. The layer-compensated control scheme can be also applied for erase operations. The 3-D stacked NAND device is able to support random multiple block erase function as shown in Fig. 11(a). Two ran- domly located blocks, one in each Si layer, can be selected and erased simultaneously. Thus, both Si-layer dedicated WL-decoders are activated in the operation. This improves device performance in continuous mass-block erasing. To compensate for the variation of different layers for the multiple block erase operation, Fowler-Nordheim (F-N) erasing should be applied differently as each blocks. One solution for above problem is to bias well voltage differently depending on the selected Si layer. However, it results in a large area overhead in memory array and power consumption by additional charge pump circuit. There- fore, a new WL modulated erase operation can be performed by the layer compensation control scheme, as shown in Fig. 11(b). With the same erase voltage applied to both wells, a slightly different voltage level, of WLs can be selectively applied in accordance with the Si layers. It leads to reduce erase character- istic difference between Si layers effectively. Additionally, to save power during erase verification for the Fig. 9. Typical memory cell Vth distribution of 3-D stacked NAND. multiple block erase operation, a charge-recycling verification method is used as shown in Fig. 12. In general, BL capacitance distribution of the device, . To reduce the performance degra- of NAND flash is very huge as much as over several hundreds dation, a layer-compensated control scheme is adopted as shown nF. Therefore, charging power for all BLs during erase veri- in Fig. 10. Depending on the location of the MAT (first or second fication is one of major power consumption source of NAND Si layer), program parameters such as start program voltage, erase operation. The erase verify of the block of one of the MATs (MAT2 in Fig. 12) is performed with BL source-fol- stepping voltage and pulse width of ISPP and maximum number lowing. After passing the verification, all selected BLs are al- of ISPP are set optimally using the layer-compensated program ready precharged to a read level voltage, Va. Then, for erase scheme implemented in the 3-D stacked NAND device. As a verify of the block of the other MAT (MAT1 in Fig. 12), the result, the program performance of 2.5 MB/s with 2 kB page precharged read level voltage is used as BL precharging voltage. size, which is almost comparable to the conventional planar de- As a result, the current power of BL precharging during the erase vice, was achieved in the 3-D stacked NAND device. For 8 kB verification is reduced by up to 50%. To ensure erase verification page size which is typically used in recent NAND device, its without erroneous operation that might caused by the difference

Fig. 10. Layer-compensated control scheme.

Fig. 12. Charge recycling veriﬁcation.

IV. PERFORMANCE Fig. 13 shows measured Vth distributions of the fabricated 3-D stacked NAND device. In the conventional program scheme, when applying single program pulses, 17 V with 50 us width, slightly different Vth distributions for each Si layer are observed. After adjusting parameters of the ISPP that are opti- mized for memory array of each Si layer by the implemented layer-compensated control circuit, their Vth distributions are equivalently matched as shown in the figure. It eventually leads to program performances which are almost equivalent to the conventional planar device in the 3-D stacked NAND device. Fig. 14 shows a measured MLC Vth distribution of the 3-D Fig. 11. (a) Diagram and (b) WL modulated erase scheme of random multi- stacked NAND device. With the layer-compensated control and block erase. an improved program scheme to reduce cell-to-cell interference by floating-gate coupling [16], the obtained Vth distribution satisfies the requirements for MLC NAND. Table I summarizes read method, erase verify read with BL source-following is per- features of the 3-D stacked NAND device. It should be noted formed for both MATs at final verification phase. that its device performances such as program, read and erase

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Fig. 13. Measured Vth distributions by (a) conventional control scheme and (b) layer-compensated control scheme.

single-crystal Si layer stacking technologies. It realizes 0.0021 um2/bit per unit feature size which is smallest cell size ever reported. 3-D architectures such as shared BL, Si-layer dedicated WL-decoder and layer-compensated control scheme are proposed and 2.5 MB/s program bandwidth with 2 kB page size as well as read and erase performance, which are all equivalent performance to conventional planar NAND device, are achieved. The proposed 3-D stacked NAND device is expected to be a strong future NAND device which is able to overcome device scaling and lithograph limitation.

ACKNOWLEDGMENT The authors would like to appreciate Kinam Kim for great Fig. 14. Measured MLC Vth distribution of fabricated 3-D stacked NAND. support and Sungsoo Lee, Young-Ho Lim for great design advice and many supports, and also appreciate Hyunkyoung Kim, Jae-Hun Jeong, Seung-Min Kim, Hongshik Kang, Inseok TABLE I SUMMARIZED DEVICE FEATURES Hwang, and entire layout, device, process and testing teams.

REFERENCES [1] K. Kim and G. Jeong, “Memory technologies for sub-40 nm node,” in IEDM Tech. Dig., Dec. 2007, pp. 27–30. [2] D. Kwak et al., “Integration technology of 30 nm generation multi- level NAND flash for 64 Gb NAND flash memory,” in Sympo. VLSI Technology., June 2007, pp. 12–13. [3] K. Kim and J. Choi, “Future outlook of NAND flash technology for 40 nm node and beyond,” in IEEE NVSMW Tech. Dig., 2006, pp. 9–11. [4] K. W. Lee et al., “Three-dimensional shared memory fabricated using wafer stacking technology,” in IEDM Tech. Dig., Dec. 2000, pp. 165–168. [5] M. Koyanagi et al., “Three-dimensional integration technology based on wafer bonding with vertical buried interconnections,” IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2799–2808, Nov. 2006. [6] M. Crowley et al., “512-Mb PROM with 8 layers of antifuse/diode cells,” in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 284–285. [7] A. J. Walker et al., “3D TFT-SONOS memory cell for ultra-high density file storage applications,” in Sympo. VLSI Technol., June 2003, pp. times are all fully comparable to conventional planar NAND 29–30. device. [8] H. Tanaka et al., “Bit cost scalable technology with punch and plug process for ultra high flash memory,” in Sympo. VLSI Tech., June 2006, pp. 14–15. V. C ONCLUSIONS [9] S.-M. Jung et al., “Highly area efficient and cost effective double stacked S3 (stacked single-crystal Si) peripheral CMOS SSTFT and 3-dimensional 4 Gb double-stacked MLC NAND flash SRAM cell technology for 512 Mbit density SRAM,” in IEDM Tech. is successively developed using 45 nm floating-gate and Dig., Dec. 2004, pp. 265–268.

[10] S.-M. Jung et al., “Three dimensionally stacked NAND flash memory Doogon Kim was born in Gyeongnam, Korea. technology using stacking single crystal Si layers on ILD and TANOS He received the B.S., M.S. degrees in electrical structure for beyond 30 nm node,” in IEDM Tech. Dig., Dec. 2006, pp. engineering from Korea University, in 1999, 2001, 37–40. respectively. [11] K.-T. Park et al., “A 45 nm 4 Gb 3-dimensional double-stacked multi- From 2001 to 2005, he was with Silicon7 Industry, level NAND flash memory with shared bitline structure,” in ISSCC Dig. Gyeonggi, Korea, where he was working on the cir- Tech. Papers, Feb. 2008, pp. 510–511. cuit design of low power Pseudo SRAM memories. [12] J.-D. Lee et al., “A new programming disturbance phenomenon in In 2005, he joined Samsung Electronics Corporation, NAND flash memory by source/drain hot-electrons generated by GIDL Gyeonggi, Korea, where he has been working on the current,” in NVSMW, Feb. 2006, pp. 31–33. circuit design of High Density NAND flash memory. [13] T. Cho et al., “A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512 Mb single-level modes,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1700–1706, 2001. [14] K.-T. Park et al., “Scalable wordline shielding scheme using dummy cell beyond 40 nm NAND flash memory for eliminating abnormal Hoo-Sung Cho was born in Yeosu, Korea, in 1970. disturb of edge memory cell,” in Ext. Abst. of SSDM, Sep. 2006, pp. He received the B.S. degree in materials engineering 298–299. from Korea AeroSpace University, Korea, in 1996. [15] K.-D. Suh et al., “A 3.3 V 32 Mb NAND flash memory with incre- He joined Samsung Electronics Corporation, mental step pulse programming scheme,” in ISSCC Dig. Tech. Papers, Gyeonggi, Korea, in 1996, where he has been Feb. 1995, pp. 128–129. working on Process Architecture. He has specialized [16] K.-T. Park et al., “A zeroing cell-to-cell interference page architec- in areas such as process integration, yield enhance- ture with temporary LSB storing program scheme for sub-40 nm MLC ment, and failure analysis. NAND flash memories and beyond,” in Sympo. VLSI Circuits., June 2007, pp. 188–189.

Youngwook Jeong was born in Namhae, Korea. He received the B.S. degree in electronics engineering from Incheon University, Incheon, Korea in 2003, Ki-Tae Park received the B.S. degree in electronics and the M.S degree in electronics engineering from engineering from Kyoungbook National University, the Hanyang University, Seoul, Korea in 2005. Korea, in 1993, and the M.S. and Ph.D. degree In 2005, he joined the Flash Development Team in machine intelligence and system engineering of Samsung Electronics Company, Kyungi-do, from Tohoku University, Japan in 1993, and 1999, Korea. His current research interests are testing and respectively. evaluating to 3-Dimensional Double-Stacked NAND From 1999 to 2001, he served as Research As- Flash Device. sociate and worked on nano-CMOS devices, low power circuits, 3-D shared memories and artificial retina chips in Tohoku University. From 2001 to 2004, he was with Halo LSI, New York, in circuit Yong-Il Seo was born on June 16, 1966, in Taejon, design for high speed embedded flash and NAND compatible high density Korea. He received the B.E. degree in electronics en- flash memories using SONOS technology. He joined Semiconductor R&D gineering form Myong-Ji University, Korea, in 1991. Center of Samsung Electronics, Korea in 2004 and has working on advanced He joined Samsung Electronics Corporation, multi-level-cell NAND flash memory design. He received several achievement Ki-heung, Korea, in 1991, where he has been awards from Samsung for his outstanding work on patents and technical papers. working on Test and PE of EEPROMs and high-density NAND flash memories.

Myounggon Kang was born in Jeonju, Korea. He received the B.S. degree (with the Presidential Award) in electronics and information engineering from Chonbuk National University, Jeonju, Korea in 2003, and the M.S degree in electrical engineering from the Seoul National University, Seoul, Korea in Jaehoon Jang was born in Seoul, Korea, in 1969. He 2005. received the B.S., M.S., and Ph.D. degrees in elec- In 2005, he joined the Advanced Technology trical engineering from Korea Advanced Institute of Development (ATD) Team of Samsung Electronics Science and Technology (KAIST), Daejeon, Korea, Company, Kyungi-do, Korea. His current research in 1991, 1993 and 1997, respectively. The subject of interests are circuit design and modeling of high his doctoral thesis was about the improvement in ef- density NAND flash memory. ficiency of amorphous Silicon solar cell. After receiving the Ph.D degree, he joined Samsung Electronics Corporation, Gyeonggi-do, Korea in 1997 and has been engaged in the development of devices and process integration for SRAM Soon-Wook Hwang was born in Kyunggi, Korea, by April/2005. During that period, he has been working in the development on May 22, 1977. He Received the B.S. degree in of 8 M SP SRAM, 16 M DDR SRAM with 0.18 um technology and 8 M/16 electronic engineering from Kwangwoon University M ultra-low power SRAM with 0.15 um technology and also, 8 M/16 M in 2003 and the M.S. degree in electrical engineering ultra-low power SRAM with 0.10 um technology. He was also one of the major from the State University of New York (SUNY) in developers of the revolutionary S3 SRAM. From May/2005 to April/2006, Buffalo in 2006. He joined Samsung Electronics he has been a visiting scholar at Stanford University in Palo Alto, CA, USA. Corporation, Kiheung, Korea in 2006, where he has After returning to Samsung Electronics Co. Ltd., he has been involved in the been working on the circuit design and development development of 3-dimensionally stacked NAND flash memory up to now. His of high density NAND flash memories. current interest is the development of sub-40 nm NAND cells for the stacked structure.

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Han-Soo Kim was born in ChoongNam, Korea, Soon-moon Jung received the B.S. and M.S. degree in 1964. He received the B.S. and M.S. degree in in materials science and engineering from Hanyang electronics from HanYang University, Seoul, Korea University, Korea, in 1984, and 1986, respectively. In in 1987 and 1989, respectively. 1996, he received the Ph.D. degree in materials sci- In 1989, he joined the Research and Development ence and engineering from the University of Florida. Center, Memory Division, Samsung Electronics, He joined Samsung Electronics as device and Korea, where he was engaged in the research and process integration engineer in 1986. Since 1986, he development on the Low Power and High Speed has mainly developed SRAM products from 64 K bit SRAMs. Since 2002, he has been engaged in the SRAM to 72 M bit SRAM for high speed and low research and development on the NAND type Flash power application. In 2004, he developed for the ﬁrst Memory at the Research and Development Center, time 3 dimensional stacked SRAM cell, so called Semiconductor Business, Samsung Electronics, Korea. He is presently engaged SRAM. From 2005, he is engaged to develop NAND Flash memory. In 2006, in the characterization and development of 3D NAND Flash Memory Devices for the ﬁrst time, he developed 3 dimensional stacked NAND Flash memory. that have technology of sub-40 nm. Currently, he is a V.P. and a project manger of next generation NAND Flash memory and SRAM products in R&D center.

Yeong-Taek Lee was born on February 19, 1964, in Korea. He received the B.S., M.S. degrees in elec- Changhyun Kim (SM’05) received the B.S. and tronics engineering from Seoul National University, M.S. degrees in electronics engineering from Seoul Seoul, Korea, in 1987 and 1989, respectively, and the National University, Seoul, Korea, in 1982 and Ph.D. degree in electrical engineering from Seoul Na- 1984, respectively, and the Ph.D. degree in electrical tional University, in 1998. engineering from the University of Michigan, Ann He joined Samsung Electronics Corporation, Arbor, in 1994. Kiheung Korea, in 1989. From 1989 to 1994, he In 1984, he joined Samsung Electronics Co., Ltd., was involved in circuit design for the high density Gyeonggi-do, Korea, where he has been involved DRAM such as 4M and 16MDRAMs. After fin- in circuit design for high-speed dynamic RAM’s, ishing his Ph.D. degree in 1998, he rejoined Samsung ranging from 64 Kb to 16 Mb in size. From 1989 until Electronics and has been working on the circuit design and development of 1995, he was a research assistant and research faculty high-density memories. He was involved in circuit designs of 1G and 4G of the Center for Integrated Sensors and Circuits, University of Michigan. In multi-level cell NAND flash memories. He contributed as the leader of design 1995, he rejoined Samsung Electronics and worked for Gigabit DRAM and high part to the successful development of 4Gb NAND flash memory which was speed devices, such as RDRAM & DDR2. His present research interests are awarded the Grand Prize from the Samsung group in 2003. His present research in the area of circuit design for low-voltage and high-performance Giga-scale interests are in the area of circuit design for advanced multi-level-cell NAND Memory and future high performance memory architectures, ranging from 1 flash memory and emerging new memories such as PRAM and MRAM and GHz to 10 GHz in speed including new nonvolatile memories (PRAM, FRAM, future high-performance memory architectures. He serves as a committee STT-MRAM, RRAM, etc.). He published international technical papers (b30) member of the Asian Solid State Circuit Conference. and filed US patents (b15) regarding to high performance memories. Dr. Kim received the Grand Prize from the Samsung group for the successful development of 1 Mb and 1 Gb DRAM’s in 1986 and 1996, respectively. He received several technical achievement awards from R&D center of Samsung for his work on the development of high speed devices and the characterization of sub-micron devices and reliability issues in high-density DRAM’s, including reducing soft-error rates and reducing sensitivity to electrostatic dis- charge problems. He received first prize for design excellence in student VLSI design contests at the Center for Integrated Sensors and Circuits in 1991 and 1993, sponsored by several U.S. companies. He serves as a committee member of the Symposium on VLSI Circuits and the A-SSCC. He was honorary elected as the Samsung fellow in Nov. 2004.

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