208 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure Ki-Tae Park, Myounggon Kang, Soonwook Hwang, Doogon Kim, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jaehoon Jang, Han-Soo Kim, Yeong-Taek Lee, Soon-Moon Jung, and Changhyun Kim, Senior Member, IEEE Abstract—A 3-dimensional double stacked 4 Giga-bit multi-level NAND device by using conventional linear scaling method cell NAND flash memory device with shared bitline structure will face severe scaling barriers such as increasing cell-to-cell have successfully developed. The device is fabricated by 45 nm interference and decreasing coupling ratio at under 20 nm tech- floating-gate CMOS and single-crystal Si layer stacking tech- nologies. To support fully compatible device performance and nology node [3]. Therefore, a new innovated and breakthrough characteristics with conventional planar device, shared bit- technology to solve these issues is deadly required. As one of line architecture including Si layer-dedicated decoder and Si the potential solutions, three-dimensional (3-D) memories have layer-compensated control schemes are also developed. By using regained attention for recent several years. the architecture and the design techniques, a memory cell size of 0.0021 mP bit per unit feature area which is smallest cell size So far, many 3-D memory technologies have been proposed and 2.5 MB/s program throughput with 2 kB page size which is and evaluated. They can be simply categorized into two dif- almost equivalent performance compared to conventional planar ferent technologies as follows, in terms of cost and performance. device are realized. One is package-based wafer or chip stacking 3-D memory tech- Index Terms—Layer-compensated control, NAND flash, shared nologies that is able to provide high performance and is fully bitline architecture, Si layer-dedicated decoder, single-crystal Si compatible with conventional planar device [4], [5]. However, layer stacking, 3-dimensional device. this 3-D technology is difficult to realize high density memory while serving low cost due to decreasing number of die on the I. INTRODUCTION wafer. On the other hand, thin-film based cell stacking tech- nology such as laser-crystallized poly-Si based 3-D device has a HE ever increasing demand for NAND flash memory has great potential to realize both high density and low cost [6]–[8]. T lead to ever scaled down in NAND technology which But it is hard to provide compatible performance to conven- has achieved with double density every year in recent year. tional NAND device due to its inherent low electrical charac- Fig. 1 shows mass-produced NAND technology node and used teristics of thin-film memory cell device. Among the proposed lithography technology which have traced for past several 3-D memory technologies, the recently developed single-crystal years. As further scaling NAND device with the current scaling Si layer stacking is a very attractive method which satisfies both pace, however, two big challenges to overcome scaling NAND device performance and fabrication cost [9], [10]. A 3-D double are expected in near future [1]. One is uncertainty of future stacked NAND flash memory cell implemented by the single- lithography technology. So far, lithography for each generation crystal Si layer stacking was successfully demonstrated using has been available by improving its patter resolution with phase 63 nm CMOS technology [10]. shift mask (PSM) and optical proximity correction (OPC) tech- In this paper, we present a 3-D double stacked 4 Gb MLC niques. For recent 50 nm and 40 nm node NAND device, ArF (Multi-Level Cell) NAND flash memory device with shared lithography technology with immersion technique has been BL (Bit Line) structure, which realized a memory cell size used, and for 30 nm node NAND device, another technique of 0.0021 m bit per unit feature area [11]. The device like self-aligned double pattering (SADP) using the ArF lithog- is designed to support 3-D stacking and fabricated by the raphy was proposed [2]. However, to pattern under-30 nm node single-crystal Si layer stacking and 45 nm floating-gate CMOS NAND device, a new lithography technology like Extreme technologies. By using special design techniques such as Ultraviolet (EUV) should be available. But, we expect it is Si-layer-dedicated decoder and layer-compensated control still uncertain when it will be available. The other challenge is scheme, the 3-D device is able to increase double density uncertainty of NAND device scaling itself. It is expected that physically without performance degradation compared to con- ventional planar NAND flash device. This paper is organized as follows. 3-D stacked NAND Manuscript received March 24, 2008; revised June 24, 2008. Current version device and its chip architecture are described in Section II. published December 24, 2008. Some important circuit designs for 3-D NAND are presented The authors are with the Semiconductor R&D Center, Memory Business, in Section III and its performances based on measured results Samsung Electronics Co., Ltd., Gyeonggi-Do 445-701, Korea (e-mail: kt21c. [email protected]). are described in Section IV. Finally, the conclusion is given in Digital Object Identifier 10.1109/JSSC.2008.2006437 Section V. 0018-9200/$25.00 © 2008 IEEE Authorized licensed use limited to: IEEE Xplore. Downloaded on January 15, 2009 at 10:09 from IEEE Xplore. Restrictions apply. PARK et al.: FULLY PERFORMANCE COMPATIBLE 45 nm 4-GIGABIT 3-D DOUBLE-STACKED MULTI-LEVEL NAND FLASH MEMORY 209 Fig. 1. NAND technology node and used lithography technology. Fig. 2. Cross-sectional view and top layout view of the 3-D stacked NAND string. II. THREE-DIMENSIONAL STACKED NAND AND CHIP ARCHITECTURE Fig. 2 shows a cross-sectional view and a top layout view of the 3-D stacked NAND string. The NAND cell on the second Si layer which is identical to NAND cell on the first Si layer is formed after fabricating NAND cell on the first Si layer. All metals including not only bitline (BL) and common source line (CSL) but also 2 aluminum metals for interconnecting are formed on the second Si layer as shown in the figure. Because two memory cells are stacked vertically, simply twice memory density can be realized within unit feature size. In addition, the memory cell on the second Si layer is also formed on single-crystal Si layer so that its electrical characteristics is equivalent to that of conventional planar NAND cell. Due to its higher height between BL and surface of first Si layer compared to conventional planar NAND device, however, a relative larger Fig. 3. Micrograph of the fabricated 3-D stacked 4 Gb MLC NAND flash. contact-via on the second Si layer is required. Fig. 3 shows a micrograph of the 3-D stacked 4 Gb MLC NAND flash memory chip. The chip was fabricated by 45 nm decoders which are placed at both sides of the memory array are floating-gate NAND and the single-crystal Si layer stacking dedicated to each MAT. A 2 kB page buffer, which is shared by technologies. The device is composed of two stacked Si layers, the two MATs, is located at the bottom side of memory array. each Si layers containing a 2 Gb MLC memory array (MAT1 Except MAT2 that was fabricated on the second Si layer, MAT1 for first Si layer, MAT2 for second Si layer) consisting of 1 k and all peripheral circuitry including high voltage generation blocks with a page size of (2 kB 64). Two word-line (WL) circuits are formed on the first Si layer. Authorized licensed use limited to: IEEE Xplore. Downloaded on January 15, 2009 at 10:09 from IEEE Xplore. Restrictions apply. 210 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 Fig. 5. Simplified chip architecture. Fig. 4. NAND string with dummy cells ([14]). As shown in the Fig. 4, 32-cell string with 2 dummy cells is used to reduce abnormal disturbances of edge memory cells ( and in Fig. 4) which are adjacent to select transistors in NAND string in the 3-D stacked NAND device. The abnormal disturbances are caused by hot electron injec- tion induced by band-to-band tunneling at junction of the se- lect transistor [12] and boosted channel potential leakage due to WL-WL capacitive coupling noise [13]. By inserting addi- tional memory cell used as dummy between the select transistor and edge memory cell and applying proper bias voltages on the Fig. 6. (a) Single WL-decoder, (b) Si-layer dedicated WL-decoder. dummy cell during operations, the abnormal disturbances can be reduced significantly [14]. The architecture of the chip is shown in Fig. 5. Basically, (CSL) and wells of memory arrays are electrically connected memory array is formed on each Si layer and all peripheral cir- between the MATs and driven by CSL and well driver circuits, cuitry are formed on the bulky first Si layer. BL of the memory respectively. cells are formed on the MAT2 and shared with MAT1 using con- By using the shared BL structure, the page buffer is able to tact-vias which are formed through the second Si layer. WL of access both MAT1 and MAT2 so that the BL loading of the memory cells is each formed on the MAT. Common source lines 3-D device is almost comparable to the loading of conventional Authorized licensed use limited to: IEEE Xplore. Downloaded on January 15, 2009 at 10:09 from IEEE Xplore. Restrictions apply.