DOCSLIB.ORG

Investigation of High-К Dielectric Films Incorporated with Lanthanum and Their Application in Flash Memory Devices

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Investigation of High-К Dielectric Films Incorporated with Lanthanum and Their Application in Flash Memory Devices View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by ScholarBank@NUS INVESTIGATION OF HIGH-К DIELECTRIC FILMS INCORPORATED WITH LANTHANUM AND THEIR APPLICATION IN FLASH MEMORY DEVICES HE WEI NATIONAL UNIVERSITY OF SINGAPORE 2009 INVESTIGATION OF HIGH-К DIELECTRIC FILMS INCORPORATED WITH LANTHANUM AND THEIR APPLICATION IN FLASH MEMORY DEVICES He Wei (B. Eng., Harbin Institute of Technology) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2009 Abstract Abstract The SONOS-type of flash memory is one of the promising candidates to replace the conventional floating-gate type flash memory to enable continued memory device down-sizing. For a typical SONOS-type flash memory, there is a tradeoff between data retention and operation speeds. In order to break this tradeoff, Al2O3 as a blocking oxide has been proposed and exhibits promising results. However, the permittivity of Al2O3 is not high (only around 9) and even higher permittivity dielectrics, such as LaAlOx and HfLaOx, were investigated here to further improve the memory performance. The lanthanum-incorporated dielectrics (LaAlOx and HfLaOx) were deposited using the atomic layer deposition (ALD) method at 300ºC. The enhancement of deposition rate of La2O3 was observed when co-introducing the Hf or Al precursor into the process chamber to form HfLaOx or LaAlOx, respectively. Overall, the ALD processes of both HfLaOx and LaAlOx showed good self-limiting behavior, good film uniformity, low carbon impurity and a strictly linear relationship between the film thickness and deposition cycles, indicating good ALD characteristics. Both ALD LaAlOx and HfLaOx layers exhibited wide energy band gap and relatively large conduction band offset. LaAlOx films with a higher La percentage showed higher permittivity. The permittivity of amorphous LaAlOx films with 46% La was around 18 and these films could stand annealing temperature up to 850ºC. In I Abstract contrast, at low temperatures (~ 500ºC), HfLaOx with 8 at.% La would crystallize to a cubic-like phase and this phase has a much greater permittivity (~ 38) than that of amorphous or monoclinic phases (~ 20). This increase in permittivity resulted in a significant improvement in the overall leakage current. Moreover, the permittivities and leakage currents are dependant on annealing temperatures. Both LaAlOx and HfLaOx were used as blocking oxides in nitride-based SONOS-type flash memories. In comparison with memory cells using Al2O3 blocking oxide, those with LaAlOx or HfLaOx blocking oxide exhibited improved memory characteristics, such as faster operation speeds, wider saturation window, and better time-to-breakdown (tBD) reliability. Furthermore, memory cells with LaAlOx blocking oxide showed improved retention performance below 120ºC, which is similar to normal memory working temperature. On the other hand, memory cells using HfLaOx blocking oxide showed degraded retention performance due to their relatively low conduction band offset. By compiling above data retention results, it is found that the conduction band offset of blocking oxide over Si is required to be greater than 2.4 eV. However, few dielectrics can satisfy such requirement. In addition, by using the modified Yang’s model, the trapping energy depth in nitride films was calculated to be ~ 0.7 eV below the nitride conduction band edge. Overall, LaAlOx is a promising candidate as a blocking oxide to further boost the memory performances. And HfLaOx, due to its improved permittivity under cubic phase, may be useful in other applications, e.g. in DRAMs. II Acknowledgements Acknowledgements Many colleagues and individuals who have directly or indirectly assisted in the preparation of this manuscript are much appreciated. First of all, I would like to express my sincere gratitude to my thesis advisors, namely, Prof. Daniel Chan and Prof. Byung-jin Cho for their invaluable guidance, wisdom, and kindness in instructing and encouraging me during my postgraduate study at NUS. I will definitely benefit from the experience and knowledge I have gained from them throughout my life. I am especially grateful to Prof. Cho who provided me an opportunity to join Silicon Nano Device Lab and start the postgraduate study; secondly for his patience and painstaking efforts devoted to my research as well as his kindness and understanding which accompanied me over the last four years. Besides, I am also grateful to Prof. Chan’s, who guided me through the Ph.D study, offered me a position to continue the study and spent a lot of time in correcting the thesis. Hence, my best wishes will go to Prof. Cho and Prof. Chan as I am deeply appreciated for their generous help. Besides, I have had a great pleasure of collaborating with numerous talented graduate students and colleagues over the past four years. Firstly, I would like to give my thanks to my colleagues in Prof. Cho’s group, including Dr. Kim Sun-Jung, Dr. Hwang Wansik, Dr. Shen Chen, Ms. Zhang Lu, and Ms. Pu Ji for their useful discussions and kind assistances. Secondly, many thanks also go to Mr. Zhang Gang, III Acknowledgements Mr. Sun Zhiqiang, Mr. Ma Fajun and other technical staffs (Mr. Yong YuFoo, Mr. Lau BoonTeck, Mr. Tang Patrick, and O Yan Wai Linn) for their knowledge and experiences which had benefited me, as well as the long lasting friendship. I would also like to extend my appreciation to all NUS members including professors (such as Prof. Samudra Ganesh, Dr. Zhu Chunxiang, Dr. Yeo Yee-Chia, Dr. Yuan Zeliang, etc.), non-academic staffs and graduate students for the terrific academic environment, as well as the technical staffs in IMRE who have assisted me in material analysis, such as Dr. Zhang Zheng, Lim Poh Chong, Doreen Lai Mei-Ying, etc. Last but not least, my deepest love and gratitude will go to my family, especially to my wife and my parents for their self-giving love, patience and support throughout my life. He Wei Nov 2009 IV Table of Contents Table of Contents Abstract......................................................................................................................... I Acknowledgements ....................................................................................................III Table of Contents ........................................................................................................V List of Tables ...........................................................................................................VIII List of Figures.............................................................................................................IX List of Symbols and Abbreviations .......................................................................XVI Chapter 1 Introduction of Flash Memory and High-К Dielectrics.........................1 1.1 Overview..............................................................................................................1 1.2 Nitride-based SONOS-type Flash Memory.........................................................4 1.2.1 Overview of Non-volatile Memory Candidates............................................4 1.2.2 A Brief Review of SONOS-type Flash Memory ..........................................8 1.2.3 Using High-κ Dielectric to Improve Memory Performance.......................11 1.3 Lanthanum-incorporated High-κ Dielectrics .....................................................13 1.3.1 Dielectric Parameters for the Selection of High-κ Thin Film.....................13 1.3.2 Lanthanum-incorporated High-κ Dielectrics: LaAlOx and HfLaOx ...........17 1.3.3 Current Developments of LaAlOx and HfLaOx Dielectrics........................19 1.3.4 Using ALD LaAlOx and HfLaOx Dielectrics in Memory Application.......23 1.4 Outline of the Thesis..........................................................................................25 References................................................................................................................26 Chapter 2 High-К Dielectrics Engineering by Atomic Layer Deposition (ALD).35 2.1 Introduction........................................................................................................35 2.1.2 Introduction of ALD Principles ..................................................................36 V Table of Contents 2.1.2 A Brief Review of ALD Precursors............................................................39 2.3 Experiment Conditions ......................................................................................41 2.4 ALD Process of Lanthanum-incorporated Dielectrics.......................................41 2.5 Characterization of Deposited Film...................................................................53 2.6 Summary............................................................................................................57 References................................................................................................................57 Chapter 3 Characteristics of Lanthanum-incorporated Dielectrics .....................61 3.1 Introduction........................................................................................................61 3.2 Experiments .......................................................................................................62 3.3 Physical Characteristics of HfLaOx and LaAlOx Films.....................................66 3.4 Electrical Characteristics of HfLaOx Films .......................................................75
Load more

Recommended publications
  • Scalability and Reliability of Phase Change Memory
    SCALABILITY AND RELIABILITY OF PHASE CHANGE MEMORY A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY SangBum Kim Aug 2010 © 2010 by SangBum Kim. All Rights Reserved. Re-distributed by Stanford University under license with the author. This work is licensed under a Creative Commons Attribution- Noncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/ This dissertation is online at: http://purl.stanford.edu/kk866zc2173 ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Philip Wong, Primary Adviser I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Yi Cui I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Yoshio Nishi Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost Graduate Education This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives. iii Abstract Various memory devices are being widely used for a wide range of applications. There has not been any universal memory device so far because each memory device has a unique set of features.
    [Show full text]
  • Device-Aware Inference Operations in SONOS Non- Volatile Memory Arrays
    Device-aware inference operations in SONOS non- volatile memory arrays Christopher H. Bennett1*, T. Patrick Xiao1*, Ryan Dellana1, Ben Feinberg1, Sapan Agarwal1, and Matthew J. Marinella1 1. Sandia National Laboratories, Albuquerque, NM 87185-1084, USA {cbennet,txiao,mmarine}@sandia.gov *These authors contributed equally Vineet Agrawal2, Venkatraman Prabhakar2, Krishnaswamy Ramkumar2, Long Hinh2, Swatilekha Saha2, Vijay Raghavan3, Ramesh Chettuvetty3 2. Cypress Semiconductor Corporation, 198 Champion Court, San Jose, CA, 95134, USA 3. Cypress Semiconductor Corporation, Ste #120, 536 Chapel Hills Drive, Colorado Springs, CO, 80920, USA [email protected] Abstract— Non-volatile memory arrays can deploy pre-trained noise, variability, and circuit non-idealities [6],[7]. We neural network models for edge inference. However, these additionally investigate the impact of retention loss as systems are affected by device-level noise and retention issues. measured in real devices and show that the same device-aware Here, we examine damage caused by these effects, introduce a training methods can be applied to mitigate the effects of mitigation strategy, and demonstrate its use in fabricated array weight drift. In the following sections, we demonstrate that the of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) devices. On following two approaches – in terms of software neural MNIST, fashion-MNIST, and CIFAR-10 tasks, our approach network and circuit architecture respectively – can mitigate increases resilience to synaptic noise and drift. We also show device non-idealities: strong performance can be realized with ADCs of 5-8 bits precision. The use of noise regularization during training which implicitly counteracts generic noise disturbance, device- Index Terms-- SONOS, CTM, neural networks, edge inference to-device variability, and charge decay phenomenon: The use of an appropriate 1T,1CTM cells in a dual array I.
    [Show full text]
  • A Stacked Memory Device on Logic 3D Technology for Ultra-High-Density Data Storage
    IOP PUBLISHING NANOTECHNOLOGY Nanotechnology 22 (2011) 254006 (7pp) doi:10.1088/0957-4484/22/25/254006 A stacked memory device on logic 3D technology for ultra-high-density data storage Jiyoung Kim1,2, Augustin J Hong1, Sung Min Kim1,2, Kyeong-Sik Shin1, Emil B Song1, Yongha Hwang1, Faxian Xiu1, Kosmas Galatsis1, Chi On Chui1, Rob N Candler1, Siyoung Choi2, Joo-Tae Moon2 and Kang L Wang1 1 Device Research Laboratory, Department of Electrical Engineering, University of California, Los Angeles, CA 90095, USA 2 Advanced Technology Development Team and Process Development Team, Memory R&D Center, Samsung Electronics Co. Ltd, Korea E-mail: [email protected] Received 22 June 2010, in final form 29 September 2010 Published 16 May 2011 Online at stacks.iop.org/Nano/22/254006 Abstract We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures. S Online supplementary data available from stacks.iop.org/Nano/22/254006/mmedia (Some figures in this article are in colour only in the electronic version) 1. Introduction patterning resolution, transistor short-channel effects, and ever increasing interference between adjacent cells [3, 5–8].
    [Show full text]
  • Resistive-RAM for Data Storage Applications by Siddharth Gaba A
    Resistive-RAM for Data Storage Applications by Siddharth Gaba A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in the University of Michigan 2014 Doctoral Committee Associate Professor Wei Lu, Chair Assistant Professor Emmanouil Kioupakis Professor Jerome P. Lynch Assistant Professor Zhengya Zhang Associate Professor Zhaohui Zhong TABLE OF CONTENTS List of Figures…………………………………………………………………………………….vi List of Tables……………………………………………………………………………………xiii Abstract………………………………………………………………………………………….xiv Chapter 1 Introduction ............................................................................................................. 1 1.1 Data Explosion .................................................................................................. 1 1.2 The NVM Workhorse: FLASH ........................................................................ 1 1.3 Semiconductor Flash Memory Scaling ............................................................. 3 1.4 Emerging Non-Volatile Memories ................................................................... 5 1.5 RRAM ............................................................................................................... 8 1.6 Organization of the Thesis .............................................................................. 11 References ............................................................................................................. 12 Chapter 2 Amorphous Silicon Based Electrochemical
    [Show full text]
  • A Study About Non-Volatile Memories
    Preprints (www.preprints.org) | NOT PEER-REVIEWED | Posted: 29 July 2016 doi:10.20944/preprints201607.0093.v1 1 Article 2 A Study about Non‐Volatile Memories 3 Dileep Kumar* 4 Department of Information Media, The University of Suwon, Hwaseong‐Si South Korea ; [email protected] 5 * Correspondence: [email protected] ; Tel.: +82‐31‐229‐8212 6 7 8 Abstract: This paper presents an upcoming nonvolatile memories (NVM) overview. Non‐volatile 9 memory devices are electrically programmable and erasable to store charge in a location within the 10 device and to retain that charge when voltage supply from the device is disconnected. The 11 non‐volatile memory is typically a semiconductor memory comprising thousands of individual 12 transistors configured on a substrate to form a matrix of rows and columns of memory cells. 13 Non‐volatile memories are used in digital computing devices for the storage of data. In this paper 14 we have given introduction including a brief survey on upcoming NVMʹs such as FeRAM, MRAM, 15 CBRAM, PRAM, SONOS, RRAM, Racetrack memory and NRAM. In future Non‐volatile memory 16 may eliminate the need for comparatively slow forms of secondary storage systems, which include 17 hard disks. 18 Keywords: Non‐volatile Memories; NAND Flash Memories; Storage Memories 19 PACS: J0101 20 21 22 1. Introduction 23 Memory is divided into two main parts: volatile and nonvolatile. Volatile memory loses any 24 data when the system is turned off; it requires constant power to remain viable. Most kinds of 25 random access memory (RAM) fall into this category.
    [Show full text]
  • Wordperfect Office Document
    THE INTERNET OF BODIES ANDREA M. MATWYSHYN* ABSTRACT This Article introduces the ongoing progression of the Internet of Things (IoT) into the Internet of Bodies (IoB)—a network of human bodies whose integrity and functionality rely at least in part on the Internet and related technologies, such as artificial intelligence. IoB devices will evidence the same categories of legacy security flaws that have plagued IoT devices. However, unlike most IoT, IoB technolo- gies will directly, physically harm human bodies—a set of harms courts, legislators, and regulators will deem worthy of legal redress. As such, IoB will herald the arrival of (some forms of) corporate software liability and a new legal and policy battle over the integrity of the human body and mind. Framing this integrity battle in light of current regulatory approaches, this Article offers a set of specific innovation-sensitive proposals to bolster corporate conduct safe- guards through regulatory agency action, contract, tort, intellectual property, and secured transactions and bankruptcy. Yet, the challenges of IoB are not purely legal in nature. The social integration of IoB will also not be seamless. As bits and bodies meld and as human flesh becomes permanently entwined with hardware, * Associate Dean of Innovation and Professor of Law and Engineering Policy, Penn State Law (University Park); Professor of Engineering Design, Penn State Engineering; Founding Director Penn State Policy Innovation Lab of Tomorrow (PILOT); Affiliate Scholar, Center for Internet and Society, Stanford
    [Show full text]
  • ASIC Design Using Programmable Interconnects Based on CBRAM
    IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. 2 Issue 4, April 2015. www.ijiset.com ISSN 2348 – 7968 ASIC Design Using Programmable Interconnects Based On CBRAM Shankar Narayanan P Dr V Nagarajan Abstract— This work evaluates the performance of This may sound easy but in real case it is quite harder. So the CBRAM(Conductive Bridging Random Access Memory) based work required a special routing algorithm. The nature of the architecture for ASIC (Application Specific Integrated Circuit). algorithm is said to be more complex to solve the physical In everyday life we completely depend on the VLSI(Very Large design constraints. So to overcome this kind of tedious process Scale Integrated Circuits) chips that drives our electronic devices CBRAM just eases the design process. It is notable that the such as microwaves, mobile phones and ICs that drives our vehicles. So it is necessary that the programs that drive the work CBRAM are proven to be a better performer than the previous should be burned to the chip in a faster way. In general case of works done by [2] -[5]. the ASIC devices the speed of programming the device is entirely depend upon the interconnect network that are present inside the II. WHY PREFERRING ASIC memory devices for example the EEPROM(Electrically Erasable The previous work are constructed for the FPGA Programmable Read Only Memory).The interconnect networks framework, we know that FPGAs are test equipment. Our idea consist of SRAM(Static Random Access Memory) network that is to concentrate on real time applications, so that we can able bridges the switch block and logical block.
    [Show full text]
  • Implications for Nigeria's Higher Education Curricular
    Emerging Technologies and the Internet of all Things: Implications for Nigeria’s higher education curricular Osuagwu, O.E. 1, Eze Udoka Felicia 2, Edebatu D. 3, Okide S. 4, Ndigwe Chinwe 5 and, UzomaJohn-Paul 6 1Department of Computer Science, Imo State University + South Eastern College of Computer Engineering & Information Technology, Owerri, Tel: +234 803 710 1792 [email protected]. 2 Department of Information Mgt. Technology, FUTO 3,4 Department of Computer Science, Nnamdi Azikiwe University, Akwa, Anambra State 5 Department of Computer Science, Anambra State University of Science & Technology 6 Department of Computer Science, Alvan Ikoku Federal College of Education, Owerri Abstract The quality of education and graduates emerging from a country’s educational system is a catalyst for technology innovation and national development index. World class universities are showcasing their innovations in science and technology because their high education curricular put the future of Research and Development as their pillar for a brighter world. Our curricular in the higher education system needs a rethink, recasting to embrace innovation, design and production at the heart of what our new generation graduates should be. This article discusses an array of such emerging technologies. Because emerging technologies in all sectors are over 150. we had decided to select three key technologies from each sector for our sample questionnaire. A questionnaire was distributed mainly to educational planners, Lecturers and managers of the industry for purposes of having a feel of how knowledgeable these professionals are understanding developments in science technology and what plans they have to integrate these new knowledge domains so that educational planners can integrate them into the curricular of undergraduate and graduate degree programs in our tertiary institutions.
    [Show full text]
  • Resistive Memory Devices
    RESISTIVE MEMORY DEVICES RESISTIVE MEMORY DEVICES Jayant Thatte Indian Institute of Technology Madras INDO-GERMAN WINTER ACADEMY 2012 JAYANT THATTE, IIT MADRAS OUTLINE 2 Outline Existing Memory Technology • Flash Memory, SRAM, DRAM • Working Principle, Advantages and Disadvantages Need for New Technology Next Generation Memory Devices • Commercially Available: MRAM, PCRAM, CBRAM, FeRAM • Working Principle, Advantages and Disadvantages • Infant memories: STT-RAM, SONOS, Millipede, NRAM • Working Principle, Advantages and Disadvantages Comparison Current state of the new technology memory devices Acknowledgements and References INDO-GERMAN WINTER ACADEMY 2012 JAYANT THATTE, IIT MADRAS EXISTING MEMORY DEVICES – FLASH MEMORY 3 Flash Memory: Working Principle • Floating gate • No charge => 1 • Trapped Electrons => 0 • Read: VT of the transistor increases due to trapped electrons • VT0 < WL < VT1; pre-charge BL; binary o/p (sense amplifier) • Write: Electrons can tunnel across the oxide under high voltage (Hot electron injection) • Large voltage is applied to gate (WL), BL is pulled high Program/Erase depending on polarity of gate voltage INDO-GERMAN WINTER ACADEMY 2012 JAYANT THATTE, IIT MADRAS EXISTING MEMORY DEVICES – FLASH MEMORY 4 Advantages and Disadvantages Advantages • Non-volatile • High density: Stacked memory, Multi-level cells Disadvantages • Block erase and re-write: lacks 0 1 bit-wise alterability • Solution: Flash type file systems • Memory wear: finite number of P/E cycles • Solution: Writes with dynamic remapping, level wear
    [Show full text]
  • Wykrzyozfhdetncn.Pdf
    208 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure Ki-Tae Park, Myounggon Kang, Soonwook Hwang, Doogon Kim, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jaehoon Jang, Han-Soo Kim, Yeong-Taek Lee, Soon-Moon Jung, and Changhyun Kim, Senior Member, IEEE Abstract—A 3-dimensional double stacked 4 Giga-bit multi-level NAND device by using conventional linear scaling method cell NAND flash memory device with shared bitline structure will face severe scaling barriers such as increasing cell-to-cell have successfully developed. The device is fabricated by 45 nm interference and decreasing coupling ratio at under 20 nm tech- floating-gate CMOS and single-crystal Si layer stacking tech- nologies. To support fully compatible device performance and nology node [3]. Therefore, a new innovated and breakthrough characteristics with conventional planar device, shared bit- technology to solve these issues is deadly required. As one of line architecture including Si layer-dedicated decoder and Si the potential solutions, three-dimensional (3-D) memories have layer-compensated control schemes are also developed. By using regained attention for recent several years. the architecture and the design techniques, a memory cell size of 0.0021 mP bit per unit feature area which is smallest cell size So far, many 3-D memory technologies have been proposed and 2.5 MB/s program throughput with 2 kB page size which is and evaluated. They can be simply categorized into two dif- almost equivalent performance compared to conventional planar ferent technologies as follows, in terms of cost and performance.
    [Show full text]
  • Nano-Scale Memory Devices: Space-Time Energy Trade-Offs
    Nano-Scale Memory Devices: Space-Time-Energy Trade-offs Ralph Cavin and Victor Zhirnov Semiconductor Research Corporation 1 Main Points Many candidates for beyond-CMOS nano-electronics have been proposed for memory, but no clear successor has been identified. MthdlMethodology for sys tem-lllevel ana lilysis How is maximum performance related to device physics? 2 Three integrated components of a Memory Device: 1) ‘Storage node’ ppyhysics of memor y o peration 2) ‘Sensor’ which reads the state e.g. transistor 3) ‘Selector’ which allows a memory cell in an array to be addressed transistor diode All three components impact scaling limits for all memory didevices 3 Space-Time-Energy Metrics Essential parameters of the memory element are: cell size/density, retention time, access time/speed operating voltage/energy. None of known memory technologies, perform well across all of these parameters At the most basic level, for an arbitrary memory element, there is interdependence between operational voltage, the spppeed of operation and the retention time. More generally, cell dimensions are also part of the trade-off, hence the Space-Time-Energy compromise 4 Space-Action Principle for Memory EnergytimeVolume min E t V min E t L min E t Nat min The Least Action principle is a fundamental principle in Physics E t min (h) Plank’s constant h=6.62x10-34 Js 5 Three Major Memory State Variables Electron Charge (‘moving electrons’) e.g. DRAM, Flash Electron Spin (‘moving spins’) (STT-) MRAM Massive particle(s) (‘moving atoms’) e.g. ReRAM, PCM, Nanomechanical, etc. 6 Charge-based Memories DRAM/SRAM A e- B Floating Gate Memory SONOS Control Requirements: 1) Efficient charge injection during programming 2) Suppresse d bac k-flfhflow of charge it/din store/read mo des 3) Efficient erase 4) Min .
    [Show full text]
  • Co-Integration of Single Transistor Neurons and Synapses by Nanoscale CMOS Fabrication for Highly Scalable Neuromorphic Hardware
    Co-integration of single transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware Joon-Kyu Han Korea Advanced Institute of Science and Technology Jungyeop Oh Korea Advanced Institute of Science and Technology Gyeong-Jun Yun Korea Advanced Institute of Science and Technology Dongeun Yoo National Nanofab Center (NNFC) Myung-Su Kim Korea Advanced Institute of Science and Technology Ji-Man Yu Korea Advanced Institute of Science and Technology Sung-Yool Choi Korea Advanced Institute of Science and Technology Yang-Kyu Choi ( [email protected] ) Korea Advanced Institute of Science and Technology https://orcid.org/0000-0001-5480-7027 Article Keywords: articial neural network (ANN), complementary metal-oxide-semiconductor (CMOS), co- integration, excitatory neuron, inhibitory neuron, MOSFET, neuromorphic system, neuron device, silicon- oxide-nitride-oxide-silicon (SONOS), single transistor latch (STL), single transistor neuron, spiking neural network (SNN), synapse device Posted Date: January 6th, 2021 DOI: https://doi.org/10.21203/rs.3.rs-120802/v1 License: This work is licensed under a Creative Commons Attribution 4.0 International License. Read Full License Page 1/20 Abstract Co-integration of multi-state single transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide-semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide-semiconductor eld-effect transistor (MOSFET) with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to co-integrate the neurons and synapses with additional CMOS circuits, such as a current mirror and inverter.
    [Show full text]