Charge- Trapping Non-Volatile Memories Volume 2—Emerging Materials and Structures Charge-Trapping Non-Volatile Memories Panagiotis Dimitrakis Editor

Panagiotis Dimitrakis Editor Charge- Trapping Non-Volatile Memories Volume 2—Emerging Materials and Structures Charge-Trapping Non-Volatile Memories Panagiotis Dimitrakis Editor

Charge-Trapping Non-Volatile Memories Volume 2—Emerging Materials and Structures

123 Editor Panagiotis Dimitrakis Department of Microelectronics Institute of Advanced Materials Athens Greece

ISBN 978-3-319-48703-8 ISBN 978-3-319-48705-2 (eBook) DOI 10.1007/978-3-319-48705-2

Library of Congress Control Number: 2016956818

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1 Materials and Device Reliability in SONOS Memories...... 1 Krishnaswamy Ramkumar 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash Memory Devices ...... 55 Konstantina Saranti and Shashi Paul 3 Hybrid Memories Based on Redox Molecules ...... 91 Nikolaos Glezos 4 Organic Floating Gate Memory Structures ...... 123 S. Fakher, A. Sleiman, A. Ayesh, A. AL-Ghaferi, M.C. Petty, D. Zeze and Mohammed Mabrook 5 Nanoparticles-Based Flash-Like Nonvolatile Memories: Cluster Beam Synthesis of Metallic Nanoparticles and Challenges for the Overlying Control Oxide Layer...... 157 E. Verrelli and D. Tsoukalas Index ...... 211

v Chapter 1 Materials and Device Reliability in SONOS Memories

Krishnaswamy Ramkumar

1.1 Introduction

Non-volatile memories for data and code storage have been growing rapidly in performance and capacity over last few decades. With the advent of the many widely used consumer electronic gadgets such as cell phones, laptop computers, tablets, and electronic games, the need for non-volatile memories has been ever increasing recently. While the need for larger and larger memory capacity is obvious, there has also been an increasing demand for more and more robust data retention performance over a widening range of temperature. This is because the non-volatile memories are now getting into gadgets used in industrial and automotive environment. This coupled with the need for low cost solutions is chal- lenging the memory technology. SONOS (Silicon–Oxide–Nitride–Oxide–Silicon) seems to offer the non-volatile memory solutions in an ever widening range of applications. The key features of the SONOS memory device and their dependence on material characteristics are discussed in the following sections.

1.2 History of SONOS Memory Devices

SONOS memory device has been known for many decades. The initial work on SONOS devices was reported in the late 1960s. The MNS (Metal–Nitride–Silicon) structure was ﬁrst proposed as an alternate to the MOS (Metal–Oxide–Silicon)

K. Ramkumar (&) Cypress Semiconductor, 3833 North First Street, San Jose, USA e-mail: [email protected]

© Springer International Publishing AG 2017 1 P. Dimitrakis (ed.), Charge-Trapping Non-Volatile Memories, DOI 10.1007/978-3-319-48705-2_1 2 K. Ramkumar structure for superior dielectric strength [1]. However, instabilities were found with this device due to the large density of interface states at the Nitride–Silicon interface. The MNOS (Metal–Nitride–Oxide–Silicon) was proposed as a solution to this instability on account of the stable interface between silicon dioxide and silicon [2]. The charge storage in the MNOS structure was first observed as a hysteresis in the threshold voltage as a function of the gate voltage as shown in Fig. 1.1 [3]. In these devices, the nitride layer was identified as the charge storage layer due to the traps present and the oxide layer was proposed for injecting electrons or holes by direct tunneling. These early MNOS devices were made using the Aluminum gate technology The MNOS concept was studied widely in the 1970s and applied to memory structures [4–9]. With the advent of polysilicon gate technology, the Aluminum was replaced by polysilicon and SNOS devices became available. In the 1980s, to prevent carrier injection from the gate electrode to the nitride, another oxide layer was introduced between the nitride layer and the polysilicon gate and the SONOS device was invented [10]. The SONOS transistor was thus conceived as a storage element with its structure being almost identical to that of a MOS transistor with the gate dielectric being replaced by a ONO dielectric. This device has been studied extensively in the last three decades to understand the carrier transport, trapping and de-trapping mechanisms in the nitride layer. Several mechanisms have been proposed such as direct or modified Fowler–Nordiehm tunneling of carriers from the silicon to the nitride through the oxide and subsequent capture of these carriers by the deep traps in the nitride. The research on the SONOS device has continued with more sophisticated modeling of the transport and trapping mechanisms [11–13]. With the highlighting of the charge trapping mechanism in the SONOS device and its application in memories, the SONOS device also got referred to as a “Charge Trap Memory Device” or “CT” memory.

Fig. 1.1 First observation of memory effect in MNOS device [3] 1 Materials and Device Reliability in SONOS Memories 3

1.3 Floating Gate and SONOS Memories

SONOS-based memories were first introduced in the 1980s with a 16 Kbit EEPROM as one of the first products. The competition at that time was from Floating gate memories. The different types of Floating gate transistors used in memories are shown in Fig. 1.2. In all cases, a conducting but electrically floating polysilicon layer is used for charge storage. These devices are used even in present day Flash memories with device scaling being the main driver of the increase in memory density. Many enhancements such as Multi-levels and scaling have been introduced into the Floating gate technology to extend its capability. It is clear from the above figure that significant process changes are required to realize the floating gate memory device—a second polysilicon layer deposition and additional patterning steps. However, the retention performance of the Floating gate device is very robust on account of the relatively thick (60–80 Å) tunnel oxide being used. A SONOS memory device, on the other hand, greatly resembles a regular MOSFET and requires very few changes to the basic MOS process. The only significant process change is the formation of the ONO dielectric which forms the gate dielectric of the SONOS device. A typical SONOS FET is shown in Fig. 1.3. The SONOS memories could not compete well against the Floating gate memories, in the 1980s because the program/erase voltages required to get significant tunneling currents were very high (>20 V) on account of the difficulty in scaling down the thicknesses of the layers of the ONO stack. With availability of better film deposition and metrology equipment subsequently, the ONO stack

CG CG CG Float Float 14VSG Float e- Float SL SG FG FG FG

e- S e- D S D S D

Fig. 1.2 Different ﬂoating gate device used for memories

Fig. 1.3 Schematic cross section of a typical SONOS Salicide ONO FET Poly

Source Well Drain

D-N Well 4 K. Ramkumar thickness could be scaled down with robust process control and SONOS memories capable of program/erase at lower voltages were conceived. Additionally, extensive research on charge trap devices yielded novel methods of program and erase that allowed low voltage operation [14]. With this feature, SONOS memories became competitive with the ﬂoating gate memories and have carved a niche in the NVM market. The SONOS memory technology claims to be much less complex as compared to the Floating gate technology [15].

1.4 SONOS Memory Devices

As mentioned earlier, the simplest SONOS device closely resembles a normal CMOS FET (Fig. 1.4). The main difference is that the gate dielectric now is a ONO dielectric made up of a tunnel oxide, a nitride and a blocking oxide. The transistor can be NMOS or PMOS and can be either enhancement type or depletion type. Depletion type has the beneﬁt of a buried channel which keeps the carriers in the channel away from the interface states in Tunnel oxide–Semiconductor interface. If the memory stack is described in more general terms, the three layers can be referred to as 1. The tunneling layer, used for injecting charge carriers into the trap layer and to prevent trapped charges in the trap layer from being lost to the substrate. 2. The charge trap layer which stores charge by trapping the mobile carriers in traps located in the band gap. 3. The blocking layer which keeps the trapped charge in the trap layer isolated from the gate.

N+ N+

P-Well

Deep N-Well Poly

Blocking Oxide (HTO)

Nitride

Tunnel Oxide Silicon

Fig. 1.4 ONO stack in a SONOS FET 1 Materials and Device Reliability in SONOS Memories 5

All these are insulator layers which is a key difference from a floating gate memory device in which the charge storage layer is a semiconductor (Fig. 1.5). In fact, this difference gives a key advantage to the SONOS device. The charge carriers being trapped in an insulator makes them immobile which makes the device less susceptible to charge loss due to defects such as pin holes in contrast to a floating gate device where a defect can attract mobile charge carriers from everywhere in the storage layer and give rise to a significant charge loss (Fig. 1.6). The three layers of the charge trap memory stack need not always be SiO2 and SiN layers. For example, the tunneling layer can be a SiON layer or a high K

Fig. 1.5 Differences between ﬂoating gate and SONOS memory devices [16]

Fig. 1.6 Comparison of charge loss in ﬂoating gate and SONOS devices 6 K. Ramkumar dielectric and the blocking layer can be a high K dielectric. The trapping layer can be a SiON layer. One of the “S” layers in the SONOS is a polysilicon gate layer but can also be replaced by a metal layer, to form the MONOS device. Further, the three layers of the stack can themselves be made up of multilayer stack. For example, the tunneling layer can be made of a thin ONO stack or the trapping layer can be made of multiple nitride layers with different stoichiometry. A very good example for a SONOS memory device using a stack different from the standard ONO stack is the “TANOS” device in which TaN is the metal gate, Al2O3 is the blocking layer, Si3N4 is the trap layer and SiO2 is the tunneling layer. Although many novel and exotic stacks have been proposed and studied, the ONO with some modiﬁcations is still the most dominant charge trap memory stack.

1.4.1 Traps in the SONOS Stack

The trap levels and trapping–de-trapping mechanisms have themselves been sub- jects of extensive studies over the last three decades. The density, distribution, and energy levels of the traps in the nitride layer play a crucial role in the performance and reliability of the SONOS devices. Several experimental studies have attempted to quantify these parameters. Early studies of traps in silicon nitride were reported by Kapoor et al. [17] who used photocurrent spectroscopic technique to investigate the nitride deposited by Low Pressure Chemical Vapor Deposition (LPCVD). Their study revealed five different trap levels within the Si3N4 band gap at 2.50, 2.76, 3.03, 3.36, and 3.76 eV below the Si3N4 conduction band. Lue et al. [18] proposed a transient analysis electrical method. A direct charge observation method using scanning nonlinear dielectric microscopy has also been proposed [19]. According to the results of these studies, the trap levels for electrons and holes are at different energy levels in the band gap. The electron traps are close to the band edge whereas the hole traps are more in the middle of the band gap. On the other hand, a study by Seo et al. [20] used the DLTS technique to look at trap levels in Si3N4 deposited by LPCVD. This technique enabled the authors to determine the location of the electron and hole traps. They concluded that traps in SONOS stack are present both at the Si–SiO2 interface and in the nitride film. In both locations the traps were found to be fairly deep in the band gap of silicon and the nitride. Kim et al. also characterized the traps in the ONO stack using the DLTS technique [21]. Their study showed that the trap energy levels appeared at 0.307 and 0.472 eV above the valence band of the nitride. Ishida et al. analyzed trap distributions using a combination of avalanche charge injection and C– V (capacitance–voltage) measurement with varying thicknesses of the oxide and nitride layers in MONOS structures [22]. They found that electron traps mainly locate at both top and bottom oxide/nitride interfaces, whereas hole traps locate at 1 Materials and Device Reliability in SONOS Memories 7 the same interfaces as well as in the nitride bulk. The electron trap level is distributed between 0.9 and 1.7 eV. All these studies clearly show that the location of traps in the nitride can vary depending on the method of deposition and the experimental technique used for characterization. Electron and hole traps are located both close to the band edges as well as in the middle of the band gap of silicon and nitride. In optimizing the Si3N4 based ONO stacks, the approaches currently used focus on modifying the concentrations and the spatial distributions of traps in the nitride layer such that the charge trapping is maximized and charge loss is minimized. In recent years, with the increased focus on the use of high K dielectrics for gate dielectric of CMOS FETs, several investigations have focused on incorporating the high-K materials as charge trapping layer in a SONOS type of device [23]. Chin et al. [24] examined SONOS stacks with a high K dielectric as the trapping layer. The stacks they reported on are TaN–AILaO3–AIGaN–SiO2–Si and TaN– HfLaON–HfONx–SiOz–Si. Other modified stacks with multiple trap layers were also studied. The high-K trap materials with smaller band gap make the trap levels close to the band edges much deeper than in conventional SONOS stacks. With such deeper traps, the retention was improved significantly [25]. Attempts have also been made to optimize SONOS stacks with HfON and other high-k dielectrics commonly used as gate dielectric in CMOS FETs. These stacks, referred to as SOHOS, when optimized, typically exhibit superior retention performance [26]. The optimization involves the study of the composition of these high-K layers and their crystalline state at the end of processing due to the thermal processing steps post high-K deposition.

1.4.2 Program and Erase of SONOS FET

In a SONOS FET, silicon nitride is still the most widely used trapping layer and there are multiple methods by which charge carriers from the channel can be injected into this layer to be trapped. 1. By applying a high electric field between the gate and the channel, sufficient band bending can be created in the gate stack to enable injection of electrons or holes from the channel into the nitride through the tunnel oxide by Fowler– Nordheim (FN) tunneling. 2. By turning the transistor ON with an appropriate gate voltage and applying a high enough voltage to the drain, Hot carrier injection (HCI) can be achieved and a fraction of the hot carriers will get injected across the tunnel oxide into the nitride to get trapped there. Hot electron injection is generally used for programming and Hot Hole injection is used for erasing. The key difference between these two methods is that for FN tunneling, significant band bending has to be achieved with the applied gate voltage and this 8 K. Ramkumar means that the tunnel oxide has to be very thin (<20A) whereas with HCI, the carrier injection is less dependent on the tunnel oxide thickness and hence it can be much thicker (30–50A). As will be discussed later this difference has a big impact on the reliability. Another difference is that in FN tunneling, carrier injection occurs uniformly over the entire length of the channel whereas in HCI, most of the carrier injection occurs near the drain where the charge carriers have the maximum energy. The energy band diagram of the gate stack with a simple ONO gate dielectric in such a device with no bias voltage applied is shown in Fig. 1.7a. On application of a voltage to the gate with respect to the channel, band bending occurs (Fig. 1.7b). In the programing condition, with positive bias applied to the gate, electrons from the channel tunnel through the tunnel oxide by FN tunneling into the conduction band of the nitride. Many of them get trapped by the deep level traps in the nitride while the remaining move through the nitride, tunnel through the blocking oxide and get collected by the gate. As long as the gate bias is present, more and more electrons get injected into and trapped in the nitride thereby building up the trapped charge. The charge build up will saturate only when the built-in electric filed due to the stored charge becomes large enough to reduce the FN tunneling from the channel or induce injection of holes from gate through the blocking oxide. In the erasing condition, with the negative bias applied to the gate, holes from the channel get injected into the valence band of the nitride, again by FN tunneling, and subsequently get trapped in the nitride (Fig. 1.7b). With the gate voltage applied, the positive charge due to the trapped holes continues to increase and will saturate only when the built-up charge becomes large enough to reduce the FN tunneling from the channel or induces injection of electrons from gate through the blocking oxide. Depending on the initial channel doping (enhancement or depletion type), the threshold voltage of the transistor, Vt, also changes with change in stored charge. This is typically shown as a variation of Vt in the program state (VTP) and erase state (VTE) with the pulse-width of the program or erase pulse. A typical variation of Vt for a depletion mode NMOS SONOS FET is shown in Fig. 1.8.

SiO2 Si3N4 SiO2

Si Si

oooooo oooooo

(a) Unbiased (b) Program (c) Erase

Fig. 1.7 Band diagram of SONOS device 1 Materials and Device Reliability in SONOS Memories 9

Fig. 1.8 Typical Pulse characteristics of a SONOS 2

FET 1 Avg. VTP (V) 0 Avg. VTE (V) -1 VT (V) -2

-3

-4 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 Pulse (sec)

The saturation of the Vt can be seen for both program and erase states, although it is more pronounced for the erase state. This is because the back injection of electrons from the gate in the erase state is more pronounced than the hole injection in the program state on account of the energy barrier difference. This pulse-width versus Vt curve determines the program/erase speed of the memory cell and is widely used for optimizing the SONOS memory cell. The injection of carriers from the channel into the nitride can also be achieved by hot carrier injection (HCI) which is also referred to as Channel Hot Electron injection (CHE). This is achieved by applying an appropriate voltage to the gate to turn it fully ON and applying a high enough voltage to the drain to accelerate the carriers through the channel. As explained earlier, the accelerated carriers become highly energetic near the drain end and a fraction of them can cross the tunneling barrier into the trapping layer and get trapped there leading to a change in the Vt of the transistor. In a NMOS device, programming is done by hot electron injection while erasing is done by hot hole injection or hole band-to-band tunneling. Unlike in FN tunneling, there is a large channel current which is able to supply a copious amount of charge carriers for injection into the nitride in the case of hot carrier injection. Therefore, signiﬁcantly faster program/erase is achieved in the case of hot carrier injection (ls) as compared to FN tunneling (ms). Another carrier injection mechanism for programming is the Channel Initiated Secondary Electron injection (CHISEL). In this mechanism, hot channel electrons cause impact ionization and the energetic holes generated create secondary electrons which get injected into the nitride [27]. The CHE and CHISEL mechanisms are shown in Fig. 1.9. One issue with the program/erase by HCI or CHISEL is that there will be a mismatch between the spatial distribution of electrons and holes in the channel and this can affect the device reliability. Memory cells with source side injection seem to have solved this problem substantially [28, 29]. In some SONOS memories, programming is done by HCI but erase is done by FN tunneling with a high erase voltage. This enables a very fast programming. The slow erase by the FN tunneling does not matter when a bulk erase is done. 10 K. Ramkumar

Fig. 1.9 Schematic and energy band diagram for CHE and CHISEL [27]

1.5 SONOS Memory Cells

Several types of SONOS cells have been proposed over the years for memory applications. They all have their own advantages and disadvantages but may be suitable to meet speciﬁc requirements.

1.5.1 1T Cell

The 1T cell has only one SONOS transistor whose terminals are brought out at metal level in order to be connected to neighboring cells in the array. The terminals of a typical 1T cell are shown in Fig. 1.10. The 1T cell is the simplest of the SONOS cells and will obviously have the smallest cell area.

Fig. 1.10 1T SONOS Cell SL WL BL

BL: Bit line

SL: Source Line

WL: Word line 1 Materials and Device Reliability in SONOS Memories 11

1.5.2 Split Gate Cell

This cell has a SONOS transistor (MG) and a Control transistor (CG) but the channel is shared by both the devices and hence enables area reduction for the cell. The schematic of this cell is shown in Fig. 1.11. In the split gate cell, the ONO dielectric of the SONOS transistor has a hori- zontal portion in contact with the channel and a vertical portion in contact with the word line poly. This happens because the ONO is deposited after the word line formation and it deposits all around the word line (including the sidewall) and on the channel. The oxide on the side wall of the poly word line is sufﬁciently thick so that the ONO on the side wall will not interact with the memory gate voltage.

1.5.3 2T SONOS Cell

This cell has two separate MOSFETs, with the SONOS transistor having the ONO as the gate dielectric and the select transistor having oxide as the gate dielectric. These two transistors are in series as shown in Fig. 1.12.

LBL: Local Bit line

SL: Source Line

WL: Word line

MG: Memory Gate

Fig. 1.11 Split gate cell

SL WL WLS BL

SONOS SELECT

Fig. 1.12 2T SONOS cell 12 K. Ramkumar

The process complexity is signiﬁcantly lower in the case of the 2T cell because both the transistors of the cell are very similar except for the gate dielectric. No special processing is needed except for the addition of a few masking steps. Depending on how the terminals are connected in the array, there can be three types of 2T cell—Dedicated Source Line (DSL) cell, Shared Source Line (SSL) cell, and Common Source Line (CSL) cell. In the DSL cell array, each column of cells has its own Source Line (connecting the sources of all the select transistors) and its own Bit line (connecting all the drains of the SONOS transistors). In order to reduce the cell area, two modiﬁcations of this cell, SSL and CSL, have been proposed. In the SSL cell array, adjacent columns share a common Source Line. This reduces the cell size in the array by about 25%. In the CSL cell array, all the cells in a row share a common Source line. This reduces the cell size by about 40–50%. Obviously, the CSL cell offers the smallest cell size for the memory array. While the area reduction is a strong advantage for SSL and CSL cells, they run the risk of some cross talk between adjacent cells.

1.5.4 MirrorBit® Cell

A MirrorBit cell looks similar to a 1T cell in its construction. However, the tunnel oxide is signiﬁcantly thicker (30–50Å) since the program and erase is done by HCI. The above discussion is not restricted to only ONO stack but applies to any type of charge trap stack. In fact, there is no one single stack or cell adopted by the NVM industry. Different memory companies use different NVM stacks and SONOS cells to claim their own unique features such as small area or read speed or reliability.

1.6 SONOS Memory Cell Architectures

In a non-volatile memory, the SONOS memory cells are connected in the form of an array. There are different kinds of memory cell architectures depending on how the devices are connected in the array and how the bias voltages are applied to the devices. The most important types are—1T cell, 2T cell, and Split Gate cell.

1.6.1 1T-Cell

As the name suggests, the 1T cell just contains the Charge trap or SONOS transistor. A 1T array is just a matrix of SONOS transistors connected as an array as shown in Fig. 1.13. 1 Materials and Device Reliability in SONOS Memories 13

SLn BLn BLn+1 SLn+1

WL n

WL n+1

Fig. 1.13 1T memory array

In a 1T array with NMOS SONOS FETs, the programming of the 1T cell, is done by maintaining the source line, bit line and substrate of the column containing the cell to be programmed at the same reference voltage and raising the voltage on the word line (Row) containing the cell to be programmed to the required positive voltage with respect to the reference voltage. All other columns have their bit lines maintained at a positive voltage with respect to the reference voltage and all other rows have the word line at the same voltage as the reference. With this biasing, only the cell to be programmed gets the required high positive voltage between the gate and the channel which enables the injection of electrons from the n-type channel across the tunnel oxide into the nitride by Fowler–Nordhiem tunneling. These electrons get trapped in the nitride and change the threshold voltage to the required value. For erasing, a similar biasing is done except that the voltages have the opposite polarity. This enables injection of holes from the channel across the tunnel oxide into the nitride to be trapped there thus changing the threshold voltage to the desired value. Depending on the type of the channel (N-channel or P-channel) and the mode (Enhancement or depletion type), the channel becomes more or less conducting. The threshold voltage becomes more positive after programming and more negative after erasing.

1.6.2 2T Cell

The 2T cell consists of the SONOS FET in series with a CMOS FET which acts as a select device that is used to select or unselect the SONOS transistor for writing or for reading data. The 2T memory conﬁguration is shown in Fig. 1.14. 14 K. Ramkumar

Fig. 1.14 2T Cell conﬁguration

Bias voltages to the cell are applied through the word line WL, Select line WLS, Bit line, Source line and the P-well (substrate). A2Â 2 mini-array with such 2T cells, which is a representative of the full array is shown in Fig. 1.15. The min-array shown is for DSL cells but similar arrays can be drawn for SSL and CSL cells. In the 2T cell, the programming or erasing involves not only the source line, the bit line and the word line but also the select gate word line which is used to select the cell to write the data into. The biasing of the SONOS transistor for programming and erasing is similar to that in the 1T cell. In addition, the select word line also needs biasing. The voltage on the select word line containing the cell to be programmed is raised beyond the threshold voltage of the select transistor. This enables the source line voltage to be coupled only to the target cell.

1.6.3 MirrorBit Cell

The MirrorBit cell uses the HCI based method for program and Band-to-band tunneling for erase of the SONOS transistor. This cell uses the NROM concept ﬁrst proposed by Eitan et al. [30]. With a N-channel transistor, the cell is as shown in Fig. 1.16. Since charge storage occurs near the drain end because of large hot carrier injection there, reading is done by reversing the biases which means the terminal at the charge stored end is used as a source. This enables the charge stored to change the threshold voltage of the transistor. Another advantage of charge stored mainly near the drain end is that by changing the biases, charge can be stored in the nitride at both ends of the channel. 1 Materials and Device Reliability in SONOS Memories 15

Fig. 1.15 2T cell memory array

Fig. 1.16 2-bit MirrorBit cell

This enables the storage of 2 bits of data in each cell. As explained previously, reading can be done from either source or drain terminals and in either case the charge at the source end is read. The 2-bit per cell is a major advantage of the MirrorBit cell and this feature is exploited by large density memory manufacturers. The array of such MirrorBit cells is shown in Fig. 1.17. 16 K. Ramkumar

Fig. 1.17 MirrorBit cell memory array

Each cell can store 2 bits on either side of the channel. The array is similar to the 1T cell SONOS array. A specific cell is accessed by biasing the word line and bit line appropriately as in the case of the 1T SONOS cell. The 2 bits per cell operation assumes that the charges stored in the nitride on both ends of the device do not move or communicate with each other. This assumption is reasonable because nitride is a very good insulator and the trapped carriers typically do not mix as long as they are separated by a significant gap. However, with the shrinking of device dimensions in advanced technology nodes, the small movement of trapped charges within the nitride can become significant and limit cell scaling. To write data into a specific cell, the voltage on the appropriate word line is raised and depending on whether the data is to be written on to the source side or the drain side, the appropriate voltages are applied to the source and drain terminals, the high voltage being applied to the side where the data needs to be written into. In this way 2 bits of data can be written into the entire array. For reading, the source and drain of each cell are biased to read only one side of the cell at a time. Typical bias conditions to read different combinations of stored data are shown as an example in Fig. 1.18 with a MirrorBit array made up of enhancement type SONOS transistors. In this example, when there is no charge trapped in the nitride on any side, the channel is turned off on both sides and the cell 1 Materials and Device Reliability in SONOS Memories 17

Fig. 1.18 Bias conditions for a MirrorBit cell should read (11). When there is charge stored on the Source side, the channel on that side is inverted and current ﬂows on application of drain voltage. When the drain and source voltages are interchanged, the channel on the Drain side is read and there is no current ﬂow since there is no trapped charge in the nitride. In this way a (01) is sensed in the cell. Other states of the cell, (10) and (11) are also read in the same way. This MirrorBit cell array is currently used for large density Flash memories for a variety of applications.

1.7 Leakage Currents in SONOS Cells

Since the devices in the SONOS cells are basically MOSFETs, the leakage currents that affect CMOSFETs will also affect the SONOS cell transistors. The usual suspects are the subthreshold leakage and Gate Induced Drain Leakage (GIDL). In a 2T cell, we need to worry about the leakages of both the SONOS transistor and the Select transistor. Also, in the 2T cell, since the intermediate node is ﬂoating, the leakage currents can get enhanced. Also impacting the leakage current is the effect of operating temperature over the speciﬁed range. The net impact of cell leakage will be felt by the charge pump circuits that generate the voltages for program and erase of the cells in the array. In the worst case, the leakages from all the cells add up and this large current has to be supported by the charge pump circuits which will increase its area and hence the total area of the memory in addition to being a drain on the power source. 18 K. Ramkumar

The key cause for the leakage current in SONOS cells is the scaling of the channel length of the SONOS transistor and the Select transistor. While the channel lengths shrink to about 100 nm in a 40 nm SONOS technology, the gate oxide thickness for the select transistor remains high (about 55 Å) to be able to withstand higher voltage and the equivalent oxide thickness of the SONOS stack is also relatively high (about 100 Å). With enhanced short channel effects such as Vt—roll off and lesser control of gate due to the thicker gate dielectric, the subthreshold leakage tends to be relatively high. The GIDL is also a very significant component of the leakage current in a SONOS cell. The GIDL is strongly dependent on the LDD implant profiles and well doping levels in the SONOS as well as the Select transistors. These and the bias voltages which control the internal electric fields and band bending have a strong influence on the GIDL current. As in the case of MOSFETs, the leakage reduction strategies in SONOS cells also focus on the optimization of the implant species and dose/energy of the well/LDD/pocket implants as well as the thermal budget seen by the implanted species. It is the final profile of the LDD dopants and the well-dopant level that determines the band-to-band tunneling which in turn determines the GIDL currents. This implant optimization is usually initiated by TCAD simulations which are followed by actual wafer fabrication with implant conditions highlighted by the simulations.

1.8 SONOS Memory Cell Processing

SONOS cell processing has different complexity depending on the choice of the cell. The simplest for processing are the 1T and 2T SONOS cells. In these, all steps needed for baseline CMOS FET formation are used for the SONOS FET also with minimum or no changes. The only additional steps are the well, channel and LDD implants which are done through special additional masks so that they are blocked from CMOS regions. Separate masks are also used to open windows for removal of sacriﬁcial oxide where SONOS device is formed and for etching the ONO in the CMOS areas. ONO deposition is the other critical step for cell formation. In the case of 1T array, only SONOS devices are formed in the array. In a 2T array, the select transistor is also formed. Baseline processes are used for this device wherever possible (Gate oxide, well implants). Many other features like spacers, silicide and contacts are used for the SONOS cell also without any changes. In the case of split gate cell, because of the construction of the cell, unique process steps will be required. This cell needs two polysilicon layer depositions, two poly patterning steps, ONO deposition on polysilicon sidewalls and ONO removal from one of the sidewalls of polysilicon lines as shown in Fig. 1.19 [31]. 1 Materials and Device Reliability in SONOS Memories 19

MG – Memory Gate

CG – Select Gate

Fig. 1.19 Process ﬂow for split gate cell [31]

The split gate cell process ﬂow will therefore use more masking steps than the 1T or 2T cell ﬂows. The MirrorBit cell should have the same process complexity as the 1T cell. However, novel concepts such as buried bit lines, in which heavily doped silicon lines are used as the bit lines have been proposed and are used in volume production today [32, 33].

1.9 SONOS Memory Cell Reliability

In any type of charge trap memory array, when any particular cell is placed in a “Program” or “Erase” state, ideally, the cell is expected to unambiguously retain the written state over the lifetime of the product across a speciﬁed range of ambient temperature, irrespective of how many times this state is sensed and in spite of how many times neighboring cells are programmed or erased. This means, ideally, the charge stored in the cell is not lost or changed over a long period of time irrespective of what goes on in the neighboring cells. In reality, however, the state does not stay constant because of several phenomena that affect the stored charge. The phenomena that change the stored charge due to repeated sensing of the cell and 20 K. Ramkumar events happening in neighboring cells are called “Disturbs”. The phenomenon that changes the stored charge over time, even with no bias applied, due to loss of the charge is referred to as “Retention”. Another phenomenon affecting the cell is the wear out that occurs due to repeated programming and erasing. This wear out typically slowly shifts the threshold voltages of the cell and is referred to as “Endurance”. The impact of all the effects discussed above is that the program or erase states shift and beyond some point their sensing becomes problematic. These phenomena will be discussed in detail below.

1.9.1 Memory Cell Disturbs

In a non-volatile memory array, since the threshold voltage defines the state of a cell, the program and erase threshold voltages should be clearly separated in their values so that the states can be sensed unambiguously. However, disturbs arise on account of the potentials of certain nodes of the cell reaching values at which either a soft programming of an erased bit or a soft erasing of a programmed bit can occur. They affect the charge storage and hence slightly change the threshold voltages. Charge transport mechanisms such as band-to-band tunneling can get enhanced under certain biasing conditions and these can lead to electron or hole injection into the trap layer which can alter the stored charge slightly. This small change during every program or erase cycle can add up to a significant change in threshold voltages after a large number of program/erase cycles used to write or read other cells on the same bit line or word line of the array. This shift in Vts is insignificant when the program or erase Vts are large. However, with the scaling down of the programming voltages, in advanced technology nodes, the Vts tend to be lower and the shift due to disturbs can become significant enough to cause sensing problems. Inhibit Disturb Inhibit disturb, also referred to as “Program” disturb occurs in an erased, unselected cell during the programming of an erased, selected cell [34]. The disturb can be explained using an example mini-array shown in Fig. 1.20. During programming, with the applied select word line bias, only cell A has large enough voltage between Gate and Drain so that it can be programmed. However, cell B has a bias across the gate not as high as that in cell A but high enough to cause a “soft” programming of the cell. Therefore, as the cell A gets more and more programmed, its Vt keeps increasing but the Vt of cell B also keeps creeping up. This disturb of cell B is referred to as “Inhibit disturb” and its threshold voltage is referred to as inhibited threshold voltage, Vtpi. On account of this disturb, the actual Vt window of the mini-array is less than the difference between the fully programmed cell and a fully erased cell. A typical variation of Vt of cell A (Vtp) and cell B (Vtpi) is shown in Fig. 1.21. 1 Materials and Device Reliability in SONOS Memories 21

Inhibit Disturb

Fig. 1.20 SONOS mini-array showing the inhibit disturb location

Fig. 1.21 Inhibit disturb in a 3 SONOS cell 2 Vtp 1

VT (V) -1 Vtpi -2

-3 1E-5 1E-4 1E-3 1E-2 1E-1 PULSE WIDTH (SECS)

The extent of the inhibit disturb is dependent on the speed at which trapping takes place which in turn depends on the energy distribution of the trap density in the band gap. Shallow traps close to the band edges can get ﬁlled up fast and in such cases the inhibit disturb can be signiﬁcantly larger. Bit-line disturb This disturb, also referred to as “Diagonal disturb” or “Drain disturb”, is generated during the programming of all the rows in the memory array, due to the bit-line 22 K. Ramkumar

Fig. 1.22 Electric ﬁeld and hot hole density variation along channel of SONOS FET during erase and disturb [35]

voltage being raised for every programming pulse. Drain disturb occurs in a cell of an unselected word line that shares the bit line of cells being programmed. Drain disturb in SONOS cells is found to be significant only in programmed state and it leads to a continuous drop in Vt with the programming of other cells on the same bit line. Although the Vt drop looks similar to charge loss during retention, the cause of the drop is different. The drain disturb is due to hole injection from Si substrate into the ONO stack rather than electron loss from the nitride. The hot holes are generated by Band-to-Band tunneling in the SONOS Drain–Gate overlap region and they get injected into the nitride. Although the hole generation is not as high as in a regular erase, due to lower bias voltages, there is still a significant amount of hole injection that can disturb the net charge in the nitride [35]. Figure 1.22 shows the electric field across the channel during a regular erase and during a disturb and the corresponding hole distributions in the two cases. It is clear that the peak electric field along the channel is significantly lower during a disturb as compared to an erase and hence the hole density is also lower. However, this is enough to cause the Vt to shift after many program/erase cycles on a neighboring cell on the same bit line. The drain disturb can impact arrays with both 1T and 2T cells. In the 2T cell, the potential of the internal node plays a key role. The disturb occurs when the gate– drain voltage of the SONOS transistor reaches a value at which charge can get injected into the nitride. The origin of bit-line disturb is illustrated in a 2 Â 2 mini-array of 2T cells shown in Fig. 1.23. In this illustration, with the Bit Line and Source Line held at the specified voltages, only the SONOS transistor in cell A gets the high voltage applied between the gate and drain. This enables that cell to be 1 Materials and Device Reliability in SONOS Memories 23

Fig. 1.23 Drain disturb in a SONOS cell mini-array

Fig. 1.24 Mechanisms of bit-line disturb programmed. However, in cell D, the gate bias condition can generate gate induced drain leakage (GIDL) current which in turn generates hot hole injection (HHI), and “erases” (disturbs) device D if it was initially in the program state. The erased state would be reinforced. If the short channel SONOS drain to source voltage becomes too high then there will be a very high ﬁeld in the channel during weak inversion where hot carriers can 24 K. Ramkumar

0.05

0.00 SL= BL

-0.05

-0.10

-0.15 SL Floating -0.20

SONOS VTP Shift (V) -0.25

-0.30 1E+01 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 Disturb Cycles

Fig. 1.25 Bit-line disturb with cycling be generated, and holes will be injected into the programmed memory layer causing a disturb. The different mechanisms that can give rise to the bit-line disturb are summarized in Fig. 1.24. The effect of bit-line disturb is that a programmed cell gets soft erased with the subsequent programming of all remaining cells on the specific bit line. Given a long enough time the device will become completely erased. If proper cell biases are applied, the disturb time can be extended for several million disturb cycles. The source of SONOS transistor D is more susceptible than the drain relative to Vtp shift. A typical variation of bit-line disturb over programming cycles is shown in Fig. 1.25. The disturb is very small initially but with larger number of cycles it increases significantly as more and more charge gets trapped in the nitride. The disturb is also very sensitive to bias conditions as shown. It is much lower when the Source line (SL) and the Bit line (BL) are shorted as compared to when the Source line is left floating since several disturb mechanisms are shut off. To reduce the bit-line disturb, the leakage mechanisms such as GIDL need to be reduced by optimizing the dopant profile in the LDD region of the SONOS transistor. The disturb is also reduced by changing the voltage on the unselected word line appropriately. Read Disturb Read disturb happens when the threshold voltage of a programmed cell changes due to repeated reading of the cell. This disturb happens because the voltages applied for reading can give rise to some Hot electron or hole injection from the channel into the trap layer. In the 2 Â 2 mini-array, depending on the states of the four SONOS transistors, the disturb due to reading will be different. Erased cells can get soft programmed due to Channel Hot Electron injection. Programmed cell can get soft erased by hole tunneling. 1 Materials and Device Reliability in SONOS Memories 25

Fig. 1.26 Disturb mechanism in split gate cell [36]

Liu et al. have done a detailed study of all the disturbs in a 2T SONOS array and reported the data [34]. They have also proposed ways to reduce the disturbs by changing the bias conditions and the program/erase conditions. Disturbs in Split Gate cell Disturbs in the split gate SONOS cell using the source side injection for programming has been studied [36]. The split gate cell studied is shown in Fig. 1.26. The disturb mechanisms have been studied in a 2 Â 2 array of cells. The mechanisms of disturb are different in the cells of this mini-array based on the bias voltages seen by the devices. They have been identiﬁed as punch through and band to band tunneling, as shown in Fig. 1.27. The inhibit voltage on the WGn−1 word line impacts the two disturbs mechanisms differently and hence the threshold voltage shifts in opposite directions with change in the inhibit voltage (Fig. 1.28). Disturbs in MirrorBit cell Disturbs in the MirrorBit cell are complicated by the fact that information is stored in the charge trap layer at both ends of the channel. This manifests as a change in Vt of the unprogrammed bit as the other bit is getting programmed. This effect is illustrated in Fig. 1.29 and is commonly referred to as Complimentary Bit Disturb (CBD). CBD occurs because of the penetration of the electric ﬁeld from the charge stored at one end of the channel to the channel of the other, unprogrammed bit. A simulation study done by Kathawala et al. [37] illustrates this effect in Fig. 1.30 which shows the distribution of gate current along the channel of a MirrorBit cell. The plot shows that the gate current, which is a measure of electron injection into the trap layer, spreads towards the other end of the channel, especially in the case of CHISEL. The impact of CBD is minimized by optimized biasing and junction engineering. The MirrorBit cell is very robust against the Program Disturb and Bit-line Disturb. Typical variations of the Vts with cycling incorporating the effects of these disturbs show almost no degradation (Fig. 1.31). 26 K. Ramkumar

Fig. 1.27 Disturb mechanisms in split gate cell [36]

Fig. 1.28 Vt shift due to disturbs in split gate cell [36]

Fig. 1.29 Variation of Vt due Cell vt vs.read Vd Source to CBD in a MirrorBit cell Vts (V) Source

read vd (v) 1 Materials and Device Reliability in SONOS Memories 27

Fig. 1.30 Illustration of complimentary Bit disturb [37]

Fig. 1.31 Bit-line and Inhibit disturbs in MirrorBit cell

Bit Line Disturb

Inhibit Disturb

1.9.2 SONOS Endurance

Endurance of a NVM cell refers to the wear out that occurs in the NVM device due to repeated cycling between “Program” and “Erase” states. This wear out manifests itself as a slow shift of the threshold voltages with repeated program/erase cycles. The endurance performance of a NVM cell is speciﬁed as a maximum threshold voltage shift after 10 K or 100 K or 1 M or higher program/erase cycles, depending on the product application. The mechanism of the wear out is typically interface state generation due to transfer of high energy charge carriers across the silicon-tunnel oxide and gate-blocking oxide interfaces. The interface state density increases with the number of cycles and hence the threshold voltages also change with the number of cycles. Since the interface states disturb the charge injection into the trap layer, the charge trapping can get reduced with cycling and this will result in a decrease of the threshold voltage during program or erase. Such a decrease can 28 K. Ramkumar

Fig. 1.32 Threshold voltage in variations in SONOS during endurance cycling

lead to a gradual closing of the Vt window with increase in the number of cycles. Endurance performance of SONOS is generally very good as shown in Fig. 1.32. 6 Typically there is minimal shift in the Vts even after 10 cycles. The interface state generation model used to explain the Vt shift during endurance cycling is similar to that in the case of Floating gate technology. However, since the tunnel oxide in SONOS is much thinner, the carriers can tunnel through it much more easily and hence the damage to the interface is much less. This results in lower density of interface states generated during cycling. However, when the endurance requirement is very severe, even SONOS can fall short and in such cases, some improvement is required. There is another type of endurance effect in non-volatile devices and that is the charging up of the interface states at the Si–Tunnel oxide interface without much damage to the interface (less degradation in the charge injection). This effect usually shifts both the Program Vt and erase Vt in the same direction, depending on the nature of the interface charge. This is common in devices that have a thick tunnel oxide. However, in SONOS devices that use FN tunneling for both program and erase, there is a little interface charging because the electrons and holes are able to tunnel into and out of the nitride. Therefore there is almost no shifting of the Vts due to interface charging but the shifts are mainly due to interface damage which tends to close the Vt window. The methods to improve endurance of a SONOS cell involve changes to the ONO stack to reduce the interface damage by using techniques such as nitridation of the SiO2–Si interface. Making the blocking oxide thicker will also reduce the damage to the gate–blocking oxide interface. Deuterium anneal has also been proposed for endurance improvement [38]. The improvement has been shown to be due to the reduction of interface trap density on account of the Deuterium, as shown in Fig. 1.33. 1 Materials and Device Reliability in SONOS Memories 29

Fig. 1.33 Effect of D2 anneal on interface trap density generation during cycling [38]

Fig. 1.34 Endurance performance of tunnel oxide grown in N2O[39]

Wu et al. studied the impact of N2O grown tunnel oxide on the reliability of the SONOS device [39]. This study showed that growing the tunnel oxide in N2O ambient at high temperature of 900 °C improves the retention after cycling, as shown in Fig. 1.34. This was attributed to the lower level of charge trapping in the oxide grown in N2O, due to N2 incorporation which reduces the charge build up in the interface. N2 incorporation in the tunnel oxide can also be achieved by growing the oxide in pure O2 but annealing it in N2O or NO. Wang et al. [40] used this method on a BE-SONOS stack and demonstrated improved endurance performance (Fig. 1.35). 30 K. Ramkumar

Fig. 1.35 Impact of N2O anneal of tunnel oxide on the endurance of SONOS [40]

All these results essentially show that incorporation of D2 or N2 at the Si-tunnel oxide interface passivates a signiﬁcant number of dangling bonds which leads to lesser amount of interface trapping and a smaller interface charge. This, in turn, should improve the endurance performance.

1.9.3 Data Retention

Data Retention in the NVM cell is the most critical specification because it indicates how long the cell can retain the data written into it. The retention is specified as the number of years at a given ambient temperature for which the state of the memory cell can be read without any ambiguity. The data retention issue arises because the charge stored in the device is slowly lost over time. Higher ambient temperature accelerates the charge loss. In the SONOS memory device, the charge loss from the charge trap layer, which is Silicon nitride in most devices, can be due mechanisms such as trap assisted tunneling in the nitride and tunneling through the thin tunnel oxide. Charge loss can also be due to lateral migration of trapped charge in the nitride layer. Although the nitride is considered as an insulator, in reality, there is some movement of trapped charge in the nitride if it is present as a continuous film between adjacent devices. This can manifest itself as a data retention loss. To prevent this, additional process steps are used to cut the nitride in the region between devices in order to break the continuity of the film. The trapped charge transport in the nitride also limits the scaling of the MirrorBit device for a 2-bit operation. The 2-bit operation of the MirrorBit cell is limited to the 45 nm technology. The retention performance is characterized by measuring the variation of program and erase threshold voltages with time at an elevated temperature. A typical retention characteristic is shown in Fig. 1.36. 1 Materials and Device Reliability in SONOS Memories 31

Data Retention at 85C 10 yrs

Program VT (V) VT

Erase

1.0E+02 1.0E+04 1.0E+06 1.0E+08 Time (sec)

Fig. 1.36 Vt variation in SONOS during retention bake

As can be seen from this graph, the program and erase threshold voltages decay with time. The rate of decay depends on the temperature during the retention testing. The temperature is often elevated substantially so that the decay can be accelerated and the retention can be tested in reasonably short time of 10–20 h.

1.9.4 Temperature Acceleration—Activation Energy (Ea)

Retention is one of the key parameters measured in the testing of wafers with SONOS memory arrays. To ensure that the dies on the wafer meet the retention specification, an accelerated test has to be performed on each die. The temperature and time of the accelerated test will need to be determined based on the retention specification and the activation energy of the SONOS stack. Several models have been evaluated for the SONOS and it is found that the conventional Arrhenius (1/T) model is not always able to fit the measured retention time with temperature. A new T model fits the observed data much better, as shown in Fig. 1.37. The T model seems to predict the retention behavior of the ONO stack more accurately [41]. Using this model, one can calculate the constants in the equation 32 K. Ramkumar

Fig. 1.37 Fitting of retention by (1/T) and T models [41]

À T T tR ¼ tO Á e O

With the fitting of the observed data to the model, one can determine acceleration test temperature and time which is equivalent to the required lifetime at the specified temperature. Using the equation one can come up with a retention cal- culator in which a user can input the actual operating temperature profile and determine whether the stack can meet the retention specification.

1.10 SONOS Memory Stack Enhancements—Impact on Reliability

The SONOS stack is the most critical component of any SONOS memory array and needs the most amount of optimization. The retention performance is the main weakness of the SONOS memory stack as compared to the ﬂoating gate stack. This is mainly due to the tunnel oxide being thin which allows charge loss from the trap layer to the substrate. The carrier transport in the trap layer has been studied extensively and the key transport mechanisms have been identiﬁed [42, 43]. When considered as a three layer stack made up of a bottom dielectric, a charge storage dielectric and a blocking dielectric, two approaches can be used for the optimization —layer thickness changes and layer stoichiometry changes. The layer thickness impact is quite straight forward. Making the bottom dielectric thicker reduces the charge loss from the trap layer to the channel but it also reduces the FN tunneling current from the channel to the trap layer. Making the top dielectric thick will reduce the interaction between the gate and the trap layer but at the same time increases the voltage needed for program/erase. Reducing the trap layer thickness impacts the amount of charge stored while increasing it impacts the program/erase voltage. Thus, the options to optimize the three layer stack by changing layer thicknesses have both pros and cons and hence are limited in their scope. These 1 Materials and Device Reliability in SONOS Memories 33

Fig. 1.38 BE-SONOS stack

limitations have led to a signiﬁcant amount of research to change the stack layers so as to improve performance and reliability without compromising on any parameter.

1.10.1 BE-SONOS

Band Gap Engineered SONOS, also known as BE-SONOS was proposed to improve the retention property of the SONOS device without compromising on the program/erase efﬁciency. In this device, the single bottom tunnel oxide is replaced by a ONO stack which has a similar equivalent oxide thickness (EOT) but is physically much thicker. The resulting multilayer stack is shown in Fig. 1.38.

Fig. 1.39 Band diagram of BE-SONOS stack during programming and retention 34 K. Ramkumar

Fig. 1.40 Leakage and FN tunneling in the ONO tunnel dielectric of BE-SONOS [44]

The band diagram of the ONO stack tunneling dielectric (O1N1O2) with a bias applied to the gate and during retention with no bias applied is shown in Fig. 1.39. With a negative voltage applied to the gate, the band bending is such that the holes in the channel can tunnel through the ONO dielectric and get injected into the trap layer (Fig. 1.39a) where a fraction gets trapped to give rise to the trapped charge. With no bias applied, as in the case of retention, hole tunneling through the O2N1O1 dielectric stack is greatly reduced and hence the charge in the trap layer is not lost (Fig. 1.39b). The effectiveness of the ONO stack tunnel dielectric to yield a substantial tunneling during program/erase but have minimum leakage current is well illustrated in Fig. 1.40 for a specific ONO stack tunnel dielectric. Closer examination of the BE-SONOS stack shows that the ONO tunnel dielectric layers are extremely thin, of the order of 1.5–2 nm. Uniform deposition of continuous films of this thickness was unthinkable even 20 years ago. However, with the availability of new processing techniques such as Atomic Layer Deposition (ALD), it is possible to deposit such thin films with good repeatability. Therefore, BE-SONOS is a production worthy approach to improve the reliability of charge trap devices. In fact, this approach is used by Macronix to produce high density NAND Flash memories [44, 45].

1.10.2 TANOS Device

TANOS Stands for TaN–Al2O3–Silicon Nitride–Silicon dioxide–Silicon. This is also a three-layer charge trap memory stack but in this case the materials of the stack are changed so as to improve the reliability of the stack. TANOS was first proposed in 2003 by Lee et al. [46]. In this stack Al2O3 replaces the conventional SiO2 for the blocking oxide. The high dielectric constant of this blocking oxide reduces the electric field across this layer and hence the field across the tunnel oxide will increase. This means the tunnel oxide thickness can be increased in order to 1 Materials and Device Reliability in SONOS Memories 35

Fig. 1.41 Band diagram of TANOS device [46]

bring back the electric ﬁeld to the original value. A thicker tunnel oxide improves the data retention (un-biased condition) performance of the cell dramatically. The energy bad diagram of this stack is shown in Fig. 1.41. This stack has the further advantage of having a metal gate with the metal work function being large which helps to reduce the back injection of carriers from the gate to the trapping layer. This helps reduce the damage to the trap layer-blocking oxide interface and improves the endurance performance of the stack. This stack

Fig. 1.42 Endurance and Retention characteristics of TANOS [47] 36 K. Ramkumar has been studied in depth by a few research groups and the reliability has been characterized in detail for NAND memories [47, 48]. Robust retention and endurance performance have been demonstrated in TANOS at 63 nm technology node, as shown in Fig. 1.42.

1.10.3 Other Improvements to Charge Trap Memory Stack

High Work function gate for NMOS SONOS FET P-type doped polysilicon gate for a N-channel SONOS FET can be used as a way to increase the energy barrier for electrons to cross from the gate to the nitride and subsequently reduce the trapped hole charge in the erased state (erase saturation). Another option is to use high work function metal gate such as TaN which should have a similar impact. In either case, when the charge injection from gate to nitride is reduced, more charge can be trapped during erase and hence the erase can be deeper without saturating. A detailed comparison of TaN gate and N+ polysilicon gate on SONOS device performance has been reported by Lee [46]. A key comparison is on the erase characteristics in which the high work function gate enables a deeper erase as shown in Fig. 1.43. The high-work function metal gate is a very attractive option when SONOS is integrated into the High K-Metal gate process ﬂow where this metal is available as a standard feature of the baseline for PMOS FETs. Charge trap memory stack with High K dielectric The most widely used CMOS process ﬂows at 28 nm and beyond are based on the high K-metal gate option in which a Hafnium based oxide is used as the gate dielectric for the core devices and metals with appropriate work functions are used as gates. Therefore it is imperative that SONOS devices with metal gates will need to be characterized and optimized. A limited amount of work seems to have been

Fig. 1.43 Erase characteristics comparison between SONOS and TANOS [46] 1 Materials and Device Reliability in SONOS Memories 37

Fig. 1.44 Threshold Voltage variation of SONOS with SiO2 and HFSiON blocking oxide [49]

reported on this topic since NVM technologies are still at least one node behind the logic technologies. However, this topic will become signiﬁcant in the coming years. Depending on how the SONOS device is integrated, the high-K dielectric can replace or be a part of different layers of the SONOS stack. In a conventional SONOS device, the simplest memory stack would have the high-K dielectric as part of the blocking layer. One of the early studies on this topic was reported by Duurenn et al. from Phlilips Research [49]. In this study, the HfSiON was incorporated as part of the blocking layer and its impact on the program-erase behavior was examined. The threshold voltage variation during program-erase clearly indicates that the high-K dielectric prevents the erase saturation seen in the pure ONO stack (Fig. 1.44). The high-K dielectric can also be incorporated into the tunneling layer of the charge trap memory stack and this will impact the hole tunneling from the substrate

Fig. 1.45 Program—erase characteristics of SONOS for different thicknesses of high-K dielectric in the tunneling layer [50] 38 K. Ramkumar

Fig. 1.46 Improvement in endurance in BE TANOS using HfSiON [51]

to the trap layer on account of the lower band offset of the high-K layer. This enables a deeper erase with the high-K tunneling layer as shown in Fig. 1.45. TANOS device with HfSiON as part of the tunneling layer was investigated by Molas et al. [51]. With a band gap engineered TANOS having HfSiON as part of the tunneling layer a signiﬁcant improvement in endurance was demonstrated, as shown in Fig. 1.46. Several other studies have evaluated stacks with high-K dielectrics for the bottom and top layers [50]. Most of these report superior erase characteristics of the memory stack. The adaptation of these stacks by the industry is more dependent on the complexity of process integration than the beneﬁt for the reliability of the stack. In recent years there has been extensive studies reported on using Al2O3 as part of the blocking layer in SONOS and TANOS devices. Although the dielectric constant of Al2O3 is not too high, the availability of mature tools and processes for its deposition has made it a popular choice. Published literature on this topic covers BE-SONOS and 3D SONOS [24]. Another option that has been evaluated is the use of high-K dielectric as the trapping layer in the SONOS stack. Here the choice of the material and processing is directed towards generating a trap rich layer. Techniques such as Nitrogen implantation are adopted to make the high-K layer suitable. When the materials and deposition tools become more readily available, it may become feasible to have an all high-k layer charge trap memory stack. A study published by Buckley [25] evaluated a variety of Hf based oxides for the trap layer of SONOS. This study concludes that the crystallization of the high K layer subsequent to deposition holds the key to its success as a trap layer. It is found that the more crystalline the high-K layer the higher is the trapping capability The study also found In addition to deeper traps, the smaller trap cross section in the Hf based high-K dielectric is shown to be the cause of the superior retention performance (Fig. 1.47). Once high-K dielectric-based stacks will become feasible, replacing the polysilicon gate with an appropriate metal gate is a logical next step. Since metal gate is a fairly mature process option at 28 nm node and beyond, there should be 1 Materials and Device Reliability in SONOS Memories 39

Fig. 1.47 Dependence of retention on trap cross section and trap energy level in SONOS with HfSiON trap layer [25]

relatively less complexity in getting to a high k-metal gate SONOS stack. In the best case scenario, such a stack should have very good erase characteristics, robust retention and very good endurance. MirrorBit or NROM type of memory stack using high K dielectric for the trap layer is another interesting option. An Al2O3 trap layer-based stack has enabled lower voltage program-erase and shown acceptable retention [52] (Fig. 1.48). The high-K trap layer shows much higher program speed as compared to Si3N4 or Al2O3. Other high-K dielectrics have also been evaluated [53]. Although it is not a true high-K material, Al2O3 can also be considered as one. There were studies reported

Fig. 1.48 MirrorBit memory device with high K trap layer [52] 40 K. Ramkumar using this material as port of the ONO stack. The reason to study this material was because deposition techniques such as ALD were available to deposit thin ﬁlms of Al2O3 with good uniformity as compared to Hf based dielectrics. Specht et al. [54] studied SONOS device with Al2O3 replacing SiO2 as the blocking dielectric. Integration of metal gate and Al2O3 as a part of BE-SONOS was reported by Lai et al. [55]. This study found that the Al2O3 and metal gate help greatly in reducing the injection from the gate during erase and this reduces erase saturation signiﬁcantly. Nitridation of SONOS stack layers Nitrogen incorporation into the layers of the SONOS memory stack is another process option available. There are several mature options available such as Nitrogen implantation, thermal nitridation and plasma nitridation. As discussed earlier, in SONOS memory device, a thin nitrided tunnel oxide can have reduced Dit generation in the SiO2–SI interface. Incorporation of Nitrogen into the trapping layer has also been examined with the aim of modulating the trap density. It has been reported that N2 implantation of the silicon nitride increases the density of deeper traps [56].

1.10.4 Novel Materials for Charge Trap Layer

New materials have been explored for the charge trap layer. La2O3 is one of the materials investigated by Park et al. [57]. In this study, an ultrathin La2O3 layer was inserted in the middle of the SiN trap layer and annealed at high temperature to mix the layers. Other oxides such as Ga2O3,Al2O3 and ZrO2 were also studied. It was found that the La-doped trap layer showed the best retention performance (Fig. 1.49).

Fig. 1.49 Retention performance of SONOS with oxide dopants in nitride layer [57] 1 Materials and Device Reliability in SONOS Memories 41

Fig. 1.50 Dependence of charge loss on thickness of La2O3 layer [57]

The superior retention is attributed to the deep traps generated due to the doping by La2O3. The thickness of the La2O3 layer is critical and needs to be about 4A. Beyond 6A, the charge loss increases signiﬁcantly as shown in Fig. 1.50. ZrO2 as a trapping layer was studied by Wu et al. This study showed that nitrogen stabilization of a crystalline ZrO2 layer helps to increase the trapping sites which enable a lower voltage, higher speed operation of the memory [58]. Formation of the blocking oxide by radical oxidation There are several options for forming the blocking oxide of the charge trap memory stack. In a SONOS stack, the blocking oxide is SiO2 and this oxide can be formed in multiple ways. 1. The oxide can be deposited on top of the silicon nitride by thermal Low Pressure Chemical Vapor Deposition (CVD) by reacting a silicon containing precursor such as Silane (SiH4) or Dichlorosilane (SiH2Cl2) with an oxygen containing gas such as O2 or N2O, at elevated temperatures in the range 700–800 °C. 2. The oxide can be grown by a thermal oxidation of the top portion of the Silicon nitride. Conventional wet oxidation can grow the oxide but requires a large thermal budget (temperature and time). Radical oxidation such as In Situ Steam Generation (ISSG) can grow this oxide with relatively low thermal budget (high temperature rapid oxidation). 3. Plasma oxidation with Oxygen plasma can also be used to grow the blocking oxide by oxidizing the silicon nitride. This is a low temperature radical oxidation process (about 400 °C) which is able to oxidize the nitride layer. The blocking oxide grown by any of the above methods is denser and more uniform than the oxide deposited by CVD process. The ISSG is likely to be used widely since most advanced technologies use this process for growing the gate oxide and provides an opportunity to simultaneously grow the blocking oxide of the ONO and the gate oxide. 42 K. Ramkumar

Fig. 1.51 SONOS device with Si nano crystals in the nitride layer

Other improvements to the Charge Trap stack Other modiﬁcations to the charge trap stack have been studied to improve the reliability. One of the signiﬁcant changes is the removal of the trap layer between adjacent devices in a memory array in order to prevent lateral movement of trapped charges between the cells. This is achieved by a separate mask and etching process steps. Nanocrystal SONOS A key innovation in SONOS which was proposed in the early 2000s was nanocrystals for the key layers of the ONO stack. The initial publications featured Silicon nanocrystals used to make ONO structures. More recent work [59–61] has shown SONOS based on silicon nanocrystals in the charge trap layer, as shown in Fig. 1.51. A key advantage of this charge trap memory stack is the absence of lateral stored charge migration which is an issue for a continuous charge trap layer in conventional SONOS. In this device the size and density of the nano crystals depends on the deposition time as shown in Fig. 1.52. The retention behavior also depends on the deposition time (Fig. 1.53).

Fig. 1.52 Nano crystal size dependence on deposition time [61] 1 Materials and Device Reliability in SONOS Memories 43

Fig. 1.53 SONOS retention dependence on nano crystal size [61]

As can be seen from these figures, the larger nanocrystals help the retention performance. However, the challenge with this type of device is to get a uniform distribution of the nanocrystal size over a large volume of wafers. SONOS technology with FINFETs FinFET is the widely accepted device for high performance logic circuits in 21 nm technology and beyond. The advantages of the FinFET architecture for device drive current and leakage have been widely reported for CMOS FETs in advanced platforms. When SONOS memory is embedded into such a logic platform, the FinFET architecture and process is available to be used for SONOS devices also. The impact of FinFET architecture on SONOS has been studied quite extensively in the last 10 years. Most of the studies have been on FinFETs on bulk silicon, not SOI. One of the early studies was reported by Hsu et al. [62]. This study showed that the electric field gets significantly enhanced in the curved part of the fin (region

Fig. 1.54 Schematic of FinFET SONOS 44 K. Ramkumar

Fig. 1.55 Field enhancement in FinFET SONOS [62]

I in Fig. 1.54). The enhancement factor (FE) can be as high as 2.0 depending on the width (Fig. 1.55) and this substantially increases the carrier injection from the channel into the trap layer of the charge trap memory stack. Because of the different electric fields in the flat and curved portions of the fin, the carrier injection will also be nonuniform. On account of the field enhancement, the program and erase speeds are significantly increased in a FinFET. Retention behavior of FinFET SONOS has been studied by Lee et al. [63]. In this study, the temperature acceleration and field acceleration were both considered to come up with a retention model for the FinFET SONOS. S.H. Lee has shown that with a FinFET SONOS device with high K blocking dielectric (Al2O3), cell current which is 3X higher than in a planar device can be achieved [64]. The band gap engineered SONOS stack, with a ONO stack acting as the tunneling layer, can be implemented in the FinFET SONOS device also. The same is true for the TANOS stack. Hwang discussed the process flow used for the formation of FinFET SONOS [65]. The flow uses the recess of the STI oxide to form the fins (Fig. 1.56). The detailed process sequence for SONOS FinFET formation is: • Fin patterning • Dry etching with hard mask trimming • STI gap fill and CMP • STI Oxide recess by blanket etch back • Deep well implant • Sacrificial oxide removal • Tunnel oxide growth • Charge Trap layer deposition • Blocking oxide deposition • Gate layer deposition • Gate patterning • LDD and pocket implants 1 Materials and Device Reliability in SONOS Memories 45

Fig. 1.56 Process ﬂow for FinFET SONOS [65]

• RTP Implant anneal • S/D Formation • Contact formation • Back-end process Samsung and Macronix have published process flows that use this approach but have some differences in the actual flow. The same flow can be used to form FinFETs with BE-SONOS and TANOS charge trap memory stacks. A critical review of the different types of charge Trap memory devices has been published by Lue et al. [66]. This review covers all the different devices that have been discussed in this chapter.

1.11 Embedded Charge Trap Memories

Embedded non-volatile memories are a critical component in several integrated circuits such as microcontrollers, smart cards, touch screen controllers, and many Internet of Things (IOT) applications. The requirements for these memories are different from the standalone memories. The densities of the embedded memories are much smaller, in the range of 1–16 Mb. The most critical requirements for the embedded NVM memory are 46 K. Ramkumar

1. Minimal area for the array 2. Wide range of operating temperature for automotive applications 3. Low cost of integration into a baseline process ﬂow—minimum added masks 4. No impact on baseline FETs, to ensure device models and IP can be reused 5. Robust endurance and retention 6. Program/Erase time and access time to meet product needs 7. Access time to meet product needs. The integration of the NVM module into a CMOS baseline presents challenges for the different non-volatile devices to be viable options for embedded memories. Since the 1990s, the Floating Gate ﬂash has been the dominant player in embedded Flash. However, in the last few years, SONOS has emerged as a strong option because of the ease of integration compared to Floating gate. A comparison of

Fig. 1.57 Comparison of mask layers between embedded floating gate and SONOS processes [15] 1 Materials and Device Reliability in SONOS Memories 47 masking layers in a floating gate based and a SONOS based embedded NVM technology is given in Fig. 1.57 [15]. It is clear that the SONOS based approach is much simpler for embedded NVM. It is known that floating gate has superior retention performance because the tunnel oxide is much thicker than in SONOS. However, SONOS memories with hot electron programing allow the use of thicker tunnel oxide and hence these memories have very robust retention. The lower cost of the embedded SONOS is making it very attractive for many products and hence several foundries are in the process of developing this technology. A key desirable feature in an embedded memory is that it should not require a supply voltage higher than what can be handled by the rest of the CMOS circuitry. For example if the rest of the chip uses 2.5 V, the embedded memory should be able to use the 2.5 V CMOS devices for its Program/Erase voltage generation. Based on the reliability of the 2.5 V devices, the high voltage circuits can handle a maximum of 8.0 V. This means that the embedded memory should be able to function at 7.5 V nominal voltage for its program/erase operations. In this respect the SONOS cells offer distinct advantage. Floating gate memories typically require 12–14 V for erase and this needs a new high voltage device to be incorporated into the memory circuit just to be able to handle high voltages of the program/erase voltage generation. This implies the incorporation of an additional thicker gate oxide into the process flow for these high voltage devices. The low voltage program/erase capability is one of the key reasons for which SONOS memory is becoming very attractive for embedded memories. While this is an extremely attractive feature of the SONOS technology, it poses significant challenges for device and memory cell optimization. The program and erase Vts will be lower and hence the impact of Vt shifts due to cycling or disturbs or retention become much more significant with lower beginning of life (BOL) Vts and Vt window. To reduce or eliminate the shifts, careful optimization of the various implantations is required with the aid of process simulations.

1.12 Challenges of Integration of SONOS Memory Module

They key challenge of integrating a charge trap device into a CMOS baseline is to preserve the baseline device characteristics. This means the thermal budget of the additional steps has to be low. In addition the new steps should not introduce defects due to the additional deposition or etch steps. The thermal budget can be minimized by using low temperature processes such as Chemical vapor deposition (at about 750 °C) or Atomic Layer Deposition (at about 500–600 °C). In the integration of SONOS, for example, the SONOS module is introduced between the CMOS well/channel implants and the periphery gate oxide steps. After all CMOS well and Channel implants are done, windows are opened in the pad oxide using a masking step. The SONOS channel implants are done through this mask. Using the 48 K. Ramkumar

ONO PRECLN

WAFER START ONO DEP SONOS LDD MASK STI ONO MASK SONOS LDD ONO ETCH SPACER 2 DEP SPACER 2 ETCH DEEP N-WELL, WELL, CHANNEL GATE OXIDE PRECLNS – N & PMOS DUAL GATE OIDE S/D IMPLANTS GATE DEPOSITION SILICIDE BLK OX DEP GATE PATTERNING SILICIDE BLK MASK TUNNEL MASK SILICIDE BLK ETCH SONOS CH IMPLTS SILICIDE PROCESS PAD OXIDE ETCH SPACER 1 DEP SPACER 1 ETCH LDD IMPLANTS REST OF PROCESS

BASELINE NEW STEP / PROCESS

Fig. 1.58 Process flow for embedded SONOS same mask, the pad oxide is then removed using a BOE etch. Subsequently, the resist is removed and a blanket ONO is deposited by Chemical Vapor Deposition, using either an in situ deposition in a single tool or a multilayer deposition in multiple tools. Following the ONO deposition, using masking and dry etch, the ONO is removed from everywhere except in the SONOS region. This is then followed by dual or triple gate oxidation steps and polysilicon deposition which are part of the baseline flow. After polysilicon patterning, the LDD and pocket implants for the SONOS device are done through a special mask. The rest of the process follows the baseline flow. The insertion of SONOS typically takes an addition of 3– 5 masks to the baseline flow. A typical process flow for this type of integration is as shown in Fig. 1.58. Although this is the general approach for SONOS cell integration, there are some innovative aspects that use the baseline process to form the SONOS memory stack. For example, the periphery gate oxidation, which is typically a radical oxidation such as ISSG, can also be used to grow the blocking oxide of the ONO stack. This oxide has better thickness uniformity and better quality (being thermally grown). Another exciting option is to use the high K dielectric layer, used as the gate dielectric for the core, as a part of the blocking oxide, thereby reducing he back tunneling of carriers from the gate to the charge trap layer without increasing the EOT of the ONO dielectric significantly. Similarly, the metal gate used for the core devices can be used as the gate for the CT stack also. By choosing the right metal (NMOS or PMOS), the erase saturation can be significantly reduced. 1 Materials and Device Reliability in SONOS Memories 49

1.13 Charge Trap Memory—Present and Future

The SONOS memory based on SONOS is in volume production for large scale standalone NOR memories. The MirrorBit cell based memories are manufactured by Cypress Semiconductor and the BE-SONOS based memories are manufactured by Macronix. The density of the memories available in the market is in the range 512 Kb–2 Gb. These memories are available as both Serial and Parallel NOR Flash. The table below indicates how these memories stack up against each other and against Floating gate Flash.

Manufacturer Cypress Micron Cypress Winbond Cypress MXIC Micron Cypress Technology MirrorBit FG FG FG FG FG FG MirrorBit Node (nm) 65 65 65 58/58S 55 55 45 45 Status Prod Prod Development Prod Feasibility Prod Prod Development Prgm/Erase CHE/HHI CHE/FN CHE/FN CHE/FN CHE/FN CHE/FN CHE/FN CHE/HHI Method Endurance 10 k min/ >100 k >100 k >100 k >100 k Typ >100 k >100 k (cycles) 100 k typ 100 k Data Ret. 20 >20 Typ 20 >20 Typ 20 20 Typ 20 25 (yrs) Operating −40–105 −40– −40–125 −40–105 −40–125 −40–85 −40–85 −40–125 Temp (°C) 125

SONOS memory, is also becoming a very attractive option for embedded memories on account of the lower cost of integration into the CMOS baseline. A comparison of the various competing technology options for the embedded Flash is given below. 50

90 nm embedded flash 55 nm embedded flash 40 nm embedded flash Company Cypress Renesas SST Freescale Cypress Cypress SST Freescale Cypress Cypress Renesas SST Technology FG MONOS FG SONOS FG SONOS FG FG SONOS SONOS MONOS FG Cell 1T 1.5T 1.5T 1.5T 1T 2T 1.5T 1T 2T 1.5T 1.5T 1.5T Endurance (K) 100 30 100 10 100 100 10 100 100 100 100 100 Retention 20 yrs @ 10 yrs 10 yrs @ 10 yrs 20 yrs @ 10 yrs @ 10 yrs @ 10 yrs 10 yrs @ 20 yrs @ 20 yrs 20 yrs 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C Temperature −40 to −40 to −40 to −40 to −40 to −40 to −40 to −40 −40 to −40 to −40 to −40 to range (°C) 125 125 85 105 125 85 125 to 125 85 125 125 125C Additional 13179915412581713 Masks .Ramkumar K. 1 Materials and Device Reliability in SONOS Memories 51

1.14 NVM Roadmap

The non-volatile memory roadmap as deﬁned by ITRS is shown in Fig. 1.58.

As the Roadmap shows, we are at the cusp of major changes in the materials used for the SONOS memory devices. An order of magnitude increase in trap density is expected from 2016. This coincides with the changeover from SiN or SiN/Al2O3 type of dielectric to higher K dielectric for the charge trap layer. Blocking dielectric thickness is also expected to decrease by 2018. The tunnel dielectric mentioned in this table is fairly thick which means it is referring only to memory cells that use HCI for program/erase. As the roadmap indicates there are no known solutions to meet these requirements. It will require new technological breakthroughs to achieve the goals set by the roadmap.

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Konstantina Saranti and Shashi Paul

Silicon nanostructures are discussed in this chapter. First, the field of nanotechnology in relation to the properties and basic physical phenomena of nanomaterials is presented. Then, the current status of nanomaterials used for memory storage devices is reviewed. Vapour–liquid–solid method is described in details as the most common techniques to fabricate silicon nanostructures. In addition, a brief discussion on various metals for the role of the catalyst material is provided. This chapter also familiarises the reader with the subject area of flexible electronic flash memory devices. The structure of the flash memory device, the idea behind its development and the basic operating principle are discussed. Silicon nitride is considered, for flexible flash-type memory devices, as an alternative for the dielectric material as it could solve a few of the current memory challenges. Lastly, a brief history and a critique of the current position of the flexible electronic flash memory devices are provided.

2.1 Nanotechnology and Nanomaterials

Nanoscience and nanotechnology are among the greatest emerging scientiﬁc areas in the last 50 years. The development of the next generation of electronics is partly established on the utilisation of nanomaterials. Although the origin of the use of nanomaterials goes back to the ninth century BC where nanoparticles were used as part of the surface treatment for decoration applied on ceramics [1], it is only after the early 1990s that the sophisticated equipment such as atomic force microscope [2] became available to view the nanoworld. This was one of the leading steps in

K. Saranti Á S. Paul (&) Emerging Technologies Research Centre, De Montfort University, The Gateway, Leicester LE1 9BH, UK e-mail: [email protected]

Fig. 2.1 Classification of nanomaterials according to their dimensions the foundations and evolution of nanotechnology. In 1986, Gerd Binnig and Heinrich Rohrer were awarded the Nobel Prize for their design of the scanning tunnelling microscope [3], which gave the fundamentals for the development of atomic force microscopy technique. On 29th December 1959, Richard P. Feynman made a lecture to the American Physical Society titled “There’s Plenty of Room at the Bottom”. Feynman shared his vision about manipulating and controlling things on a small scale. An article was published following that talk and it is believed to have established the pre- liminaries of the history of nanotechnology [4]. In 1974, the term ‘nanotechnology’ was used for the first time by Norio Taniguchi [5]. As a general rule, nanostructures or nanomaterials are definedbyhavingatleast onedimensioninthenanometrescale(from1to100nm).Onemetreisequaltoone thousand million (109) of a nanometre and the prefix “nano” means dwarf in Greek. NASA suggested a more thorough description of the nanotechnology field as follows: “The creation of functional materials, devices and systems through control of matter on the nanometre length scale (1–100 nm), and exploitation of novel phenomena and properties (physical, chemical, biological) at that length scale” [6]. Nanomaterials can be classified according to the number of dimensions that have not been reduced below 100 nm (see Fig. 2.1). • Zero-dimension (0D): The size of the materials is reduced to nanoscale in all three directions. Common examples of this category are the nanoparticles, nanoclusters and nanocrystals. • One-dimension (1D): These nanomaterials have dimensions at nanoscale in two directions. Nanowires, nanotubes, nanofibers and nanorods are included in this category. • Two-dimension (2D): The size of the materials is reduced to nanoscale in one direction. Examples are the nanofilms, nanocoatings and nanosheets. • Three-dimension (3D): Materials with dimensions beyond the nanometre scale in any direction. 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 57

As soon as the novel properties of the nanomaterials were understood, their applications expanded in all the fields of science. The applications of nanoscience and nanotechnology are numerous and extend from the fields of coating, energy sources, environmental, electronics, to health and medical treatments. The commercially available nanomaterials are nanocoatings and nanocomposites, which find use in everyday products such as cosmetics, sunscreens [7], sunglasses [8], sports equipment and self-cleaning windows [9]. Nevertheless, there is still a room for many more potential applications to be discovered.

2.2 Properties of Nanomaterials

Nanomaterials offer signiﬁcant differences in their properties in comparison to their bulk materials. The main two reasons are the high surface area to volume ratio and the small dimensions giving rise to quantum effects. As materials becoming smaller in size, their surface area to volume ratio starts increasing and as a result, the atoms on the surface have a more dominant behaviour than those in the interior of the crystalline lattice core. Hence, the surface atoms have more energy, which makes them more reactive, either chemically or mechanically, in interaction with other materials. This phenomenon is responsible for the catalytic properties of the nanoparticles [10]. Furthermore, the quantum conﬁnement effect is observed for materials at the nanometre scale. The energy levels of materials are arranged in bands (conduction and valence). For insulators and semiconductors these bands are separated by a forbidden region, called bandgap (Eg), in which there is no solution of the Schrödinger’s equation (see Fig. 2.2). The quantum size effects have an impressive correlation between the bandgap and the size of the nanostructure.

Fig. 2.2 The diagram represents the energy bands in metals, semiconductors and energy levels in nanomaterials. For nanomaterials the size quantization effect is shown 58 K. Saranti and S. Paul

Particularly, the bandgap increases as the nanostructure diameter decreases being smaller than its bulk exciton Bohr radius [11, 12]. Moreover, the quantum confinement in semiconductors leads to a ladder of discrete energy levels rather than energy bands [13] as shown in Fig. 2.2. In other words, as the dimensions of the structure become smaller, the energy levels are quantised leading to a spectrum of discrete energies. Although the quantum confinement effect has been established and explored for 0D nanomaterials, the effect has also been confirmed for 1D and 2D nanomaterials. However, different dimensionality of confinement is occurred for each case. In the case of quantum wires, quantum confinement is weakened relative to that in quantum dots [14]. Consequently, by changing the nanocrystals size, the energy gap of this material can be adjusted. This also results in changing the density of electronic energy levels. The density of states (DOS) is the number of available states per unit energy in the band structure (D(E) = dN/dE) and it is a fundamental material’s characteristic that determines many of its properties. Figure 2.3 presents the idealised distribution of states as a function of energy of 3D, 2D, 1D and 0D semiconductor structures [15]. Considering these phenomena, novel optical, magnetic, electrical, and other properties emerge at nanoscale. At this point, only a brief description of a few fundamental paradigms is presented. The effects of quantum confinement predominantly influence the electrical properties, such as electrical conductivity and photoconductivity due to their high dependence on the energy state and DOS. Still, it is broadly reported that the shape can have a dramatic influence on the optical properties of nanostructures [16–18]. Figure 2.4a shows the fluorescence emission of (CdSe)ZnS quantum dots of various sizes. As the size of the dot gets smaller, both the optical absorption and emission of quantum dots shift to higher energies (blue) [17]. This is due to the confinement effect, in which a decrease in size leads to a larger bandgap. Moreover, Fig. 2.4b represents the absorption spectra of various sizes and shapes of gold

Fig. 2.3 Schematic representation of the density of states as a function of energy exhibited in 3D, 2D, 1D and 0D semiconductor structures 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 59

Fig. 2.4 a Fluorescence emission of (CdSe) ZnS quantum dots of various sizes and b absorption spectra of various sizes and shapes of gold nanoparticles. Reproduced with permission from The Royal Society of Chemistry [18] nanoparticles. When gold nanoparticles are enlarged a very similar absorption is observed, while other shapes such as nanorods give a significantly different absorption spectrum [18]. The combination of unique electronic and optical properties offers compelling products such as lasers and light-emitting diodes (LED) using either quantum dots or quantum wires. Nanotubes are widely known for exhibiting superior mechanical properties. The bonding structure of nanotubes is extremely strong, enabling them to be fabricated with unique strength and toughness properties [19]. Bulk modulus of 462–546 GPa have been reported for superhard phase single-walled carbon nanotubes which exceeds even that of diamond (420 GPa for a single diamond crystal) [20]. Thus, nanotubes are ideal for lightweight construction, for example, in automotive and aerospace industries. Apart from using nanotubes as the fundamental materials, another common use is advanced filler materials in composites. Both single and multiwalled nanotubes enable enhancement to material mechanical properties for reinforced polymer fillers their fabrication can be very simple. The nanotubes and the polymer are mixed in a suitable solvent and once the solvent is evaporated a composite film is formed [21]. Hence, filling polymers with nanotubes or nanoparticles lead to improvement in their mechanical properties. The capability of high sensitivity, due to high surface to volume ratio, has led to the development of chemical sensors consisting of single-walled carbon nanotubes [22]. For example, gas sensors based on ZnO nanowires show a very high sensitivity to ethanol gas [23] and nanowire biosensors enable the detection of diseases such as Alzheimer’s or diabetes at an early stage [24]. Moreover, nanomaterial properties have led to improvements in drug delivery systems and cancer therapies, by using better materials to encapsulate and release the drugs [25, 26]. 60 K. Saranti and S. Paul

2.3 Coulomb Blockade and Single-Electron Tunnelling

The combination of quantum tunnelling phenomena (described in Chap. 3) and the Coulomb charging energy gave rise to the function of single-electron transistor (SET) [27, 28]. By exploiting the single-electron charge transfer, electrons can tunnel, one by one, into and out of the nanostructures. This is the most studied nanoparticle-charging phenomenon and is called Coulomb blockade. There is a common electrode termed island (quantum dot), which is connected through tunnel junctions to two electrodes (the source and the drain) and through a capacitor to a gate electrode. Under the application of a constant gate voltage on the island, only one electron can transfer from source to drain via island, enabling the ability to control the transfer of individual electrons. In order to observe single-electron tunnelling phenomena or Coulomb blockade effects, two conditions must be sat- isﬁed. Firstly, the charging energy must exceed the thermal energy (at room temperature E 25.7 meV) as described by Eq. (2.1). Secondly, the Heisenberg uncertainly, stated in Eq. (2.2), sets the lower limit of the tunnel resistance (25. 813 kX).

e2 k T ð2:1Þ 2C B h DE Dt ð2:2Þ 2 where Dt = RC the time to charge/discharge of an island, h is Planck’s constant, e is the electron charge, kB is Boltzmann constant, T is temperature and C is the capacitance given by Eq. (2.3). In the case of the nanoparticle, Eq. (2.3) gives the capacitance in which the nanoparticle is considered as a conducting sphere.

C ¼ 8pe0err ð2:3Þ where e0 is the permittivity of free space, er is the relative permittivity and r is the radius of the sphere. The voltage required to transfer an electron to the nanoparticle is: e V ¼ ð2:4Þ C

The energy (in joules) required to charge the nanoparticle is:

e2 Eð Þ ¼ ð2:5Þ J 2C 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 61

2.4 Current Status of Nanomaterials Used for Memory Storage—The Charge Can Trapped in Their Available Energy States

There is a plethora of applications based on the exceptional characteristics of nanomaterials and wide ranges of ﬁelds have shown to utilise them. In the scope of this chapter, only the recent applications of nanostructured materials for memory based electronic storage devices will be covered. High-density information storage devices using nanomaterials are a fast-developing area, which competes with the conventional silicon-based materials. Memristors (an abbreviation for memory resistor), using titanium dioxide sandwiched with platinum wires, were successfully accomplished at Hewlett Packard’s labs. Leon Chua theoretically predicted the memristor in 1971 as the fourth fundamental circuit element, the other three being resistor, capacitor and inductor [29]. Nevertheless, it was 37 years later the mathematical model and proof of existence was shown. R. Stanley et al. demonstrated that memristance arises naturally in nanoscale systems, by using metal nanowires coated with titanium dioxide and arranging them in crossbar arrays forming a memristor at each inter- section. The device’s resistances change over time as a function of their existing state [30]. Recently, Chua also argued that all two-terminal non-volatile memory devices based on resistance switching phenomena are memristors, in spite of their material or physical mechanism [31]. It is believed that the development of high memory density memristors could lead to the substitution of the commonly used dynamic random-access memory (DRAM). Commercial availability of the memristor is estimated for 2018 [32]. It is widely known that magnetic materials have been efﬁciently used through the years as digital data storage. The evolution of nanomaterials and the need for miniaturisation of the memory storage units in the electronic devices led to the exploitation of magnetic nanomaterials. IBM researchers developed a new type of magnetic memory called racetrack memory in which magnetic nanowires made of an alloy of iron and nickel are utilised [33]. Racetrack memory store bits of data in the form of magnetised regions or domain in nanowires on silicon substrate. The nanowires can be arranged horizontally or vertically on the silicon chip. The racetrack memory is based on the ability to use an electric current to move magnetic domains along the nanowire and can read the bits as they go past the reading element [34]. As in all magnetic memories, magnetism plays the key role in the physical operating mechanism. A working prototype with all the necessary components on the single chip was presented at the International Electronic Devices Meeting in Washington, in December 2011 [35]. Researchers at Rice University demonstrated that resistive switches and memories could be built solely from silicon dioxide. A two-terminal resistive switch with 5 nm diameter silicon dioxide nanowires sandwiched between semiconducting sheets of polycrystalline silicon for top and bottom electrodes were studied to create memory devices by changing the resistance of the nanowire at that location. Silicon dioxide is 62 K. Saranti and S. Paul proven to be the source for the formation of silicon nanocrystals, which can be switched between conductive and non-conductive state without damaging material’s properties [36]. The simplicity of the structure, the greater compatibility (fully CMOS compatible) and 3D capability are very promising characteristics for the production of high-density memories using this approach. Moreover, only a few years later, a highly transparent memory with indium tin oxide or graphene as the electrodes and silicon dioxide as the active material was fabricated by the same research group [37]. Another approach is to store information on magnetic nanoparticles called nanodots or nanoscale magnets. Each grain is individually magnetised in its own direction and the working principle is based on switching their magnet states and reading them [38]. Research is undergoing into reducing these structures to their nanoscale size limit in which they can retain their magnetism and in consequence the memory effect. To accomplish this, highly orientated nickel magnetic nanoparticles have been studied [39]. The structures are self-assembled giving the advantage of precise arrangement with minimum energy consumption and maximum stability production. Bits are stored by controlling the orientation of each nanodot composed of magnetic nickel alloy. Developing the technique they are claiming a terabit of data could be stored on a chip of area 6 Â 6mm[40]. A nanoparticle encapsulated within a multiwall carbon nanotube has been observed to function as an electromechanical memory device. In particular, an iron nanoparticle inside a carbon nanotube can be controllably positioned and creates the binary states 0 or 1. Researchers believe that via an electrical write signal, the shuttle can move reversibly and have a thermodynamic stability that can exceed one billion years [41].

2.5 Synthesis of Silicon Nanowires

Silicon nanowires are 1D nanostructures and their use has already been established in different applications such as sensors [24], high-performance field effect transistors [42], solar cells [43] and memory devices [44]. There are many different methods to fabricate silicon nanomaterials. In general, they can be categorised into two main groups: the bottom-up approaches (i.e. laser ablation, chemical vapour deposition and thermal evaporation) and the top-down approaches (i.e. nanolithography, chemical and reactive-ion etching). In the former method, by the effective combination of the fundamental blocks the desired characteristics are achieved providing a great advantage of potential self-assembly ability and no need for patterning. In the latter case, the additional material is removed forming the final device or structure. Although nanolithography techniques can design well-patterned areas, resulting in well-oriented nanostructures, they are limited due to high cost and low yield. To the best of the author’s knowledge, Treuting and Arnord have published the first paper on silicon wire growth in 1957 [45]. At that time, the term whisker was used. Seven years later Wagner and Ellis presented the well-known vapour–liquid– 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 63 solid (VLS) growth mechanism of silicon whiskers [46], which was a stepping-stone for progress in the research field of the synthesis of silicon nanostructures. VLS is the most common growth mechanism applied to synthesise variety of nanomaterials through chemical vapour deposition (CVD), thermal evaporation oxide-assisted growth (OAG), laser ablation, solution-phase synthesis and molecular beam epitaxy (MBE) [47] techniques. It is worth mentioning that each technique has advantages and disadvantages. However, depending on the required application each technique can be applied effectively. The amazing feature of the VLS mechanism is that it works well over a range of material sizes from hundreds of micrometres to a few nanometres. For the CVD process the precursor gas used is usually silane (SiH4) or silicon tetrachloride (SiCl4). It is a bottom-up synthesis method that allows the epitaxial growth of the silicon nanostructures. The use of metal seeds as catalyst material is essential and the main constraint of the mechanism, because contamination is possible due to metal diffusion into the grown structures, which can affect the nanostructures’ properties. With the appropriate choice of catalyst and deposition conditions, well-defined nanomaterials can be grown. For lower substrate temperatures and wider range of metal catalysts, plasma-enhanced chemical vapour deposition (PECVD) method is used. The temperature for the CVD process ranges from 500 to 800 °C setting a limit for the use of temperature-sensitive substrates as well as several metal catalysts. The plasma-enhanced CVD process provides high ion energy allowing the creation of reactive gas species at lower temperatures ranging from 100 to 300 °C. Hence, if a low-temperature synthesis is required the PECVD method is preferred.

2.5.1 Vapour–Liquid–Solid Growth Mechanism

As stated previously, Wagner and Ellis described the formation of single crystal silicon whiskers by VLS mechanism in 1964. This was the leading step for the future of the synthesis of silicon nanowires. The observed structures were silicon crystal whiskers with liquid droplets at the tip. Gold (Au) was used as the catalyst material and a mixture of SiCl4 and H2 for the process [46]. Until today, these factors (Au, SiCl4 and H2) are the most favourable for the VLS growth of nanomaterials. The part of the metal seed as catalyst is essential for the VLS growth. Initially the substrate was heated up. The vapour Si (available from the source gas SiCL4) was decomposed on the surface and diffused into the metal. Therefore, a liquid Si–metal alloy was formed and once it became supersaturated the nanowire growth started. As the name states there are three phases involved in this process; vapour, liquid and solid. These three phases can be fully understood by a phase diagram. Since Au metal was ﬁrst exploited and still is used for many applications the Au–Si (gold–silicon) phase diagram is used as an example here to explain the VLS growth mechanism. With a simple eutectic phase diagram as shown in Fig. 2.5 64 K. Saranti and S. Paul

Fig. 2.5 Binary phase diagram of a Au–Si system and schematic illustrations of the VLS growth mechanism involved at the states of the binary system the state of the mixture of two elements (Au and Si) can be described as a function of temperature and composition. A eutectic phase diagram usually results when the melting point of the two components is not vastly different and the solid solubility is limited. The alloy formed by the two elements is liquid above and along the liquidus lines and solid below the solidus line [48]. For all the other regions, there is a coexistence of two phases, liquid and solid, with a certain composition and temperature. The liquidus line gives the composition of the liquid alloy as a function of temperature. The lowest melting point of the Au–Si alloy has a eutectic point (T = 370 °C) where Au is 83 at. % and Si 17 at. % [49]. Ideally, for the nanowire synthesis, we are moving along the green arrow in Fig. 2.5. Initially, the metal catalyst is at the solid phase (if the process temperature is below its melting point). (i) Precursor gas transports to the catalyst particle. (ii) The surface of the metal catalyst cracks by the precursor gas and silicon atoms are diffused into the droplet forming an alloy of Au–Si, however solid Au is also still present. (iii) While moving along the line, the Si concentration is increased up to a point where the entire droplet is a liquid Au–Si alloy and supersaturation is reached. (iv) After supersaturating, the element (Si) precipitates in a solid phase and the nanowire growth starts. The binary phase diagram of the two elements describes this process very clearly. Typically, the nanowire growth by the VLS mechanism occurs as long as the temperature is above the eutectic point. Theoretically, the growth of the nanowires will suspend if there is no source material and/or the catalyst material is not efﬁcient.

2.5.2 Choice of Catalyst Material for Silicon Nanowires Growth

For the VLS growth method the most critical part is the choice of the metal catalyst. Since the use of a catalyst is essential for the process, the best candidate to each 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 65 particular application is extremely important and should be carefully chosen. The quality and morphology of the obtained nanostructures depend on the catalyst material properties as well as the growth conditions. Up to now, silicon nanowires have been successfully grown by several catalyst materials including Al [50–52], Ag [46, 53, 54], Ni [46, 50, 53, 54], Cd, Bi, Fe, In [52, 55], Zn [50], Pd [46, 54], Ga [55], Au [46, 50, 53–57], Cu [46, 50, 53, 54] and Pt [46, 50, 53]. Starting from the Wagner and Ellis publication [46], the nanomaterials grown by Au metal are undoubtedly the most reviewed mainly because of the high chemical stability of Au, its non-toxicity and availability [47]. Moreover, another important parameter is the Au–Si low eutectic point (370 °C). Nevertheless, the impurity levels of Au are close to the middle of the silicon bandgap (see Fig. 2.6) causing degradation of the optical and electrical properties of the silicon nanowires and as a result malfunction of the devices [58]. Hence, a lot of effort is focused on the synthesis of Au-free catalysed silicon nanowires. The main factors for choosing the catalyst material aiming to synthesise silicon nanowires are the eutectic point of the metal–Si alloy, the substrate temperature, the melting point of the metal as well as the impurity levels of the catalyst in the Si bandgap. In Fig. 2.7 the impurity levels of various metal catalysts as a function of the minimum temperature required for the VLS silicon wire growth are presented. The levels are shown in respect to the centre of the Si bandgap, which has the value of 1.12 eV. Above the midgap, the solid symbols mark the donor levels while the open symbols the acceptor levels. Correspondingly, below the midgap the solid symbols mark the acceptor levels and the open symbols the donor levels [47]. The metals with impurity level energies close to the conduction or valence band will cause doping. In particular, Ga, Al and In have acceptor levels close to the valence band will cause p-type doping. Similarly, Li, Sb, Te and Bi can cause n-type doping. The materials that are close to middle of the bandgap such as Au, Zn, Cu, Fe, Cr, Pd or Co should not be the ﬁrst choice if deep impurity levels are not desired [59]. However, for charge storage deep level energy states can be ideal candidates for a long retention. The drawback of using Al metal is its high oxygen sensitivity. Cd has a relatively high vapour pressure, which means the metal may also evaporate during the growth process rather than having a catalytic effect on the growth. In that case, even a few atoms can compromise the performance of the device. Ga is also unfavourable because it has a very low melting and eutectic point (30 °C) [60]. It melts and tends to migrate on the sample’s surface, making the size and position control of the catalyst very difﬁcult [61]. Ag has a high eutectic

Fig. 2.6 The energy levels introduced by Au in Si bandgap 66 K. Saranti and S. Paul

Fig. 2.7 The impurity levels of various metal catalysts as a function of the minimum temperature required for VLS silicon wire growth. Silicon bandgap has the value of 1.12 eV and the levels are shown in respect to the centre of the bandgap [47]. The impurity states can also be exploited in charge storage memory temperature (845 °C); therefore it is not compatible with temperature-sensitive substrates and low-temperature processes [62]. Hence, Sn, Pt, Ni, Pd and Tl could be possible options of catalyst material for silicon nanostructures growth via VLS mechanism if high doping are to be avoided [47, 59].

2.5.3 In and Sn Catalyst Materials for Silicon Nanowires Growth

For the purpose of this chapter, a review of the synthesis of silicon nanowires (SiNWs) using In and Sn catalyst material was conducted. In and Sn are very promising candidates as catalysts for the VLS growth of silicon nanostructures, especially at low temperatures. Moreover, the different fabrication methods in which In and Sn were used to synthesise SiNWs are presented. Although many researchers have attempted to synthesise SiNWs using In and Sn, there are only a few papers demonstrating a successful growth. These will be discussed below. In and Sn metals share many common characteristics such as similar binary phase diagrams. They both form a single eutectic point with nearly zero concentration of silicon and without any silicide phases. In–Si eutectic temperature (156.63 °C) is almost indistinguishable from In melting point (156 °C) [63]. 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 67

Similarly, Sn–Si eutectic point (231.9 °C) is almost the same as Sn melting point (231.93 °C) [64]. The low eutectic point is one of the main features of these materials that enable the formation of silicon nanostructures at very low temperatures. In addition, the low silicon solubility and silicon concentration at the eutectic temperature are the main parameters of the liquid alloy droplet that can determine the nucleus size for the silicon growth and crystallisation. Although much research has been conducted for SiNWs growth using alternative metal catalysts, only a very few preliminary studies have been reported for In- and Sn-catalysed synthesis. These are presented in Tables 2.1 and 2.2 giving respectively their corresponding literature references. Different methods to fabricate SiNWs by In-seeded process have been reported such as PECVD [65–67], high boiling point organic solvent [68], hydrogen radical assisted [69], electron beam evaporation [70] and in-plane solid-liquid-solid [71]. As shown in Table 2.1, thermally evaporated In layer, indium tin oxide (ITO) substrate, indium oxide

Table 2.1 In-catalysed SiNWs synthesised with different methods In catalyst layer Synthesis process Silicon nanowires Ref. growth details year

Thermally H2 plasma treatment for catalyst droplet Self-aligned, in-plane [66] evaporated In formation, PECVD process for SiNWs on Si 2014 pads deposition of a-Si:H layer and annealing (100) wafers in H2 ambient at 550 °C for 1 h Thermally High boiling point organic solvent as the SiNWs 1–5 lm length [68] evaporated In growth medium and around 42 nm 2012 diameter

ITO layer H2 plasma treatment for catalyst droplet SiNWs 1.8 lm length [67] formation, VLS mechanism by PECVD and 30 nm diameter 2012 at 500 °C Thermally Electron beam evaporation at 300 °C SiNWs with 600 nm [70] evaporated In length 2012

Electron beam H2 plasma treatment for catalyst droplet SiNWs with 150 nm [65] deposition of In formation, VLS mechanism by PECVD length from 5 nm In 2010 at 500–600 °C layer

ITO substrate H2 plasma treatment for catalyst droplet Lateral growth [71] formation, in-plane solid-liquid-solid 2009 (IPSLS) at 350–500 °C

In2O3 H2 plasma treatment for catalyst droplet SiNWs with 1 lm [72, formation, VLS mechanism by length 73] microwave plasma-assisted CVD 2008 (MPCVD) at 200–400 °C

In2O3 Hydrogen radical-assisted method at SiNWs with up to [69] 400 °C 10 lm length and 10– 2008 150 nm diameter

Electrodeposited H2 plasma treatment for catalyst droplet SiNWs with around [52] In nanoparticles formation, VLS mechanism by PECVD 30 nm diameter 2007 at 500–600 °C 68 K. Saranti and S. Paul

(In2O3) layer and electron beam deposition of In are some of the routes to obtain the initial In layer. Afterwards, in most cases, H2 plasma treatment is used to form the catalyst droplets that will initiate the VLS growth. Synthesis of Sn-catalysed SiNWs has been achieved with the methods presented in Table 2.2; among them are PECVD [74–77], supercritical ﬂuid–liquid–solid (SFLS) [78], electron beam evaporation [79], hydrogen radical assisted [80, 81] and recently magnetron sputtering [82] method. Respectively, tin dioxide (SnO2)

Table 2.2 Sn-catalysed SiNWs synthesised with different methods Sn catalyst Synthesis process Silicon nanowires growth Ref. layer details year Magnetron Magnetron sputtering at 250–400 ° SiNWs with 10–40 lm [82] sputtering C length 2015 of Sn Thermally Hot wire chemical vapour SiNWs with 3.5 lm [85] evaporated processing (HWCVP) at 300– length and 350 nm 2013 Sn 400 °C diameter Thermally Electron beam evaporation at 300– SiNWs with 500 nm [79] evaporated 350 °C length 2013 Sn Thermally High boiling point organic solvent SiNWs with 70 nm [84] evaporated as the growth medium diameter 2013 Sn Thermally Catalytic thermal CVD at 500 °C Crystalline amorphous [86] evaporated core-shell structure 2012 Sn

Thermally H2 plasma treatment for catalyst SiNWs with 1–3 lm [83, 87] evaporated droplet formation, VLS length 2012 Sn mechanism by PECVD at 600 °C Electron Electron cyclotron resonance SiNWs with up to 1 lm [88] beam chemical vapour deposition length and 200 nm 2012 deposition (ECRCVD) at 380 °C diameter of Sn Sn Supercritical ﬂuid-liquid-solid SiNWs with 10–100 lm [78] (HMDS)2 (SFLS) length 2012

Thermally H2 plasma treatment for catalyst Crystalline core of 10 nm [77] evaporated droplet formation, VLS diameter and 2011 Sn mechanism by PECVD at 300– polycrystalline shell 400 °C 60 nm thick Thermally Hydrogen radical-assisted method SiNWs with up to 2 lm [80, 81] evaporated at 400 °C length and 50–200 nm 2009 Sn diameter

SnO2 H2 plasma treatment for catalyst Length growth rate of [74–76] substrate droplet formation, VLS 1nms-1 2008, mechanism by PECVD at 300– 2010– 600 °C 2011 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 69 substrates, Sn(HMDS)2 and evaporated Sn layer were required to produce the Sn catalyst droplets with the assistance of H2 plasma treatment. From the literature, it is evident that In- and Sn-catalysed SiNWs can be fabricated by the same manner [61]. Moreover, the annealing with the hydrogen plasma is the key aspect of the successful synthesis [65]. H2 plasma treatment has two beneﬁts; it (i) assists in the formation of catalyst in nanodroplets sizes and (ii) can hinder the oxidation of the catalyst layer enabling their catalytic activity. One of the main differences between the In- and Sn-catalysed SiNWs is the impurity levels. Sn does not form any deep centres in the silicon bandgap while in the case of SiNWs obtained by the In catalyst the impurity levels can cause n-type doping (see Fig. 2.7). Hence, based on the aforementioned literature review, Sn could be the best candidate for synthesising undoped SiNWs at low temperature. The alternative to Au metal-seeded synthesis of silicon nanostructures is very new and only a few applications utilising these structures have been reported. So far, Sn-catalysed SiNWs have been used for solar cell applications showing efﬁ- ciency as high as 4.9% [83]. Furthermore, the electrochemical performance of In- and Sn-catalysed SiNWs has been studied for testing the suitability of the obtained nanowires as anode material for Li ion batteries and Sn-catalysed SiNWs have been demonstrated to exhibit capacities greater than 1000 mAh g−1 after 50 charge/discharge cycles [68, 84]. To the best of the author’s knowledge, neither In- nor Sn-catalysed SiNWs have been utilised as the storage element of any electronic memory devices.

2.6 Flexible Electronic Flash Memory Devices

2.6.1 Introduction to Flash Memory Technology

In the last two decades, electronic flash memory technology has taken on a starring role in the semiconductor industry. Electronic memory is used in the majority of everyday electronic devices such as mobile phones, tablets, personal computers, digital cameras, global positioning system and other equipment. The size of all these devices has been shrunk enormously over the years [89, 90]. This progress is partly in accordance with Moore’s law. In 1965 Gordon Moore wrote a paper entitled “Cramming more components onto integrated circuits” in which he noted that “the complexity for minimum component costs has increased at a rate of roughly a factor of two per year”. His estimation has been verified through the years and it is widely known as Moore’s law [91]. Specifically, in 1971 there were chips with 2,300 transistors while in 2006 the number increased to 300 million transistors [92]. However, a similar exponential growth has not been noted during the last 70 K. Saranti and S. Paul couple of years, compelling researchers to examine alternative approaches to address the limits of further scaling down. Recently, the International Technology Roadmap for Semiconductors (ITRS) community released an article named “More-than-Moore White Paper” in which it is pointed out that for further miniaturisation a different approach might be required. In particular, the conditions that made “More Moore” possible were analysed and then the new “More-than-Moore” (MtM) trend was identified and examined as the new feasible and desirable approach [93]. Figure 2.8 shows the ideas for beyond complementary metal-oxide-semiconductor (CMOS) technology presented by the ITRS community. Up to now, it has been accepted [94, 95] that memories are chosen based on the application they are to be utilised for. A new approach to scale the memory cell size down without compromising its performance is of great importance. The flash memory market is currently following two paths: (i) evolutionary path, which involves a continuous improvement of the current products and technologies and (ii) disruptive path, where entire new storage mechanisms and technologies are offered. The former path is mostly followed in which silicon nanocrystals

Fig. 2.8 Generic representation of trends beyond the common CMOS technology, like “More Moore” for miniaturisation and “More-than-Moore” for functional diversiﬁcation approaches that were identiﬁed and presented by the ITRS community [93] 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 71

Fig. 2.9 The basic CMOS electronic memory categories memories, high dielectric constant (high-k) materials and fin flash memories were established [96]. CMOS memories can be categorised into two major categories: the volatile memories and the non-volatile memories. In the case of the volatile memories, the information is lost when the power is turned off, and in non-volatile, the information is retained even when the power is switched off. Figure 2.9 shows many types of semiconductor memories and flash memory that fall into the class of non-volatile types. The non-volatile flash memory market contains the NAND and NOR technologies. The NAND flash memory cell is fundamentally the same as the NOR flash memory cell. The difference is in the array organisation and the operation principle. The NAND flash memory utilises the Fowler–Nordheim tunnelling (described in Sect. 3.3.1.) for programming operation while the NOR flash memory uses the channel-hot-electron injection process (described in Sect. 3.3.2.). Both NAND and NOR flash memory cells are erased by the Fowler–Nordheim tunnelling process [97]. The advantage of the NAND over the NOR flash memory cell is the higher density of cells in the former and hence a higher capacity data storage as well as faster write and erase operations. Moreover, the NOR memory cells is almost double the size of the NAND flash cell and therefore more expensive [98]. Flash memory devices are the future for any type of portable application since they are non-volatile. However, they are slow and usually a combination of more than one type of memory is required in order to create a mobile device [95, 96]. Among the non-volatile memories, flash has been proved to be the most suitable one for portable applications, the main reasons are: • Flash memory has a very simple structure requiring only one transistor, thus making it easier to achieve the highest chip density in comparison to other non-volatile memories [98]. • Compatibility with the current CMOS technologies. The materials and the fabrication process of the flash memory are compatible with conventional CMOS processes [96]. 72 K. Saranti and S. Paul

• They can be programmed and erased many times (more than 100,000 times) while at the same time they offer the smallest cell size [98]. • Flash memories support the multi-bit per cell storage property. Two-bits per cell has already been established, whereas the four-bits per cell was recently commercialised by Spansion MirrorBit Quad Technology [99]. Nevertheless, electronic flash memories do have drawbacks. They require high programming and erasing voltages and their program/erase speed is slow in contrast to the rest of the non-volatile memories. CMOS floating gate is the dominant architecture for the flash memory devices. For NOR and NAND architecture further scaling looks impossible [96, 100]. There are many challenges, such as the scaling of the tunnelling dielectric layer thickness. The tunnelling dielectric layer (usually an oxide) should be thin to allow the charges to tunnel through (for the programming and erasing processes) but, at the same time, must be thick enough to ensure data retention by preventing charge tunnelling [97]. Defects in the oxide may cause failure of the device and are among the most important factor that cause reliability concerns, which can lead to high operating voltages and high leakage currents. Another issue is the limit of the channel length. A minimum channel length has to be maintained, which impedes the further scaling of the cell. A technological challenge is additionally faced when lithography is used, as there is a minimum feature size depending on the wavelength of the light source. Finally, another difficulty in the continuous scaling down is the high process temperatures and the high thermal energy generated. Due to the reduction of the dimensions, higher operating voltages are required [96] that can cause undesirable device behaviour. The total amount of energy during a process termed ‘thermal budget’ should be as low as possible. A short time process (a few seconds) can fulfil this requirement since the total energy is temperature-time dependent. In order to overcome these difficulties, new materials and device architectures are being explored. For example, charge-trapping devices, such as silicon-oxide- nitride-oxide-silicon (SONOS), were presented as a potential solution. SONOS devices have a simpler structure than the flash memory devices due to exploiting the intrinsic defects of the silicon nitride that can trap charges [97]. Another suggestion is the use of metal or silicon nanocrystals for the floating gate that was first introduced in 1995 by Tiwari [101]. High-k materials are mainly considered for the dielectric layer because a material with higher dielectric constant (k) can be physically thicker (reduces the leakage current) while having the potential to increase the gate capacitance and therefore improve the device performance [102]. Three-dimensional (3D) approach hopes to solve the obstacle of the minimum value of the channel length. It offers the prospect of a multilevel cell where the memory arrays are vertically stacked [96]. On the other hand, totally new storage mechanisms are studied, such as the ferroelectric and phase change memories [103, 104]. However, the cost of these is higher than of the flash memory and there are still several doubts about their reliability. 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 73

2.7 Flash Memory Structure

The basic flash memory cell consists of one transistor combined with a floating gate. In particular, it is a conventional metal-oxide-semiconductor field-effect- transistor (MOSFET), as can be seen in Fig. 2.10a, with an extra gate between the tunnel and the control (or gate) oxide, named the floating gate. The floating gate is the memory storage component and it is isolated between the insulator layers in order to trap charges. By adding the floating gate, the device properties change and result in a flash memory cell. In the literature, sometimes referred to as a floating gate based memory or three terminal memory cell, because the memory cell has three terminals: a source, a drain and a gate [98, 100, 105]. As part of this work, the structure shown in Fig. 2.10b was revised to meet the requirements of a flexible flash memory cell. It is however very similar to the basic flash memory cell structure and holds the same operating principle. Yet, for enabling the utilisation of the flexible substrate, the rigid silicon substrate was replaced. A suitable architecture is shown in Fig. 2.11. The structure is an inverted conventional flash cell and a high-quality semiconductor layer is used for the transistor area.

Fig. 2.10 Schematic illustration of a the conventional MOSFET structure and b the ﬂoating gate transistor or ﬂash memory cell

Fig. 2.11 Schematic illustration of a ﬂexible ﬂash memory cell structure 74 K. Saranti and S. Paul

2.8 Working Mechanisms of the Flash Memory Cell

As previously mentioned, the two main mechanisms for programing and erasing a flash memory cell are the channel-hot-electron injection and the Fowler–Nordheim tunnelling. Both mechanisms trap electrons inside the floating gate, whereas the latter removes the electrons from the gate by tunnelling processes. Trapped electrons shift the threshold voltage of the cell. This shift can be observed during the read process between the source and drain. By defining two different states (for shifted and non-shifted threshold voltage) we are able to store one bit of information (1 or 0) inside the cell. In order to explain the working mechanism of the flash memory, the quantum tunnelling phenomena and the probability of an electron to tunnel through a barrier is discussed. Quantum tunnelling is a phenomenon that can happen through a thin potential barrier and cannot be explained by classical physics. For a finite potential barrier of height V0, width L and for particles with kinetic energy smaller than the barrier height (E < V0), there is a small non-zero probability of particles tunnelling through the barrier. In that case, the time-independent Schrödinger equation for a particle moving in one dimension is the following:

h2 #2WðxÞ À ¼ðE À V ÞWðxÞð2:6Þ 2m #x2 0 where h is Planck constant divided by 2p, m is the mass of the particle and W is the wave function of the system. Moreover, the transmission probability or the transmission coefﬁcient for the potential barrier is

4k2c2 T \ ðEÞ¼ ð2:7Þ E V0 2 2ðc Þþ 2c2 V0 sin h L 4k qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 where k ¼ 2mðE À V0Þ=h and c ¼ 2mðV0 À EÞ=h For a barrier with a very large width (L ) and a barrier height greater than the energy of the particle (V0 E), the hyperbolic sin hðcLÞ term can be simplified to ffi 1 ðc Þ 2 exp L . In this case, (2.7) gives the following approximation: E E TðEÞffi16 1 À expðÀ2cLÞexpðÀ2cLÞð2:8Þ V0 V 0

Therefore, the probability of a particle tunnelling through the barrier depends exponentially on the thickness of the barrier L, the energy difference (V0 À E) and the mass of the particle (2.8)[106, 107]. 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 75

2.8.1 Fowler–Nordheim Tunnelling

It has been established that the charging and discharging of the floating gate of the flash memory devices happens through the tunnelling phenomena. The potential barrier of each device segment is shown in Fig. 2.12 to explain the working mechanism. Initially, there is no applied voltage and all the energy levels are flat (Fig. 2.12a). Once voltage is applied, the energy levels shift. In the case of a high-applied electric field, the conduction band of the tunnel oxide is triangular in nature (Fig. 2.12b, c) and the Fowler–Nordheim tunnelling occurs [108]. The magnitude of the applied voltage is very critical since the higher the gate voltage the greater the probability of tunnelling. At higher electric fields, the potential becomes steeper and the energy barrier width reduces. Wentzel–Kramers–Brillouin (WKB) [28], the approximation is the most adopted approach for calculating the transmission coefficient of variable potential barriers

Fig. 2.12 Energy band diagrams showing the potential barrier of a each section of the flash memory, b the Fowler–Nordheim tunnelling/programming process and c the Fowler–Nordheim for the erase process 76 K. Saranti and S. Paul for the time-independent one-dimensional Schrödinger equation. For E < V0, the tunnelling region, the triangular shaped barrier has a potential of V ¼ EF þ U À eEx, EF is the Fermi energy and the tunnel probability is given by (2.9). pffiffiffiffiffiffiffiffi 4 2mÃ U3=2 T ¼ exp À ð2:9Þ 3 h eE where E is the applied electric field, m* is the effective mass of the electron and U is the injection barrier height at the interface. The electron barrier at the Si/SiO2 interface is about 3.15 eV and is higher than that of the silicon nitride (2.1 eV) [89] which means that a higher applied voltage is required in order to program the memory cell, when using the silicon oxide as a tunnelling layer. Moreover, the Fowler-Nordheim tunnel current density is given by (2.10)[109, 110]. b J ¼ C E2exp À ð2:10Þ FN FN E pffiffiffiffiffiffi ¼ q3m b ¼ 4 2mÃU3=2 where CFN 8phUmÃ, 3hq , h is Planck constant, m is the mass of a free electron, q is the charge of single electron, m* is the effective mass of the electron and U is the injection barrier height of the interface. Hence the current density JFN is exponential dependent on the applied field. Usually a plot of ln(J/E2) versus 1/ E is plotted which should yield a straight line [111, 112].

2.8.2 Channel-Hot-Electron Injection Process

During programming a NOR flash memory cell, channel-hot-electron injection process occurs. Energy higher than the energy barrier (for example 3.15 eV for silicon oxide tunnel layer) is required for an electron to surmount the tunnel oxide barrier and be injected into the floating gate. Under positive drain bias, the lateral channel electric field given by the source-drain potential VDS, accelerates the electrons from the source to the drain side and are said to become ‘hot’ (have high kinetic energy). Those electrons can ‘jump’ from the channel region into the gate. However, only a few hot electrons can successfully gain sufficient energy to overcome the energy barrier and be injected into the floating gate [98, 100]. In general, the channel-hot-electron injection process takes place when the electrons have energy higher than the potential barrier in order to be injected into the floating gate. A schematic illustration is shown in Fig. 2.13. This process is not preferable because the ‘hot’ electrons have a high impact on the reliability performance of the device and can cause degradation of the cell [113]. 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 77

Fig. 2.13 A schematic illustration using the energy band diagrams of a ﬂash memory device to describe the channel-hot-electron process

2.8.3 Reading Operation

The presence of charges in the floating gate give rise to a threshold voltage shift which is monitored as shown in Fig. 2.14. For charging the floating gate, it is necessary to apply an outer gate voltage. For discharging the floating gate, an opposite in polarity but equal in magnitude to the charging voltage should be applied. The stored information in the floating gate is recalled from the cell during the read process.

Fig. 2.14 The behaviour of a ﬂash memory device during the reading process. The threshold voltage shift and the formation of the two states (charged or programmed state with bit value = 0 and uncharged or erased state with bit value = 1) are demonstrated based on the I–V characteristics 78 K. Saranti and S. Paul

When charges are stored, a conductive channel is formed, the channel current is ON and a shift in I–V characteristics of the device is observed, known as memory window. The two states are illustrated in Fig. 2.14; the programmed state with a bit value of zero and the erased state with a bit value of one. During the reading process, the states can be identiﬁed using the I–V characteristics of the device. For example, for reading a bit, a read voltage (VR) on the control gate is applied and the drain current (ID)ofthe ﬂoating gate transistor is measured. In the case shown in Fig. 2.14, at the voltage (VR), the read current shows a positive value, indicating state ‘1’.Whenstate‘0’ is formed, the drain current value is zero for the same voltage VR [98].

2.9 Choice of the Dielectric Material: Silicon Nitride

One of the main limitations for the continuous reduction of the flash memory cell dimensions is the thickness of the tunnel oxide layer. The role of the tunnel oxide is to allow the charge to transfer to and from the floating gate quickly under the influence of an electric field (see section Fowler–Nordheim tunnelling). A low electric field is preferred in order to have a low power operation and minimum undesirable effects for the rest of the memory cell. At the same time, the tunnel oxide needs to play its role as an insulator. During the read operation, the charges should not leak out fulfilling the requirement for at least 10 years retention time [98]. Moreover, the stressing effect on the layer that occurs due to the repeatedly write/erase operations will introduce defects—oxide traps in the layer. Silicon oxide is widely used because it is easy to fabricate and forms a good interface with silicon. The silicon oxide thickness currently used, satisfactory for the tunnelling process is 7–9 nm, and it has not been possible to reduce it further. A thicker dielectric layer with higher dielectric constant is possible to replace the thin silicon oxide. Hence, alternative materials are considered. Silicon nitride is used in a wide range of applications such as thin film transistors, oxidation masks and solar cells. Its most common utilisation is in the CMOS industry as a dielectric layer for electrical isolation, mainly due to its mechanical properties and chemical inertness [114]. Silicon nitride films can be produced by different deposition methods such as CVD, PECVD and reactive sputtering. However, they are generally deposited at high temperatures (700–800 °C) by both high-temperature chemical vapour deposition (HT-CVD) techniques and low-pressure chemical vapour deposition (LPCVD), which provides highly stoichiometric films with very low hydrogen content [115, 116]. The main benefits for using silicon nitride films for flexible memory are: • High-quality silicon nitride layers can be fabricated at low temperatures (200– 400 °C) by PECVD. In general, for plastic and flexible substrates, the fabrication temperature must not exceed 350 °C. For such applications, the PECVD is highly suitable, although films tend to be non-stoichiometric and contain appreciable amounts of hydrogen [116]. 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 79

• Silicon nitride ﬁlms can be fabricated with commercialised processes. Apart from compatibility issues, their chemical stability at high temperature processes is also very advantageous [117]. • Due to its high dielectric constant, a thicker layer is possible (fulﬁlling the requirement for 10 years retention time). The (electrical) equivalent oxide thickness (EOT) is an important parameter that indicates the essential thickness of the silicon oxide in order to have the same effect as with the high-k material being used and is calculated by (2.11)[118].

kSiO2 EOT ¼ thighÀk ð2:11Þ khighÀk

• where, kSiO2 is the dielectric permittivity or dielectric constant of the silicon oxide (3.9), khigh-k is the dielectric permittivity of the high-k material and thigh-k is the physical thickness of the high-k material. Hence, approximately 15.4 nm of silicon nitride layer (ksilicon nitride = 7.5) would produce the same effect as 8 nm of silicon oxide layer. • Silicon nitride is also preferred due to its lower injection barrier (2.1 eV) in comparison to silicon oxide (3.15 eV) for the tunnelling process [89]. This will enhance the programming speed (in the case of the thin layer) as well as the retention time (in the case of the thick layer). The only major drawback of using silicon nitride is that it can trap charges. However, the controlled deposition process and optimisation of the deposition conditions can offer a very low charge trapped density. Another challenge is the fabrication at low temperature. Deposition of silicon nitride dielectric ﬁlms at low temperatures is more likely to produce high concentrations of hydrogen in the ﬁlms, which lead to poor electrical properties and an increase in porosity of the material that results in oxidation over time [102].

2.10 A Brief History of Flexible Flash Memory Devices

It has been almost 50 years since the first floating gate memory device was presented using an insulated gate field effect transistor in 1967 by D. Kahng and Sze [119]. A simple sandwich structure of metal (1)/insulator (1)/metal (2)/insulator (2)/metal (3) was demonstrated effectively as a memory device with the metal (2) being the isolated floating gate component. More than a decade later, in the 1980s, Masuoka working for Toshiba made a breakthrough by inventing the flash memory [120]. Following that, it took only a couple of years for the first flashchipmemorytobecome commercially available from Intel. Since then, fast evolution has taken place, with flash memory being the dominant memory for portable applications and with memory devices on flexible substrate paving a path for new futuristic products. 80 K. Saranti and S. Paul

Until now, the demand for flash memory devices has been growing rapidly. Since the flash memory device is effectively a transistor with an additional isolated floating gate, these two parts have been evolving aiming to accomplish a fully flexible memory cell. Many types of transistors were fabricated before the memory idea came into function. The dominant materials for thin film transistors (TFTs) are the hydrogenated amorphous silicon (a-Si:H), the polycrystalline silicon (poly-Si) and the organic semiconductors [121]. All these materials have been used in flash memory devices and up to now only organic semiconductors have shown a great potential for the application with flexible substrates. It is well known that the high-performance transistors (high mobility and chemical stability) are the poly-Si transistors. However, the methods to obtain flash memories with poly-Si transistors are utilising high temperatures such as solid-phase crystallisation (SPC), excimer laser annealing (ELA) and sequential lateral solidification (SLS) [122–124]. In order to overcome this difficulty, low-temperature poly-Si thin film transistors (LTPS TFTs) [125] have gained great interest and they are excellent candidates for low-temperature non-volatile memories (NVM) with poly-Si TFTs. Many research groups have reported low-temperature NVM poly-Si TFTs with (i) trapping silicon nitride layer [126], (ii) embedding nickel–nanocrystals (Ni–NCs) into the silicon nitride layer for the trapping layer [127, 128], (iii) In2O3 nanodots embedded in polyimide insulating layer [129] or (iv) using biotechnology [130]. However, in all these cases, the maximum deposition temperature of the whole process exceeded the plastic temperature limit (350 °C), making incompatible with plastic substrates. Since process temperature is a vital concern, organic materials were thoroughly studied to replace the inorganic semiconductors. The polymers can be deposited at low temperature and cost using spin coating, roll-to-roll and inkjet printing [131]. Research in organic TFTs (OTFTs) has had a rapid increase through the years and a carrier mobility as high as 3 cm2/Vs has been exhibited which is similar or even better than that reported for a-Si:H TFTs [132]. Hence, OTFTs were actively investigated for the transistor part of the non-volatile memories (ONVM-TFTs). Pentacene organic semiconductor thin film is one of the most dominant materials [133–135]. Another promising approach is the use of transparent oxide semiconductors for the channel of thin film transistors such as indium gallium zinc oxide (IGZO) [136]. The use of these in a ferroelectric transistor memory on a flexible foil has also been demonstrated recently [137]. Nevertheless, organic materials have some vital drawbacks, such as poor electrical performance, light sensitivity and material degradation caused by the environment. One of the earliest reports on the storage function of TFTs using the floating gate concept was reported as early as 1975 in which cadmium selenide (CdSe) thin film transistor and aluminium thin layer (or clusters) for the floating gate were used [138]. However, due to the rapid evolution of silicon technology, semiconductor chalcogenide compounds did not progress as quickly. The reassessment came years later in order to challenge the established silicon industry and propose alternative materials such as nanoparticles or nanowires of chalcogenide compounds [139]. Hence, for further scaling down nanostructures were considered for their potential integration into electronic devices, either for the semiconductor channel 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 81 area of the transistor or for the floating gate component of the memory cell. The first breakthrough took place in 1995 when Tiwari first proposed the silicon nanocrystals non-volatile memory device, in which the nanocrystals served as discrete nodes for the storage of charges [101].

2.11 Review of the Current Status of Flexible Flash Memories

As previously stated, after the establishment of flexible thin film transistors, some of them were studied in order to develop into flexible flash memory devices. An interesting study by Dr. Young [140] on the fabrication of poly-Si TFTs and memory devices on glass using a silicon nitride layer with a high trapping state density, reported a high field-effect mobility (170 cm2/Vs) as well as a threshold voltage of 4.2 V. The process temperature did not exceed 300 °C, but the poly-Si was produced by the crystallisation of amorphous silicon films using a scanned excimer laser annealing process. To date, the most capable candidates for the flexible flash have been demonstrated to be the organic semiconductor materials that take advantage of the OTFTs for the transistor based memory. Flexible organic pentacene transistor non-volatile memories based on high-dielectric layers [141] or embedding self-assembled gold nanoparticles by solution process [135] are already described in literature. However, the memory window and the retention time are not high enough to fulfil the great demand of high performance flexible flash memory devices. For flexible 2 NVM-OTFT only Ha et al. reported a carrier mobility (4.25 m /Vs) using Al2O3 dielectric layers by solution-based combustion process and gold nanoparticles by contact printing process [142]. Flexible ferroelectric memory seems to be another popular approach in which the gate dielectric is replaced by a ferroelectric insulator [137, 143–146]. Among these, Breemen et al. reported a retention time of more than 12 days using indium-gallium-zinc-oxide (InGaZnO) as the semiconductor layer [137] while with amorphous InGaZnO a TFT mobility of 8 cm2/Vs was measured [143]. Moreover, flexible ferroelectric memory has been demonstrated on a polyethylene naphthalate (PEN) substrate in a NAND-like architecture [146]. Recently, all-solution processed organic transistor flexible memory devices were described [147–149]. The flexible organic transistor showed a very low mobility (0.08 cm2/Vs) and the organic flexible memory had a lower data retention time (105 s). Yet, good endurance and bending stability were reported [149]. Higher mobility (0.8 cm2/Vs) and on/off ratio of 104 were achieved for diode-load inverters [147]. It is worth mentioning that in the above cases the entire fabrication process was performed by using solution-based techniques. A new idea is the use of graphene materials, in particular reduced graphene oxide as the charge-trapping layer, on flexible memory devices based on organic 82 K. Saranti and S. Paul transistor [150]. In addition, C60 molecular floating gate layers were successfully demonstrated as the charge-trapping layer with OTFTs for flexible flash memories [151]. All of these approaches have not been fully explored yet and it is expected that researchers will push these forward. One step further is the use of paper substrates. Martins et al. reported a write-erase and read paper memory transistor with carrier mobility as high as 40 cm2/Vs using an n-type memory field effect transistor [152]. The most recent article uses Fuji Xerox printer paper for the substrate without any treatment. An average carrier mobility value of 0.297 cm2/Vs, on/off ratio >104 and a retention time of 104 s for 25 organic transistors was reported [153]. As a final point, for achieving a fully flexible flash memory some issues should be addressed. First of all, to make the structure flexible, all components must be able to bend to some degree without losing their functionality. In addition, materials with characteristics such as high carrier mobility, low cost, chemical stability and low-temperature fabrication processes should be considered. The reliability of the memory device is also a vital factor. It is possible to overcome these challenges if the device is prefabricated and then transferred onto the plastic substrates. However, that adds one more step to the fabrication process and may significantly increase the cost. The polymer substrates can also be high-temperature substrates like polyimide or polyethersulphone. Still, the overall temperature limit of the full preparation of the flexible flash memory device should be considered.

2.12 Summary

To sum up, nanotechnology and nanomaterials constitute a recent rapid developing area. Nanomaterials are used either to study fundamental quantum phenomena or to fabricate novel and improved performing devices. The state-of-the-art electronic memory devices utilising nanostructures were briefly introduced in this chapter. Side by side, the critical function of the metal catalyst in the growth dynamics of the silicon nanostructures via VLS mechanism was discussed. The energy states of these nanostructures (including the energy traps formed by catalyst materials) can be used for trapping the charge for memory devices. Flash memory cells have been established as the dominant types of the non-volatile semiconductor memories mainly for portable applications. Here, an overview of flash memory and specifically flexible flash memory devices has been presented. The structure, the basic principles behind their working mechanism, the challenges being faced as well as the previous work done in the field of the flexible flash memory devices have been discussed in this chapter. For the fabrication of a fully flexible flash memory, a combination of the required characteristics of the materials as well as a low thermal budget process for the main steps such as the fabrication of the memory element (floating gate) should be taken into consideration. 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash … 83

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Nikolaos Glezos

3.1 Introduction

The attempt to use molecules as functional parts of nanoelectronic devices is based on the benefits expected from their inherent properties. They are stable, with well-defined energy levels, capable of combining chemically to form larger composites with desired properties, capable of self-assembling in dense nanostructures on surfaces and the energy required for their manipulation and during device operation is much less compared to solid-state semiconductor devices. Furthermore if the target of scaling down a specific logic operation in one molecule is achieved, current miniaturization limits will be surpassed. However, although, logic operations on a single molecule have been demonstrated almost from the start, building circuits at a molecular level has a lot of hurdles to surpass. In the course of molecular electronics technology more realistic targets have been set up, one of them is to build hybrid memory cells with a molecular layer as the active element. This review will concentrate on describing the effort to fabricate solid-state non-volatile memory (NVM) elements based on the redox properties of some molecules. In the first part a short overview of molecular electronics will be given, with emphasis on the basic issues of this technology. In the second part the materials and the types of structures will be described. The molecules that have been used so far are mostly organometallic (such as ferrocene and porphyrins) as well as inorganic (polyoxometalates). For their implication in nanodevices and in order to test their operation as device components, several setups have been used. They include, e.g., probing molecules with Scanning Probe Microscopies (STM, AFM) or localization between nanoelectrodes (planar nanoelectrodes, braking junctions). This review will focus on devices that are more practical in the course of

N. Glezos (&) Institute of Nanoscience and Nanotechnology, NCSR “Demokritos”, Patriarchou Gregoriou and Neapoleos, 5310 Aghia Paraskevi, Attiki, Greece e-mail: [email protected]

© Springer International Publishing AG 2017 91 P. Dimitrakis (ed.), Charge-Trapping Non-Volatile Memories, DOI 10.1007/978-3-319-48705-2_3 92 N. Glezos development of functional hybrid semiconductor/molecular layer memory elements. These are either capacitors with dielectrics or MOSFET-type devices. In what follows it will be demonstrated that the fabrication of a hybrid MOSFET ﬂash-type memory element is absolutely feasible by CMOS compatible processes and offers speciﬁc advantages. Recent achievements include nanowire FETs with multimemory states and memory retention/endurance features at least equal to those of existing technology [7, 85].

3.2 Molecular Electronics Overview

Molecular electronics involves the use of single or small groups of molecules in device-based structures as the fundamental units for electronic components such as wires, switches, memory, and gain elements [73]. A molecular device is one which contains one and up to a few thousand molecules as the active element. The goal in molecular electronics is to use the molecules, designed from the “bottom-up” to have specific properties and behaviors, in place of present solid-state electronic devices that are constructed using microelectronic processing from the “top-down”. Bottom-up implies the construction of functionality, i.e., electron storage, into small features, such as molecules, with the opportunity to have the molecules further self-assemble into the higher ordered structural units such as transistors. Self-assembly is a thermodynamically favorable process, i.e., it is energetically favorable for the entities to interact to form some organized aggregate structure. The first fundamental problem is to contact a molecule and transport current through it. This happens in two distinct ways, the first is electron transfer through the molecule, which involves a charge moving from one end of the molecule to the other while the second involves current passing through the whole system of a single molecule and the connecting electrodes. The study of electronic transport in molecules can be traced back to the early 1970s when fatty acid monolayers sandwiched between different electrodes were tested for conductance [55]. The transport results were in accordance with tunneling theory, the tunneling barrier height depending on the position of the work functions of the electrode materials. It is not clear if conduction was through molecular states or the whole system was a simple potential barrier. In 1974, Arieh Aviram and Mark Ratner discussed a possible application of a molecule as a rectifier and attempted a theoretical evaluation of the transport characteristic based on self-consistent field (SCF) molecular orbital calculations [3]. Although this specific molecule has not yet been verified as a rectifier, this paper opened the discussion for intramolecular and intermolecular transport and the theoretical methods to deal with them. Furthermore it put on the table the possibility of using a single molecule to perform an electronic task, in this case rectification. Later in the 1980s, the development of Scanning Probe Microscopies (SPM) enabled to address the problem of contacting a single molecule giving a relative control and allowing the measurement of the conductance of a single molecule. The first significant current operating “device” was based on the 3 Hybrid Memories Based on Redox Molecules 93

“braking junction” principle and it was the pioneering work of Mark Reed and James Tour [63]. They measured transport through a benzene molecule anchored in the braking surface of a gold wire and discovered the existence of current plateaus. This experimental curve was later investigated theoretically and the plateaus were verified using first-principle calculations [22]. The Reed–Tour group continued its work using thiols and fabricated two port devices using conventional microelectronic techniques. These devices demonstrated negative resistance effects, in principle a potential route to a memory element [10]. The theoretical problem that came out of this work was how to deal with electronic transport in a molecular system. At the early stage, this was dealt in a rather simplified way, by considering the electrodes as electron reservoirs close to thermodynamic equilibrium and the molecular system as an energy level system between them, or even simpler, as a tunneling barrier. Some simple cases can be explained by applying similar models and derive the transport characteristics in the frame of known tunneling and thermal mechanisms [80]. A more elaborate answer to the question of how current moves through molecules is now given using nonequilibrium Green’s function techniques [16, 17, 25], a modification of the original approaches to mesoscopic transport in solids [62]. Besides addressing a single molecule, research focused also on fabricating devices by CMOS compatible processes. This inevitably resulted in using architectures involving self-assembled monolayers (SAMs). The crossbar molecular circuit is one of the earliest logic forms of molecular memory arrays [13]. In this application an array of reconfigurable switches was fabricated. The switching element is a metal/molecule/metal sandwich junction, wherein the molecules are located at the cross-section of two nanoscale metal wires. The active element was a monolayer of redox-active rotaxanes. The same group of HP built a 8 Â 8 crossbar switching device. This approach has the advantage of architectural simplicity and the potential of high density via fabrication of highly dense nanowires [11]. An alternative architecture that involves multiple junctions is the so-called nanocell, proposed by researchers at Rice University and Yale University [73]. It is a two-dimensional network of self-assembled metallic particles connected by molecules that show negative differential resistance. Around this network a series of metallic contact lines is used for input/output and programming. These leads allow the creation of pathways that can be programmed and used as a whole as a computing element to perform a specific function. This geometry enables the simulation of neuron cell operation and it is interesting by itself. The molecular devices fabricated up to now fall into the classes of diodes, transistors, switches, and memories. Here are some indicative examples and information sources: (a) Tetraphenyl and nonsymmetric diblock dipyrimidinyl diphenyl molecules covalently bound to two electrodes behave as a diode [23]. This behavior is interpreted in terms of localization of the wave function of the hole ground state at one end of the diblock under the applied field. At large forward current, the molecular diode becomes unstable and quantum point contacts between the electrodes form. (b) A transistor with a 1,4-benzenedithiol (BDT) with a delocalized aromatic ring active channel gold electrodes for source/drain and an 94 N. Glezos aluminum oxide gate dielectric [69]. This work demonstrates direct gate modulation of molecular orbitals using tunneling spectroscopy and validates the concept of molecular orbital-modulated carrier transport. (c) Molecular switches of the con- formational and the redox type have been fabricated using different materials [71, 74]. (d) A memory based on the change of the photoelectrochemical response of rod-shaped ruthenium complexes grafted on ITO electrode in an electrolyte environment. The memory effect is based on Ruthenium oxidation/reduction with P/E pulses [72]. Hybrid devices involving the use of an active molecular layer as part of a semiconductor device is another promising route for the exploitation of molecular properties. The requirement for hybrid devices arises from the need to work within currently available device fabrication techniques and therefore use existing infras- tructure. The key issues are (a) the immobilization of the molecules on the semiconducting surface (silicon in most cases of interest) (b) the isolation of the molecules from the surroundings, and (c) the selection of a CMOS compatible processing that will not harm the molecules. The interface between the molecule and the metallic contact is a critical issue [64, 78]. Here is a list of review articles for orientation in the field of molecular electronics: • McCreery reports on the experimental investigation of molecular junctions up to 2004. Devices based on covalent and Langmuir–Blodgett bonding of single molecules or molecular monolayers to conducting substrates are reviewed, as characterized by scanning probe microscopy and microelectronic techniques [56]. • Vuillaume discusses the metal–molecule problem and updates on functional devices [79]. • Van der Molen and Liljienroth discuss molecular switches and device geometries [74]. • Song, Reed, and Lee examine the experimental aspects of electronic devices made with single molecules and the characterization and manipulation of charge transport in the molecular level [70]. • Aradhya and Venkataraman examine single electron devices beyond electronic transport. They present the emerging methods being used to exploit multiple properties such as optical and spin related [1]. • Cerofolini and Romano discuss in detail the possibility of CMOS fabrication of molecular contacts based on the crossbar architecture with polysilicon nanowires. They examine different possible production protocols [8]. • Cummings, Savchenko, and Reng describe the synthetic approaches to immobilize inorganic compounds on silicon, and the structural, spectroscopic, and voltammetric techniques for characterization of molecular layers and device fabrication procedures [14]. 3 Hybrid Memories Based on Redox Molecules 95

The following books are monographs on the subject or contain extensive chapters: • Introducing Molecular Electronics [15]. • Molecular Electronics: From principles to practice [58]. • Molecular Electronics: Commercial Insights, Chemistry, Devices, Architecture and Programming [73]. • Nano and Molecular Electronics Handbook [53]. • Molecular Electronics: Materials, Devices and Applications [36]. • Electronic Device Architectures for the post-CMOS Era: From Ultimate CMOS Scaling to Beyond CMOS Devices [20]. • Electronic Transport in Mesoscopic Systems [16]. • Lessons from Nanoelectronics: A new perspective in transport [17]. • Transport in Nanostructures [25].

3.3 Memory Cells Based on Redox Molecules

3.3.1 Molecules in Hybrid Devices

Most of the research in the field of molecular electronics focuses on the properties of single molecules and this is understandable, since the final aim is to scale down device properties in the molecular level. However, in order to fabricate realistic devices based on molecular properties seems inevitable to exploit the resources and know-how of current silicon technology. A hybrid molecular/silicon device encompasses a silicon platform and molecular component. The question of interest is “what it is to be gained by replacing a solid-state semiconducting layer or dielectric or conductor by molecules that perform a specific operation in a device?”. The answer is that the inherent scalability without loss of functionality and the possibility to tune their properties according to the application by synthetic chemistry, makes molecules a potential candidate for scaling down electronics. Although a molecular memory is viewed as a long-term goal [34, 57] the hybrid non-volatile silicon/molecular redox memories discussed here, seem very promising [7, 18, 83]. The study of capacitive-based devices is the most natural starting point for the experimental understanding of memories based on molecular layers, due to the robust signal readout and fewer additional CMOS compatible steps [46]. As it will be demonstrated by specific examples, this technology, although at an early stage, has made evident that it is feasible and holds the promise for retention and endurance competitive to existing devices, plus that the charge surface density— stored with single electron precision in a molecular layer—can be higher. The added value of molecular electronics is (a) the possibility to address more than two memory states (0,1) as many as the number of redox states of the molecule used and (b) the accessibility of these states by low voltages. The redox molecules mostly used for such an application are ferrocene derivatives, porphyrins and polyoxometalates, and they will be presented in this order in 96 N. Glezos

Table 3.1 Hybrid devices for molecular memories

Electrolyte/Molecule/SiO2/Si Capacitor • Roth et al. [66] • Li et al. [44, 47, 49] • Pro et al. [60] • De Salvo and Buckley [18]

Metal/Molecule/Si Contact or Metal/Molecule/SiO2/Si Capacitor • Balliou et al. [6]

Metal/Dielectric/Molecule/SiO2/Si Capacitor • Shaw et al. [67] • Zhu et al. [84] • Balliou et al. [5]

Side Gate Nanowire MOSFET • Busche et al. [7]

Top Gate Nanowire MOSFET • Zhu et al. [85]

sequence. Other redox molecules have also been tested such as a Fe-terpyridine compound [44, 47] or Ru complexes [72, 85], the methods and approaches being the same as for the other redox molecules. The devices and structures to be discussed are all of the capacitive or MOSFET type and are summarized in Table 3.1 with some indicative references.

3.3.2 Ferrocene

Ferrocene is an organometallic compound with the formula Fe(C5H5)2.Itisa type of chemical compound consisting of two cyclopentadienyl rings bound on opposite sides of a central metal atom. Such structures are also known as sandwich 3 Hybrid Memories Based on Redox Molecules 97 compounds. The rapid growth of organometallic chemistry is often attributed to the excitement arising from the discovery of ferrocene and its many analogues. In terms of bonding, the iron center in ferrocene is usually assigned to the +2 oxidation state. On each cyclopentadienyl (Cp) ring a single negative charge is allocated, bringing the number of p-electrons on each ring to six, and thus making them aromatic. These twelve electrons (six from each ring) are then shared with the metal via covalent bonding. When combined with the six d-electrons on Fe2+, the complex attains an 18-electron configuration (Fig. 3.1). Ferrocene and its numerous derivatives some special applications which exploit its unusual structure, robustness, and redox properties [32]. Such applications include the use as antiknock agents used in the fuel for petrol engines, medical application related to anticancer activity and as a catalyst in the fabrication of carbon nanotubes. Ferrocene undergoes a one-electron oxidation at a low potential, around 0.5 V versus a saturated calomel electrode (SCE). This reversible oxidation has itself been used as standard in electrochemistry as Fc+/Fc = 0.64 V versus the standard hydrogen electrode. Oxidation of ferrocene gives the stable blue-colored cation [Fe(C5H5)2]+ called ferrocenium. Ferrocenium salts are sometimes used as oxidizing agents. The ease of handling, its stability, and the one-electron oxidation were the reasons for being one of the first materials to be tested in molecular memory applications as a two-state molecule. Earlier work involved addressing these states in metal/electrolyte/molecule/SiO2/Si [48, 49]. The main advantage of this kind of structures is that it is not necessary to evaporate a top electrode on the molecular layer and that they provide a direct comparison of the results of Cyclic Voltammetry (CyV) with those obtained with conventional methods. The substrates used were p-Si wafers. Active square areas of 100–200 lm side were defined through a 380 nm field oxide using photolithography. Thin 1.2–3 nm oxide layers were formed to serve as tunneling oxides. The molecules were attached through phosphonate-terminated linkers resulting in P–O–Si linkages. The electrical characterization utilized a silver gate electrode and a solution of 1.0 M tetrabutylam- monium hexafluorophosphate in propylene carbonate as the conducting gate

Fig. 3.1 Structure of ferrocene 98 N. Glezos electrolyte. The current peaks observed in CyV measurements at oxidizing and reducing voltages (VPO and VPR) are due to the charging and discharging transient currents associated with oxidation and reduction of the molecules. As the CyV scan rate is increased, the oxidation voltages shift to the left while the reduction voltages shift to the right. Hence, the peak separation increases from 0.18 to 0.38 V as the scanning rate increases from 2 to 20 V/s, though the average redox voltage VO =(VPR +VPO)/2 remains constant at −0.19 V. The increasing peak separation could be attributed to an increasingly large resistive drop in the electrolyte and also could indicate that the scan rates are becoming nonnegligible compared with the overall rate of electron transfer between the redox center of the ferrocene and the Si substrate. The peaks observed in capacitance and conductance measurements are attributed to the movement of charge to or from a trapped state in the redox-active molecule. This mechanism is similar to the dependence of interface states on frequency in a metal–SiO2–Si capacitor (Figs. 3.2 and 3.3). This result was further elaborated to clarify the role of the linker [60]. A ferrocene derivative as well as a porphyrine one were grafted on a SiO2 surface either directly or through linkers in electrolyte capacitor structures. The CyV and C-V measurements revealed that the linker acts as an additional barrier by shifting the peaks to higher voltage values. It was also found that the C-V peaks also depend upon the frequency used and they are more pronounced in the case of lower frequencies. This can be explained easily by the fact that at low frequencies, the charge movement can occur at a rate comparable to the measurement signal and is reﬂected by the presence of the peak. On the other hand at high frequencies the electron-transfer process becomes gradually rate-limited until a threshold frequency appears when no peak occurs. In this work an original electrical model was developed in order to predict the structure of the capacitance/conductance peaks of

Fig. 3.2 a The structure of dihydroxyphosphorylmethylferrocene and b Schematic of the electrolyte hybrid silicon capacitor with a simpliﬁed equivalent circuit. Reprinted with permission from [49]. Copyright 2003, AIP 3 Hybrid Memories Based on Redox Molecules 99

Fig. 3.3 Capacitance–voltage hysteresis of the electrolyte-molecule-oxide-silicon (TOX = 1.25– 2.85 nm) capacitor and electrolyte-oxide-silicon (TOX = 1.49 nm capacitor at 100 Hz. All the curves show depletion peaks but only the capacitors with TOX = 1.8 nm show oxidation and reduction peaks. Reprinted with permission from [49]. Copyright 2003, AIP the CV measurements. In this model, the oxidation and reduction of the molecules grafted on Si are regarded as the filling/emptying process of traps on the silicon surface in consistency with the Shockley–Read–Hall approach [68]. The results obtained for the position of the peaks and their dependence upon frequency are consistent with experimental values. Although open structures and electrolyte MOS capacitors are useful for the evaluation of the memory properties and the study of the influence of various device parameters, the final aim is the fabrication of a solid-state device, e.g., a flash-type MOSFET memory structure. To this end it is necessary to fabricate and optimize solid-state capacitors and it is inevitable to cap the molecular layer with a suitable solid-state dielectric. In the case of a ferrocene memory cell, aluminum oxide was tested as a capping layer [84] (Fig. 3.4). The most important fabrication process steps for this device are the attachment of the molecules on SiO2 and the formation of Al2O3 encapsulating the molecules. First, SiO2 (110 nm) is thermally grown on p-Si (100) substrate followed by the definition of square-shaped active areas (100 lm wide) using photolithography and wet etching. Next, a thin SiO2 (1.5 nm) is grown on Si in the active area. The molecules are then self-assembled on the SiO2 by immersing the wafer into a solution of a-Ferrocenylethanol indichloromethane (DCM). The redox molecules are covalently bonded to the SiO2 surface through the –OH linker. Next the Al2O3 layer is deposited using an ALD process. In order to ensure that the molecules survive the process, XPS spectroscopy was performed before applying the final gate electrode. Besides the basic structure MAFOS, three control structures were also fabricated, namely MAFS, MAOS, MAS (M = metal, A = Al2O3, F = Ferrocene, O = SiO2, and S = p-type S substrate) were fabricated. The CV measurements on 100 N. Glezos

Fig. 3.4 a Molecule structure of a-Ferrocenylethanol and schematic of the MAFOS capacitor structure. b Flat-band voltage shift DVFB of MAFOS and three control samples as a function of Program/Erase voltage with pulse width 500 ls. Reprinted with permission from [84]. Copyright 2013, AIP these devices revealed that the oxide traps were not significant in charging the device during the P/E operation. They also demonstrated that the bottom tunneling oxide is a necessity for charge retention. MAFS devices have a good program speed but not a good erase speed, indicating that it is more difficult for the Ferrocene layer to stay positively charged without the isolating layer. The MAFOS devices demonstrated retention time 106 s, acceptable for a non-volatile memory operation. The memory endurance test revealed a stability for times <108 s. A simple FET construction for testing purposes is a back gated FET transistor with exposed source-drain electrodes on which the molecular layer is deposited last. The obvious disadvantage is that charge in less effectively controlled by the extended back gate and the layer is exposed to the atmosphere. An alternative way to test the layer in a similar construction is to use the FET as a two-port device and control the change in the channel and the charging by controlling the source-drain current. This was tried out in the case of ferrocene [30]. When the SD Voltage is varied with the other terminals kept floating two peaks appeared when ferrocene was used as the charging layer of a p-channel MOSFET. These two peaks are due to the possible channels for the electrons to and from the molecular layer, i.e., either directly from the N/P+ diode of the Drain electrode or through the P+ Drain directly. This can lead to a two-state memory. However, the best way to exploit a redox molecule in a solid-state device seems to be through the construction of a MOSFET-like flash memory based on a nanowire channel [85]. A nanowire transistor as a test bed for molecular devices presents advantages when compared to planar FETs based on bulk materials. The nanowires have a smaller channel and large surface-to-volume ratio. Thus, nanowire structures promise a more efficient memory with less stored charge inducing a comparable memory window. This is ideal when a molecular layer is used to provide the charge in a controllable way. Although nanowire FETs are usually fabricated using electron 3 Hybrid Memories Based on Redox Molecules 101 beam lithography combined with conventional photolithography, in this work a self-aligned Si nanowire fabrication method was followed: A 300 nm SiO2 was first grown on a highly doped p-type Si (100) wafer by dry oxidization. Then a thin film of Au catalyst (2–3 nm) was deposited onto a patterned area predefined by photolithography. Next, the Si nanowires were grown from the catalyst in a low-pressure chemical vapor deposition (LPCVD) furnace with an ambient SiH4 stream under pressure. The Si nanowires grown this way have typical lengths of 20 lm and a 20 nm diameter. Immediately after the growth step, the Si nanowires were oxidized to form a 3 nm SiO2 on which the SAM will be formed. The Ti/Pt source/drain (S/D) electrodes were patterned with photolithography. The channel length between the S/D electrodes was controlled to be 6 lm (Fig. 3.5). Two different devices were fabricated, one using a-ferrocenylethanol (referred as ferrocene) and one using Ru2(ap)4(C2C6H4P(O)(OH)2) (referred as Ru2), in which ap = 2-anilinopyridinate. The molecules were deposited over the SiO2 by placing droplets of dichloromethane solutions on the devices heated in a nitrogen environment. Saturated SAMs were formed and the wafers were rinsed with dichloromethane in order to remove any residual nonbonded molecules. The molecular layer was capped by a 25 nm layer of Al2O3 deposited by atomic layer deposition (ALD). Over this structure a 100 nm Pd top gate was formed with the same

Fig. 3.5 A molecular non-volatile memory based on a Si MOSFET nanowire transistor [85]. The setup was tested with Ferrocene as well as Ruthenium complex. The Ru molecule has two redox states indicated in the Vth diagram as plateaus, thus leading to the possibility of a three-state memory. The device can withstand 1010 program/erase cycles without deterioration. Reprinted with permission from [85]. Copyright 2015, ACS Publications 102 N. Glezos photolithographic and lift-off processes as S/D electrodes. In the resulting structure, an “intermixed” 6 nm thickness region was formed in which the redox molecules diffuse in the Al2O3 dielectric. A reference sample without redox molecules was fabricated at the same time for comparison. The MOSFETs have Schottky barrier p-type I-V characteristics. The IDS-VDS curves are smooth with negligible contact resistance. However, the presence of the charging molecules results in hysteresis loops in the transfer IDS-VGS characteristics. The memory window starts to appear at 3 V and increases when swept up to 10 V. The On–Off ratio is as high as 107. The memory operation depends on the charging state of the molecules. The devices were tested with Program/Erase (P/E) pulses of up to ±10 V and a pulse width in the 1 lsec–1 s range showing excellent performance for values as low as 500 lsec. The dependence of the Flat-Band Voltage shift (DVth) on the P/E voltage was studied. In the case of the reference sample this shift is negligible, demonstrating that oxide traps have a minimal effect in the device and the charge comes from the molecules. In the case of ferrocene DVth saturates for pulses ±26 V at a value of 1.69 V suggesting that all available redox centers have been occupied by charge. One important finding is that in the case of Ru2, a two-step charge-storage behavior was observed due to the two redox states in the Ru2 molecules which can exhibit stable and distinct charged states at different voltage level. With increasing programming gate voltage, the first step charged state was observed at 10 V, with 0.8 V DVTh, indicating that the Ru2 redox centers with lower voltage levels have been occupied by electrons. With increasing programming voltage, the second charged state step was observed beyond VGS = 14 V with a saturated DVTh of 1.95 V. This suggests that all the Ru2 redox centers in the molecules have been filled with injected electrons. This paves the way to multistage memory devices based on discrete molecular charging states. Good charge retention characteristics were observed, with a projected 10-year memory window showing only 20% charge loss for both devices. The good retention is due to the intrinsic stable redox behavior of the molecules and the high-quality tunnel oxide with clean solid/molecule and dielectric interfaces using the self-alignment fabrication process. This further supports the mechanism of dominant charge storage located in the redox centers of the molecules instead of the molecule. Both devices showed excellent endurance characteristics, with negligible memory window degradation after 108 P/E cycles by applying 500 ls P/E voltages. With 100 ls P/E voltages, the device still functions perfectly even after 109 P/E cycles. This is about several decades higher than that of the conventional floating gate memory (105 cycles). The lessons learned from this work is that (a) the molecular layer for a non-volatile memory applications should be localized in nano-dimensions (in this case a nanowire) in a device sensitive to small changes in charging (b) capping with a suitable dielectric without defects is necessary in order to isolate the layer from the control gate and protect it from environmental changes, and (c) that a molecular multi-valued memory is feasible. 3 Hybrid Memories Based on Redox Molecules 103

3.3.3 Porphyrins

Porphyrins are a group of heterocyclic macrocycle organic compounds, composed of four modiﬁed pyrrole subunits interconnected at their a carbon atoms via methine bridges (=CH–). The parent porphyrin is porphin, and substituted por- phines are called porphyrins. The porphyrin ring structure is aromatic, with a total of 26 electrons in the conjugated system. Porphyrin molecules typically have very intense absorption bands in the visible region and may be deeply colored (in greek poquύqa = purple). Many porphyrins are naturally occurring; one of the best- known porphyrins is heme (in greek aίla = blood), the pigment in red blood cells, a cofactor of the protein hemoglobin. Porphyrins are the conjugate acids of ligands that bind metals to form complexes. The metal ion usually has a charge of 2+ or 3+. A porphyrin without a metal ion in its cavity is a free base. Some iron-containing porphyrins are called hemes. Heme-containing proteins, or hemoproteins (e.g., hemoglobin and myoglobin), are found extensively in nature. The main function of porphyrins is to support aerobic life. There are several applications in medicine (e.g., photodynamic therapy), as oxidation catalysts of organic compounds and in supramolecualr chemistry. Phthalocyanines, which are structurally related to porphyrins, are commercial dyes and catalysts. In the ﬁeld of molecular electronics synthetic porphyrin dyes have been incorporated in prototype dye-sensitized solar cells [82]. The redox structure of porphyrins has been investigated theoretically [45]. Porphyrins were investigated as candidates for molecular memories as early as 1994 [35]. Junctions with free base porphyrin monolayers with polyimide were fabricated and the tunneling properties were studied using Inelastic Electron Tunneling Spectroscopy (IETS). They found many peaks at low voltages due to vibrational modes of the molecules but one large peak at 1.9 V due to the redox state. Roth et al. [66] measured both electron-transfer rates and charge retention times for ferrocene and a Zn(II) trimesitylporphyrin, each derivatized with a benzyl alcohol linker for attachment to the Si surface via the formation of a Si–O bond. They performed measurements in an electrochemical cell and found memory retentions competing silicon DRAM capacitors. In a previews work [65] used Au and four zinc porphyrins, and also found retention times of the order of hundreds of seconds. The potential of porphyrins to withstand silicon processing and device operation has been proved [50]. Indeed if molecular components are to be used as functional elements in place of the semiconductor-based devices present in conventional micro circuitry, they must compete with semiconductors under the extreme conditions required for processing and operating a practical device. In the case of porphyrin- based molecules bound to Si, it was proved that they can meet this challenge. These molecular media in an inert atmosphere are stable under extremes of temperature (400 °C) for extended periods (approaching 1 h) and do not degrade under large numbers of read-write cycles (1012). Solid-state capacitors with porphyrins have also been studied in comparison to ferrocene derivatives [67]. A step forward is to combine these two molecules in a 104 N. Glezos unique monolayer. This results in a multistate memory cell [44, 47]. The mixed SAMs were prepared using a benzyl alcohol-tethered ferrocene (Fc-BzOH) and a benzyl alcohol-tethered porphyrin (Por-BzOH). The ferrocene provides one state (monopositive) while the porphyrin provides two states (monopositive, dipositive). The SAMs were deposited on p-type Si substrates where the native oxide was removed with an HF solution to ensure direct contact of the molecules with Si. The device fabricated was an electrolyte/molecule/Si contact. The benzyl alcohol tether affords attachment to the silicon surface via the formation of a Si–O bond. Cyclic Voltammetry was used in order measure the coverage and the redox potentials of the mixed SAMs. The dependence of the distance and the height of the redox peaks upon the relative concentrations of the mixture were studied. Furthermore CV measurements at a low frequency (100 Hz) revealed peaks for the same voltages. Three peaks were observed: 0.35 V (Fc) and 0.70, 1.05 V (Por). Thus a two-bit (four-state memory cell is possible, while the programming voltages are quite law (Fig. 3.6). The work on porphyrins has been recently reviewed [19, 38].

Fig. 3.6 Molecular structure of Fc-BzOH and Por-BzOH and capacitance/conductance results of different mixtures. Reprinted with permission from [44, 47]. Copyright 2004, John Wiley and Sons 3 Hybrid Memories Based on Redox Molecules 105

3.3.4 Polyoxomatalates

Polyoxometalates (POMs) are a subset of metal oxides that represent a diverse range of molecular clusters with a wide range of physical properties and the ability to form structures from nanometers to even micrometers [51]. Due to their rich structure and diverse properties, POMs have a potential to be used as building blocks for new materials. The popularity rise of POMs started in 1991 [59]. In general POMs are based upon metal oxide building blocks with a general formula {MOx}n, where M = Mo, W, V, and sometimes Nb and x =4–7. Overall, POM clusters are normally anionic and thus can be combined with additional cations as linkers, which can include heteroatom templates, and they can also form lacunary structures, whereby some of the cage atoms are removed to create vacancies that can be ﬁlled by linker atoms. The structures of POMs can be broken down into three broad subsets [52]: (a) Heteropolyanions are metal oxide clusters that include heteroanions such as 2− 3− SO4 and PO4 . These are by far the most explored subset of POM clusters; much of this research has examined the catalytic properties of POMs, with great n− n− emphasis on the Keggin [XM12O40] and Wells–Dawson [X2M18O62] anions (where M = W or Mo; X is a tetrahedral template). Tungsten-based POMs are robust, and this fact has been exploited to develop tungsten-based Keggin and Dawson anions with vacancies (most commonly with one, two, or three vacancies) that can be linked using electrophiles to larger aggregates in a predictable manner. (b) Isopolyanions are composed of a metal oxide framework, but without the internal heteroatom/heteroanion and they are often much more unstable than their heteropolyanion counterparts. However they also have interesting physical properties, such as high charges and strongly basic oxygen surfaces, which means they are attractive units for use as building blocks. (c) Molybdenum blue and molybdenum brown reduced POM clusters are related to molybdenum blue species. A very high-nuclearity ball-like cluster {Mo154} with a ring topology can be crystallized from a solution of molybdenum blue. It has been demonstrated that the redox properties of POMs present similarities with properties of aggregates of various metal oxides [33]. Some general points: (a) If one looks at the electronic absorption spectra of the oxidized and reduced WO3 colloids and at their electrochemical behavior, it can be seen that they have a pattern characteristic of polyoxotungstates. The case of TiO2 is also similar. The overall resemblance to the spectra of POM is apparent. The blue color of reduced POM is thus attributed to intra electron transfer between adjacent metal ions, M–M charge transfer (CT) bands and a somewhat similar explanation holds for the blue coloration of reduced WO3 and TiO2. 106 N. Glezos

(b) The band gap (Eg) in semiconducting metal oxides (SC), is a function of the size of the metal oxide particulates. The smaller the size, the higher the Eg. A similar trend is noticed with POM as exemplified by the threshold and peak absorptions of the spectra of Keggin (ionic size ca. 7.2 nm3) and Wells– Dawson (ionic size ca. 10.3 nm3) structures of phosphomolybdates and phosphotungstates, that have overall similar characteristics. The ground state potentials of POMs are similar to those of TiO2 and WO3 for example. The 3− HOMO-LUMO gap for PW12O40 as one case, is 3.5 eV while the corresponding values of TiO2 and WO3 are 3.0 and 3.4 eV, while their LUMO levels are relatively close. (c) It has been stated that accumulation of electrons on POM lowers the efficiency of photoreaction. An analogous statement has been made for semiconducting TiO2, namely, that accumulation of electrons on SC lowers the quantum yield by increasing the electron–hole recombination rate. (d) Appreciable negative charge can be built up on metal oxide particulates in the absence of an acceptor. This is also true for POM, whose characteristic property is that they undergo multiple, stepwise, ‘reversible’ reductions without decomposition. (e) Accumulation of charge on SC drives the redox potential to more negative values, i.e., the redox potential is a function of the charge density. The same is true for POMs. (f) The rate-determining step in photocatalytic processes with metal oxide particulates was reported to be the removal of the electrons from the SC. A similar statement has been made for POM, namely, that the rate-determining step in the photocatalytic cycle is the regeneration (reoxidation) of the catalyst. (g) Both systems, i.e., polyoxotungstates and TiO2 particulates, are effective photocatalysts for the mineralization to CO2,H2O, and inorganic anions of a great variety of organic pollutants (Fig. 3.7). Due to the above features there is a potential for exploitation of their electronic and optical properties in device applications such as electrochromic displays, dopants for conductive polymers, gas and chemical sensors, capacitors, and electrochemical cells [42]. The most important feature of POMs which makes them attractive for molecular memory applications is that they have a high charge and their redox state doesn't have much influence on the stability of their structure. They can be considered as a nanoscale-sized cage with the possibility of hosting several types of templates. If these moieties are selected to be electronically active this could lead the road of designing molecular transition metal oxides (TMOs) with properties different than those of bulk TMOs. For example, a Dawson molybdenum 2− or tungstate POM may accommodate two tetrahedral anions, e.g., sulphate (SO4 ) 3− or phosphate (PO4 ) vital for the stability and integrity of the molecule. The 4− [Mo18O54(SO3)2] molecular cluster, which displays thermochromic behavior [4] contains two sulphite anions, which under specific conditions may be reduced to form an S–S bond and release two electrons to the external cage. This change has not been observed in solution or in the solid state. However, it has been 3 Hybrid Memories Based on Redox Molecules 107

Fig. 3.7 Ground state and excited state redox potentials and corresponding energy levels, relative to vacuum and to NHE (normal hydrogen electrode), of some POM together with those of WO3 and TiO2, for comparison. Reprinted with permission from [33]. Copyright 2001, Royal Society of Chemistry demonstrated in the case of a monolayer on an Au surface [26]. A thermal cycle from 298 to 77 K and back caused reversible formation and brake of the S–S bond. This is the result of decreasing the distance of the sulfite groups by thermal activation resulting in bond formation. By theoretical evaluations it was proved that the role of the Au substrate was crucial in this effect since it is assisted from the image charges accumulated on the surface. Indeed the same effect was not observed on other surfaces such as graphite (HOPG). There are two possible methods to use POM molecules as active components of electronic devices, either to embed them in polymeric matrices or to formulate monolayers on surfaces. In the first case it is required that the host material should not react with the embedded molecules, thus altering their transport properties. A tungstate POM was embedded in poly-methyl-methacrylate (PMMA) in order to investigate the transport properties of the composite material in the nanometer region [28]. PMMA is well-suited as polymeric matrix material, because it does not react with acids at relatively low temperatures (e.g., it does not practically give de-esterification reactions at temperatures below 150 °C) and can be used as polymeric gate dielectric in FET devices due to its capacity for the formation of uniform thin films characterized by reasonable breakdown voltages and long-term electrical stability. Solutions of 3− (PW12O40) and high molecular weight PMMA into PGMEA solvent were prepared. The relative weight concentration POM/PMMA was varied in the range 1:4 w/w (equal weights of POM and PMMA) up to 5:1 w/w in order to examine the dependence of the transport characteristics upon the mean distance of the active molecules. The 1:4 formulation corresponds to a mean molecular distance of approximately 2.8 nm in solid film. The approaching distance for electron hopping 108 N. Glezos between molecules varies from d = 1.6 nm in the 1:4 w/w case to 0.5 nm 5:1 w/w case. The dependence of the conducting behavior upon the electrode distance was investigated. Aluminum electrodes with an interlectrode distance in the range 10 nm up to several micrometers were patterned on a SiO2 surface with electron beam lithography. The structure of the I–V characteristics depends upon the intermolecular distance and the electrode spacing. Tunneling effects expressed as conductivity peaks appear when the intermolecular distance d is less than 3 nm corresponding to a POM/PMMA relative concentration of 1:1 w/w and the electrode spacing is less than 100 nm. In the case of higher POM concentrations the current follows a Space Charge Limited (SCL) square. The situation is typical for one type of carriers in the presence of traps, in this case the tungstate molecules (Fig. 3.8).

Fig. 3.8 Current (solid line) and conductance (dashed line) curves in the case of a 1:1 w/w POM/PMMA composite with intermolecular distance of POMs 1.9 nm. Given that the molecular size is approximately 1 nm, the average electron path in the case of the 25 nm electrodes consists of 8–10 tunneling events. The low voltage plateau (b) is discussed in terms of low voltage tunneling and the region of the conductivity peak in terms of the Fowler–Nordheim mechanism (c). Reprinted with permission from [28]. Copyright 2003, AIP Publishing LLC 3 Hybrid Memories Based on Redox Molecules 109

This result was further elaborated in order to discuss the dependence of the transport characteristics upon the electrode material, the evaluation of the contact barriers and the influence of the type of contacts. Two kinds of electrodes were tested (a) parallel electrodes with a nanodistance and (b) opposite electrodes with a nanometer front [76]. One important finding was that the inclusion of POM molecules in the PMMA matrix had no effect on its structure and concentration as manifested by monitoring possible changes through its characteristic UV absorption spectrum during processing. The formulation of an active molecular material with lithographic capabilities would be advantageous for the fabrication of devices. Negative tone formulations of a POM containing material have been already proposed for bilayer DUV and X-ray lithography [2]. The tungstate POM was used as a photosensitizer. A 12-tungstophosphoric acid, H3PW12O40 and polyvinyl alcohol (PVA) were mixed to produce a lithographic resist. Thin films of this resist were processed with 254 nm UV light and 300 nm features were obtained. Removal of the PVA at 400 °C in air leaves a tungsten oxide film, with grains that are small enough to allow moderate temperature (450* furnace, or ambient temperature plasma hydrogen reduction to tungsten metal which serves for electroless deposition of nickel. This method was used for the fabrication of metallic bias in integrated circuits. These PVA-based formulations exhibit excellent resolution performance, approaching the limit of photolithography, but failed to attract industrial attention due to their unconventional processing. To cope with processing difficulties of PVA formulations, as well as to obtain a positive tone resist for electron beam lithography, various compositions of polymethyl methacrylate(PMMA) blended with 12-tungstophosphoric acid, H3PW12O40 were examined [9]. Compositions such as 1:1 PMMA to POM weight ratio material has a very good lithographic performance, with no loss of resolution compared to the pure PMMA. The lithographic process followed was the very same as the one used in PMMA, i.e., spinning, pre-exposure bake of 160 °C for 1 h, electron beam exposure and development in a methyl isobutyl ketone (MIBK) to isopropanol (IPA) solution 1 over 3, for 3 min. With such standard conditions, 60 nm lines where easily obtained. The dose required for high-resolution lines was about 30% higher than for pure PMMA resists. This is attributed to the fact that a considerable part of the incident energy is absorbed in the excitation of the polyoxometalates, thus not contributing to PMMA chemistry a fact verified by simulation (Fig. 3.9). One important issue in the case of the PMMA/POM material is to maintain the POM molecules intact and avoid reactions with the matrix. This has been extensively studied (Kapetanakis et al. Hybrid organic–inorganic materials for molecular proton memory devices [41]) and the main result is that there is no reaction if the processing temperature stays lower than 120 °C. However, when temperature increases substantial changes can be detected in the PMMA-related-FTIR peaks. These data point out possible formation of glutaric anhydride through the acid-catalyzed hydrolysis of PMMA by POM in the presence of water (derived from the atmosphere) and the subsequent dehydration of the poly(methacrylic acid) formed (Fig. 3.10). 110 N. Glezos

Fig. 3.9 Electron beam lithography patterning on a PVA/POM and b PMMA/POM. In the ﬁrst case the POM acts as a sensitizer and its concentration changes during the process. The line edge roughness is signiﬁcant. In the second case, the POM molecules remain intact from the lithographic process thus allowing the use as an active material in a molecular device. Reprinted with permission from [9]. Copyright 2004, Elsevier

Fig. 3.10 UV spectra showing the change of the characteristic POM peak at 266 nm of the HPW/PMMA layer (HPW: phosphotungstic POM) induced by the coating of a PMMA layer on top of it. The lower layer (HPW/PMMA) was treated thermally at 120 °C for two different durations: 10 and 60 min. The upper layer (PMMA) was treated thermally at the same temperature for 5 min in both cases. Solutions: PMMA 5% (w/w) and HPW/PMMA 5/5 % (w/w). Reprinted with permission from [41]. Copyright 2009, Elsevier

The POM/PMMA blend is a suitable candidate material for ionic memory applications. Hybrid devices containing this material and built on n-type Si have been demonstrated [40]. These storage elements comprise a proton-conducting polymeric layer (PCL), in this case POM/PMMA. Application of an electric field across the PCL produces anions and protons. The protons can be moved at either side of the PCL depending on the direction of the applied electric field. This temporary transfer of protons confers bistability and long-refresh volatile memory properties to the devices. In addition to the PCL, a molecular storage element may comprise a second proton trapping layer (PTL), in this case 2-amino-anthracene embedded in PMMA. Application of an electric field across the storage element 3 Hybrid Memories Based on Redox Molecules 111 allows trapping of protons in the PTL and thereby, offers a non-volatile function to the memory device. Test devices demonstrated considerable memory retention. The fabrication of self-assembled monolayers of POMs is a basic requirement both for planar FET-type devices as well as for capacitor type structures since in this kind of films the properties of individual molecules become prominent. Various methods can be used [37], for example, (a) spontaneous adsorption, (b) electrode- position under constant potential, and (c) layer-by-layer self-assembly of alternating layers of POMs and positively charged species. The latter technique is especially attractive as it provides control of the structure of POM-based films at the nanometer scale. While most POM-based hybrid materials reported to date involve non-covalent interactions, for example, van der Waals contacts, hydrogen bonding, and ionic interactions, a few hybrid polymers involve covalent linking. The Langmuir and Langmuir–Blodgett (LB) method is also applicable in the case of polyoxometalates. Films have been fabricated by taking advantage of the adsorption properties of these polyanions on a positively charged monolayer of an organic surfactant spread on water and their electrochemical and electrochromic properties have been investigated [12]. Hybrid materials containing alternate monolayers of anionic POMs and cationic organic molecules such as polyelectrolytes, porphyrins, dyes, or long alkyl chain amines have been fabricated using the layer-by-layer (LBL) self-assembly method. The grafting of POMs on surfaces [61] such as Silicon [24, 77], metals [81], and glasses [21] is well documented. A planar device is defined as a structure with source-drain electrodes on an insulating surface. In order to fabricate pseudo-MOSFET devices it is convenient to select a Si substrate. This offers some important advantages: (a) grafting a molecular layer on Si is far more controllable than on other surfaces, (b) CMOS processes can be used to fabricate the electrodes and define the tunneling oxide, (c) a back gate is easy to make thus giving some control on the conductance channel since making a top gate on a molecular layer is far more complicated, and (d) one may take advantage of existing methods of characterization of CMOS devices to bring forward the properties of the molecular layer. A metal (Au or Al) may be used for the formation of the nanoelectrodes or they can be defined as doped semiconducting regions [31] on a silicon on insulator (SOI) surface. A tungsten POM has been used as an active channel in a planar device with Al nanoelectrodes defined on Si [24]. POM-based films (both single-layers and multilayers) have been grafted on the surface in a controlled and reproducible way using the Layer-by-Layer method (LbL).The layers consist of 12-tungstophosphoric acid hydrate POM (H3PW12O40∙xH2O) interconnected with 1,12-diaminododecane (DD). The first POM layer bonds with a 3-aminopropyl triethoxysilane (APTES) layer electrostatic 3− interactions between POM anions (PW12O40 ) and protonated amino groups (NH3+). The process was monitored by UV and FTIR measurements and the optimum process was obtained. This required increasing the POM concentration in each step. The film thickness of each added layer and the change in the potential barrier was checked by electrical measurements by capping the layers deposited on Silicon with an Al electrode and analyze the tunneling curves in the low and high voltage regime [29]. It was found that the average thickness increase when a 112 N. Glezos

0.40 0.25

0.35 0.20

0.30 0.15

0.25 0.10 Absorbance at 270 nm

0.20 2345 Number of POM-ended bilayers 0.15 Absorbance A(PD)P 0.10 A(PD) P 2 A(PD) P 3 0.05 A(PD) P 4 0.00 200 225 250 275 300 325 350 375 Wavelength (nm)

Fig. 3.11 (Left) Schematic diagram of APTES–(POM–DD)2POM multilayer film(3-POM layer film) prepared with LBL method on Si wafer. (Right) UV spectra obtained during the fabrication of five POM layers following the optimum fabrication process at constant pH 0.5. Inset: change of the absorption peak intensity of POM at 270 nm with the number of POM-ended bilayers. Reprinted with permission from [24]. Copyright 2008, ACS

POM–DD layer was added is 1.2 nm. On the other hand the potential barrier for the composite Si/POM/Al system is larger in the case of a single POM layer (0.44 eV) and reaches a steady value of 0.25 eV in the case of several layers (Fig. 3.11). Furthermore, electrical characterization of the produced films followed with the appropriate theoretical analysis elucidated the conduction mechanisms through these films in relation to their structural properties. Electron transport analysis revealed the coexistence of tunneling, hopping, and percolation depending on the temperature range, the electrode distance, and the number of layers (Fig. 3.12). Specifically in the case of a single layer [75] new structures were fabricated, this time with Au nanoelectrodes and it was found that the dominant conduction mechanism for high temperatures (T > 200 K) is hopping with an activation energy of 80 meV, for low temperatures (T < 150 K) the indirect tunneling with an average tunneling barrier between the Au electrode and the POM molecules of 370 meV, while for temperatures between 150 and 200 K the two mechanisms coexist. In other words, while at low temperatures the electrons move from a POM anion to the next one tunneling through the intermediate barrier, at high temperatures the electrons have adequate thermal energy to travel to the neighboring anion by passing over the barrier. When the electrode distance increases, the transition between the two regions becomes sharper (Fig. 3.13). Vertical capacitor-type devices in general have some advantages over planar ones where molecular layers are included such as (a) statistically averaging transport through single molecules, (b) taking advantage of the capacitance changes when molecules are charged, (c) the isolation of molecules from the environment, and (d) the whole process can be CMOS compatible. In the case of the POM multilayers discussed above [24] hybrid capacitors on n-type and p-type Silicon were constructed [54]. In this geometry, a thick gate oxide 3 Hybrid Memories Based on Redox Molecules 113

Fig. 3.12 Schematic diagram of the transport mechanism model through the various film types at the high-voltage regime. For POM-ending films electron transport occurs through POM molecules: a When the gap between the electrodes is relatively short (50 nm) and the applied bias is sufficient, the electrons can tunnel to the other electrode. b When the gap becomes relatively wide (150 nm percolation dominates. c In case of DD ending films the electrons tunnel through the aggregates formed (due to the presence of the DD final layer) irrespective of gap width. d When more layers are added FN tunneling can be realized even at relatively wide gaps. Reprinted with permission from [24]. Copyright 2008, ACS was used to isolate each structure and the control oxide isolating the layer from the Silicon substrate was fabricated in a different step. Thus the molecular layer was deposited in a cavity and after the deposition of the top gate, the layer remains protected from environmental conditions for a long time. An additional advantage 114 N. Glezos

Fig. 3.13 (Left) SEM micrograph of the 50 nm-distant 2 lm overlap electrodes (top), top view of the electrodes with the monolayer (middle) and side view of the device showing also monolayer structure (right) Logarithmic representation of the current–voltage characteristics for the 150 K measurements (main ﬁgure) and the temperature dependence of the exponent and intercept (inset). Reprinted with permission from [75]. Copyright 2012, Elsevier

Fig. 3.14 Planar MIS and incorporated functional layers. a APTES molecules used for SiO2 surface chemical modification, b POM molecules self-organized via electrostatic forces on top of the APTES monolayer, and c IPA molecules electrostatically linked onto the POM structures, serve as capping/passivation layer. Reprinted with permission from [6]. Copyright 2014, AIP Publishing LLC of this structure is that the silicon substrate can be used as a reference in the various measurements, since its properties are well known thus a test structure not containing the molecular layer can be fabricated using the same processes as the active device (Fig. 3.14). The transport and charging properties of a POM nanolayer have been studied extensively using the above setup [6]. The basic mechanisms of vertical transport were identified utilizing capacitance-voltage and current–voltage measurements, as well as transient capacitance measurements under step voltage polarization. The conductivity of the POM layer increased via induction of gap states as a result of 3 Hybrid Memories Based on Redox Molecules 115 tailing of the electron-rich orbitals of defective POM structures within the SiO2 gap. Under gate injection, transport occurs through coupled processes of thermionic emission over the Schottky barrier induced by the HOMO-LUMO/Al Fermi level mismatch and interface states assisted Poole–Frenkel transport along with resonant tunneling through molecular states at relative high and intermediate electric fields. Hopping, coherent, and incoherent tunneling also occur in the low field regime. Each mechanism dominates the current in a different bias and/or temperature regime. When the POM film is charged this corresponds to (1–3 electrons per molecule). From structural analysis it was found that POMs aggregate in nanoislands, however, the electronic properties detected depend upon the characteristic LUMO states of the single POM molecules. The most important findings of this work are the results of transient I-V and C-V measurements. When the bias voltage is increased in as continuous way (ramp dV/dt = 0.05–0.30 V/s) due to the system capacitance it is possible to observe transient peaks which can be finally attributed to molecular levels. The peak distance measured and transformed in energy difference using the capacitances is 257 meV, while the energy difference between the HOMO and the first excited electronic state of tungstate determined by means of polarographic measurements is 243 meV. This means that most probably these transient current peaks do originate from POM charging and can be considered a fingerprint of its unoccupied energy states (Fig. 3.15). A second important result comes from the examination of transient capacitance measurements. The technique used to characterize the fabricated MIS structures in this section is based on the method of measuring the generation lifetime in MOS capacitors [39]. The capacitor is originally pulsed into deep depletion and then the evolution of the capacitance is measured over time. In the present case, this was used in order to test the influence of charging of the POMs when they are capped by an organic “insulating layer” of isopenthylamine (IPA). The result is that charge retention is improved by the addition of this layer, however a more efficient dielectric is required in order to obtain a non-volatile memory cell. The analysis

Fig. 3.15 Ramp rate current– voltage characteristics in forward sweep and range 0.05–0.30 V/s for sample AP indicating both Q1 and Q2 transient peak observed at 140 K. Reprinted with permission from [6]. Copyright 2014, AIP Publishing LLC 116 N. Glezos required the modification of the initial model with the inclusion of a molecular layer with its own time constants for charging/discharging. The quest for better retention led to the use of a dielectric [5]. A film of 25 nm Ta2O5 was used either as a covering layer of a tungsten polyoxometalate SAM or as a matrix. An additional film of the same thickness was deposited as a tapping layer. The charge trapping sites are located onto the metal framework of the electron-accepting molecular entities as well as on the molecule/oxide interfaces, which can immobilize negatively charged mobile oxygen vacancies. The memory characteristics of this nanocomposite were tested without the use of the tapping layer in order to extract the characteristics of the structure. The device with the polyoxometalates sandwiched between the two Ta2O5 has a larger memory window than the one containing the plain hybrid and comparable retention time, resulting in a memory window of 4.0 V for the write state and a retention time around 104 s without blocking medium. The distances of the molecular trapping centers from the gate and electronic coupling to the space charge region of the underlying Si substrate were identified as critical parameters for enhanced electron trapping. Implementing a numerical electrostatic model the electrical response of the cell was interpreted by examining the electrostatics of the trapping medium. There is work in progress to incorporate a blocking oxide which will increase the retention of the device. The advantage of using POMs as redox elements in non-volatile memory cells is better demonstrated when a complex molecule is selected. A Dawson-type 4− [W18O54(SeO3)2] compound which has a rich redox behavior due to both the reduction of the tungsten oxide cluster cage {W18O54} and the oxidation of the selenite double core was used to fabricate FET-type nanodevices [7]. The cluster cage can be reduced several times (up to 6 electrons) in a reversible way, while the selenium pair can be oxidized irreversibly to form a Se(V)–Se(V) bond. This means that with an appropriate selection of writing voltage pulses and optimized device geometries, memory cells with more than one state can be realized. In the present application they fabricated two different devices. The first one consists of a 4 nm Si nanowire channel with a 4 nm SiO2 layer insulator built on a Silicon On Insulator (SOI) substrate by e-beam lithography and etching. A side control gate is used to test the dependence of the transistor action upon charging of the POM layer. When a −20 V pulse is applied to the gate, electrons are injected into the molecules causing the shift of the threshold voltage required for the conduction of the channel by 1.2 V in the low voltage region. The fact that the molecules have a high density and are spread over the entire surface limits the speed of the device. The second device is also planar and consists of an interdigitated array of Pt electrodes distant 50 nm on a 30 nm SiO2/Si substrate with a back gate electrode. They used a +3 V gate bias and probed the system with +10 V writing pulses on the source-drain channel. By comparing to a similar device containing a reference POM molecule not including the Se–Se core, it was proved that the pulses permanently modified the Se–Se bond. A series of read/write measurements demonstrated that the device can be used as a write once/erase memory cell. The important conclusion of this work is that with a suitable arrangement it may be possible if the geometry is 3 Hybrid Memories Based on Redox Molecules 117 optimized to distinguish between a reversible write/erase action based on the tungsten–oxygen cage and an irreversible write/erase once action when the selenium core is modified. The same group presented a multiscale simulation study of a fully depleted silicon on insulator (FDSOI) non-volatile memory cell based on polyoxometalates inorganic molecular clusters used as a storage media embedded in the gate dielectric of flash cells [27]. They focused the threshold voltage variability introduced by random discrete dopants (random dopant fluctuation) and by fluctuations in the distribution of the POM molecules in the storage media (POM fluctuation). To highlight the advantages of the FDSOI POM flash cell, they provided a comparison with an equivalent cell based on conventional (BULK) transistors. The threshold voltage shift (VT) in the FDSOI structures is smaller in comparison with the BULK case. Second, the FDSOI flash cell has significantly smaller variation of VT in comparison with the BULK transistor, which indicates a significant potential for high yield at simplified writing scenarios in flash memory applications. However, it is important to point out that device performance depends also on the number of POMs and their organization in the gate. As an overall result nanowire transistors built on SOI are a far better template for molecular NVM than ordinary bulk FETs.

3.4 Conclusions and Outlook

This review focused on the efforts to fabricate capacitor-type hybrid silicon/molecular NMV based on the charging properties of redox molecules. The methodologies examined aim to the fabrication of devices using CMOS compatible processes. All leading-edge memory devices use charge storage. They include dynamic random-access memory (DRAM), flash memory based on a transistor floating gate and one transistor static RAM (similar to DRAM). For example the DRAM cell, which is one of the most efficient in terms of memory cell density, consists of one transistor and one capacitor and needs refreshing. A typical refreshing time is 100 ms. The quantity of the charge stored depends on the capacitor area and on the dielectric used. There is clear evidence that existing devices are unable to scale effectively. A lot of effort has been done to develop more efficient capacitors. Two of the most commonly employed strategies are (a) to form the capacitor as a deep trench with dielectric on the walls and (b) to use several layers. It is clear that both strategies add some complicated fabrication steps. Redox molecules have some inherent properties that make them suitable for charge storage. First of all charge storage depends on the properties of the molecule, not the substrate or the dielectric. In the test devices presented in this review, the charge stored in the molecular layer is at least one order of magnitude higher that a flash device with a SiO2 dielectric. An additional bonus is that the multiple redox levels allow the fabrication of multilevel memory cells operating at low voltages [7, 44, 47, 85]. Charge retention is a molecular property which does not depend on the substrate and even in the absence of a gate oxide can be in the order of minutes to 118 N. Glezos hours [6]. In order to implement molecules as charging layers in hybrid devices certain criteria have to be met [43]: (a) molecules have to be chemically stable, (b) They should withstand temperatures at least up to 400 °C, (c) the endurance of the memory cell should be >1015 cycles, (d) it must be possible to have read/write speeds <10 ns (e) charge retention should be >10 s, (f) charge density 10 lC/cm2 or higher, and (g) selective covalent bonding. From what has been presented in the review it can be deduced that (a,f,g) are achievable by many redox molecules and are easier to meet. Up to now retention and endurance tests have been performed for some limited cases. The temperature limit has been checked successfully only in the case of porphyrin [50]. In order to fabricate memory cells, capacitor structures are the first necessary step. Many of the criteria above can be tested with them. The existing successful examples indicate that the future devices of this kind most probably will involve a conductive channel such as a silicon nanowire covered by a molecular layer and a gate dielectric. This is more sensitive and efficient in handling charge [27]. The planar FET as indicated by preliminary studies suffers from leakages to the substrate from various paths [30]. In conclusion, redox molecules exhibit characteristics that could make them viable as memory devices. The last couple of years, test devices which meet many of the criteria for implementation in industrial products, have been presented. Future work should concentrate both in meeting all the criteria and in exploiting the rich properties of molecules to fabricate efficient multistate memory cells.

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S. Fakher, A. Sleiman, A. Ayesh, A. AL-Ghaferi, M.C. Petty, D. Zeze and Mohammed Mabrook

4.1 Introduction

The evolution of information and communication technologies in the last few years resulted in more demands for new data storage systems benefit from higher storage capacities. The new applications and devices in the market such as high definition TVs, iPADs, iPODs, Kindles, MP3s and smart phones operates through the storage of large amounts of data. Most of these devices are portable for everyday use for communication or entertainment purposes. The energy efficiency of the storage device is a very important parameter when considering hand-held devices, which need to keep running for a long time without the consumption of a lot of power. Depending on the energy consumption of the storage device, the memory devices are split into two types: volatile memory (VM) and non-volatile memory

S. Fakher Á A. Sleiman Á M. Mabrook (&) School of Electronic Engineering, Bangor University, Dean Street, Bangor LL57 1UT, UK e-mail: [email protected] A. Ayesh Department of Mathematics, Statistics and Physics, Qatar University, Doha, Qatar A. AL-Ghaferi Masdar Institute, Abu Dhabi, UAE M.C. Petty Á D. Zeze School of Engineering and Computing Sciences, Durham University, Durham DH1 3LE, UK S. Fakher Department of Physics, College of Education of Pure Sciences, Basrah University, Basrah, Iraq D. Zeze ITMO University, St Petersburg, Russia

(NVM) devices [1]. VM devices need constant supply of power to keep the data stored inside it, while NVM devices are able to keep the data stored even when the power is switched off. Thus NVM technology is a suitable candidate for the storage of large amounts of data when considering energy efficiency for hand-held and portable devices. One of the most familiar type of the NVM is the flash memory. Behind the tremendous success story of the flash memory is the NVM technology which depends on a metal–oxide–semiconductor field-effect transistor (MOSFET) embedded with a floating gate on which charges can be stored [2]. The success of the flash memory in the hand-held devices might be hindered by its limited scalability [3]. One of the major parameters that the memory technology should have is its ability to be scalable down to be compatible with highly desirable small sizes of the hand-held devices. On the other hand, the performance of electronic devices and circuits that are based on organic compounds witnessed significant development. In addition to other properties characterise organic materials compared with inorganic materials such as low-temperature processing and low-cost manufacture, the ability to deposit these materials from solution provides the basis for applications requiring mechanical flexibility, and large-area coverage. Recently, considerable interest has been focused on the development of new types of organic memory devices that can combine the properties of high speed, high density, and low power and cost with non-volatility. Organic memory devices based on bistable switching [4] charge storage in MIS [5], and organic thin film memory transistors (OTFMTs) [6–8] have been widely reported.

4.1.1 Organic Non-volatile Memory Devices

In recent years, organic non-volatile memory (ONVM) devices became the main drive towards future flexible, light-weight, and low-cost electronics [9–11]. As example for such NVM devices are flash memories, optical disks, and floppy disks devices. ONVM devices based on organic metal-insulator-semiconductor (OMIS) and organic thin-film transistor (OTFT) structures with floating gate are one of the key components to achieve those features due to their data storage and capability to integrate data processing. Particularly, nano-floating gate memories based on transistor structure proved to have fast switching speed, large memory window, and long retention time [12–14]. NVM consists of two main categories: (a) floating gate memory, which is differs from the conventional devices (such as MIS and TFTs) by adding thin layer of nanoparticles within the device insulator, and (b) charge trapping, where there is extra memory stack between the original dielectric and the metal gate. The later type holds for all integrated devices, i.e. transistors, capacitors, resistors and inductors. 4 Organic Floating Gate Memory Structures 125

4.1.1.1 Floating Gate Memories

It is worth mentioning that more than 90% of NVM production is based on floating gate principle [15]. Figure 4.1 shows the basic structure for non-volatile floating gate memory based on structures of (a) metal-insulator-semiconductor (MIS), and (b) thin-film transistor (TFT). These devices are modified MIS and TFTs, where the new structures have a semi-permanent charge storage as an internal gate which is called a ‘floating gate’, as shown in Fig. 4.1. Therefore, the internal gate acts as a memory cell, where the data stored in the form of accumulated electric charges dependence on the voltage that applied to the external gate. The external gate is the element which controls the flow the charge carriers to or from of the floating gate. (a) MIS-based memory structures MIS memory devices are capacitive type memories where the two states (ON and OFF) are defined by two capacitive values [16, 17]. The capacitance–voltage (C–V) characteristic of a simple p-type MIS structure is shown Fig. 4.2a; no hysteresis observed upon the double bias sweep. On the other hand, in the embedded MIS memory devices the C–V characteristics exhibit a clear hysteresis upon the double bias sweep (Fig. 4.2b). If we define the high accumulation capacitance by the ON state and the low deep-depletion capacitance by the OFF state, the hysteresis enables us to use the device as a memory device. As shown in Fig. 4.2b, if we apply a certain voltage (less than −7.5 V) we impose on the device to be in its high accumulation capacitance and thus perform the WRITE operation of the ON state. On the other hand, if we apply another voltage (higher than 10 V) we impose on the device to be in its low deep-depletion capacitance, thus perform the ERASE operation and have the device in its OFF state. At a certain range of voltages (between −7.5 and 10 V) the hysteresis in the C–V characteristics enabled both states, the ON and the OFF states, to coexist. An application of a voltage this range and reading the corresponding capacitance can sense in which state is the device without changing it. The sensing of the device state through reading the capacitance without changing it is the READ operation of the memory device. As such, the

Fig. 4.1 Basic ﬂoating gate memory devices based on a MIS, b TFT devices 126 S. Fakher et al.

(a) high accumulation capacitance C (F)

low deep-depletion capacitance

V (V)

(b) high accumulation capacitance - ON state C (F)

low deep-depletion capacitance - OFF state

-15 -10 -5 0 5 10 15 V (V) WRITE READ ERASE voltage voltage voltage

Fig. 4.2 a Typical C–V characteristics of a simple p-type MIS structure b Hysteresis in the C–V characteristics of an embedded MIS structure

WRITE-READ-ERAZE operations of a non-volatile memory device can be performed on an embedded MIS structure with hysteresis in its C–V characteristics. (b) TFT-based memory structures ONVM devices based on OTFTs are especially attractive to organic electronics, due to the possibility to read without destruction of their memory state (‘non-destructive read-out’). Furthermore, they can be fabricated in the same production line as OTFTs in any integrated circuit. In addition, integration with OTFTs settles the issue of the sneak current, which happens mostly in a passive crossbar array of 4 Organic Floating Gate Memory Structures 127

Fig. 4.3 The write and erase operations for a floating gate memory device based on TFTs, a for a p-type, and b for an n-type channel semiconductor (adapted from 12) memory elements [12, 18]. In the floating gate memory based on TFTs, the charges are stored in a metal layer which is completely surrounded by insulating layer. When a sufficient gate voltage, VG, is applied, charges are injected into the floating gate from the transistor channel, lead to a shift in the threshold voltage, VT. On the other hand, the discharge of the stored charges in the floating gate occurs when a reverse polarity VG is applied [19]. Among the qualities that should characterise memory cells is that can store the information autonomously of the external conditions and can changed from one state to the other (from “programmed, 0” to “erased, 1”), provided that the conductivity of the device can be changed in a non-destructive manner. In other words; the magnitude of change in threshold voltage, VT, from a high to low state, i.e. from programme “0” to erase “1” state, depends on the amount of stored or removed charges in or from the floating gate, respectively. The write and erase processes for this type of floating gate memory device can be presented by plotting the transfer characteristics of the transistor; the drain–source current (IDS) versus of gate–source voltage (VGS)at constant drain–source voltage (VDS) as shown in Fig. 4.3; for (a) p-type, and (b) n-type channel semiconductor. It is clear from Fig. 4.3 that the threshold voltage, VT, is shifted from the initial device state to the charged floating gate state. The shift in VT represents the memory window, which signifies the ability of memory devices to storage charges. Within this window, there are two different states of current; a high current (IDS 1) and a low current (IDS = 0), representing the logic data “1” for write and “0” for erase of the p-type channel memory [12] (Fig. 4.3a), respectively. The situation is reversed for the n-type channel memory as shown in Fig. 4.3b. The “read” process is proceeded by applying a VG that is between the values of programmed and erased VT and valuing the current flowing through the device.

4.1.1.2 Embedded MIM Structures

One of the simplest structures in electronics is the metal–insulator–metal stack, consists of a capacitor with the insulator acting as the dielectric layer (Fig. 4.4a). It 128 S. Fakher et al. is the building block of many electronic devices. Recently, embedded MIM structure was investigated as a two-dimentional (2D) novel, low-cost and high- speed NVMs [20–22]. This is done through doping the insulator of the embedded MIM structure with charge traps. The embedment of the charge traps will result in the resistive switching and the memory characteristics of the structure. Thus the structure of the embedded MIM memory devices is similar to that of the capacitor but having charges traps doped in the insulator and sandwiched between two metal electrodes as shown in Fig. 4.4b. Embedded organic MIM memory devices are resistive type memories where the two states (ON and OFF) are deﬁned by two resistive values. The memory behaviour of the devices is shown by the switching in the I–V characteristics between two resistive states; ON and OFF states. Typical I–V characteristics of embedded MIM memory devices exhibiting resistive switching (RS) behaviour upon application of opposite voltages are shown in Fig. 4.5. Upon sweeping the bias on the device and if the device is initially in the OFF state (stage 1 in Fig. 4.5), at a certain voltage (1.2 V in Fig. 4.5) the device current will increase abruptly and thus switch to ON state (stage 2 in Fig. 4.5), that voltage is called the writing voltage. In the example shown in Fig. 4.5, the switching to the ON state happens at 1.2 V. The device stays in the ON state as shown in stages 3, 4, 5 and 6 in Fig. 2.7. Upon sweeping in the opposite direction at a certain voltage the current will abruptly go back to its initial values (OFF state), this is called the erase voltage, which is −0. 8 V and occurs at stage 7 in Fig. 4.5. At any voltage between the writing and the erase voltages, the device can exhibit both states ON or OFF (depending on the previously applied voltage) and thus the range of voltages between the write and erase voltages may be used as the read voltage (between −0.8 and 1.2 V in Fig. 4.5). Usually the read voltage is chosen at the highest ON/OFF ratio to be able to easily distinguish between the different states. Different organic embedded MIM memory structures have been reported to exhibit RS upon the doping of different organic insulators with different types of charge traps. Examples of these organic embedded structures are PCBM blended in PMMA [23], FeS2 blended in P3HT [24], ZnO embedded in PMMA [25], Au-DT

(a) (b)

Fig. 4.4 The structure of an MIM device a without embedded charge traps and b the same structure with embedded charge traps inside its insulator 4 Organic Floating Gate Memory Structures 129

Fig. 4.5 Typical I–V characteristics of embedded 4 MIM memory devices high resistance - OFF state low resistance - ON state 3

5 2 9 10 0

Current (A) 8 1 7 6

-1 012 Impose Voltage (V) Impose OFF state- detect or READ ON state- ERASE WRITE

blended with P3HT, CuPC, Cr, Ag, Mg, Al embedded inside Alq3 and graphene embedded between two layers of PMMA [26]. In this investigation an organic embedded MIM structure using layer-by-layer deposited single-walled carbon nanotubes (SWCNTs) is used as charge trapped doped between two PMMA insulators. SWCNTs unlike other small organic molecules exhibits chemical inertness, stability and tunable band gap which make them favourable for such application [27, 28]. The chemical inertness and stability enhances SWCNTs lifetime inside the organic compound without changing the chemical or physical states [29]. The tunable bandgap of SWCNTs results in specifying its desired electrical characteristics, i.e. the ratio of the metallic to semiconducting SWCNTs embedded in the structure can be controlled [27]. A detailed description of the fabricated SWCNT-based MIM will be presented later.

4.2 Organic Metal-Insulator-Semiconductor (OMIS) Memory Structures

The experimental details and electrical characteristics for three types of OMIS memory structures are presented in this section. Thin layer of gold, gold nanoparticles (AuNPs) and single-walled carbon nanotubes (SWCNTs) were used as ﬂoating gates in these structures. Materials used in the fabrication of these devices are aluminium (Al) as the metal, poly(methyl methacrylate) (PMMA) as the insulating layer, pentacene as the semiconductor and gold (Au) is the contact metal. 130 S. Fakher et al.

4.2.1 OMIS Memory Devices with Thin Layer of Au as Floating Gate

The structure of the Al/PMMA/Au/PMMA/pentacene/Au MIS memory device is shown in Fig. 4.6. The device was fabricated by thermally evaporating 50 nm thickness of an Al gate electrode through a shadow mask onto a clean glass substrate. A 300 nm thick insulating layer was formed by spin coating of PMMA on top of the gate electrode and curing at 120 °C for 1 h. The floating gate was formed by evaporating about 10 nm thick gold layer. Prior to deposition of pentacene, another thin film of PMMA was deposited onto the floating gate. Pentacene was thermally evaporated at a pressure of 7.5 Â 10−7 mbar, at a rate of 0.03 nm s−1, through a shadow mask to a thickness of 50 nm. Following deposition of pentacene, top contacts were defined by thermal evaporation of 50 nm of Au through a shadow mask after about seven days of the pentacene evaporation. Figure 4.7 shows the C–V characteristics of the MIS memory (black solid line) and control (blue solid line) devices, with and without Au thin layer, respectively. The reference structure was Al/PMMA/pentacene/Au for the control device

Fig. 4.6 Schematic diagram of Al/PMMA/Au/PMMA/pentacene/Au memory structure

Fig. 4.7 C–V characteristics 70.3 75 at 1 MHz for the MIS memory (black solid line) and With Au thin layer 70.2 70 control (blue solid line) Control device structures [30] 70.1 22 V At 1MHz 65

70.0 60 69.9 Capacitance (pF) Capacitance (pF) 55 69.8 50 69.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 Voltage (V) 4 Organic Floating Gate Memory Structures 131

(without floating gate). All the measurements reported in this section were performed at 1 MHz and at a voltage scan rate of 100 m V s−1; the area of the top Au electrode was 9 Â 10−3 cm2. In each measurement, the scan started from accumulation voltage and swept toward deep depletion and back to accumulation. The C–V curve for the control device reveals the typical accumulation–depletion– inversion characteristics of an MIS structure based on p-type semiconductor, with a flat–band voltage of about −8 V, and the semiconductor becomes fully depleted at about 5 V as the measured capacitance remains constant at voltages above 5 V. A negligible (almost no) hysteresis is evident in the voltage sweep rate used for the control device. The addition of a thin layer of Au between two layers of insulators to form Al/PMMA/Au/PMMA/pentacene/Au structure produced very small change in the flat–band voltage, as shown in Fig. 4.7. Furthermore, on reversing the direction of the voltage scan, significant hysteresis was evident in the C–V curve with a large memory window (DV) of about 22 V. This was attributed to the presence of the Au thin layer and was almost certainly the result of charging and discharging. These results are consistent with our recent studies [30, 31] in which hysteresis in the C–V curves was attributed to the presence of an Au floating gate embedded within the insulating layer. The anticlockwise hysteresis after sweeping the accumulation region suggests that the charging and discharging of interface traps (floating gate) is located close to, or at, the PMMA/pentacene interface [32, 33]. We believe that, in accumulation, when a negative bias is applied to the metal gate electrode, holes are injected from the pentacene surface into the floating gate, charging up the Au layer. An increased negative voltage needs to be applied to the Au electrode to produce inversion of the pentacene surface (the C–V curve is shifted towards more negative voltages). The effect voltage sweeps on the memory window (DV) of this device is shown in Fig. 4.8. The memory window (shift in the flat– band voltage) increased linearly as the voltage sweep range increased, which is expected memory behaviour, and DV of about 7 V is achieved at sweep range ±10 and 22 V at ±40 V sweep voltage. This is indicative that the charges stored in the memory device increased as the applied voltage increased. From the value of capacitance C and conductance G in accumulation (G was 4.3 S), the parameters of the equivalent circuit in the accumulation region, which can be represented by a series of insulator capacitance CI and series resistance RS (representing the resistance of pentacene film and the contact resistance), were calculated by G G2 R ¼ ; C ¼ C 1 þ ð4:1Þ s G2 + w2C2 I w2C2

We found that CI = 70.24 pF and RS =23X. The amount of charges stored (Q) in the gold thin layer for this memory device can be estimated from Ci (accumulation capacitance per unit area) and the ﬂat–band voltage shift DVFB using Q = Ci DVFB. From the accumulation capacitance in Fig. 4.12, the calculated value −9 −2 of Ci is 7.8 Â 10 Fcm ; the number of charge carriers stored is approximately 1.07 Â 1012 cm−2 for the sweep range ±40 V. 132 S. Fakher et al.

Fig. 4.8 The memory 24 window (ﬂat band voltage 22 shift) versus the voltage sweep range for MIS memory 20 device with Au thin layer 18 ﬂoating gate 16 14 12

Memory window (V) 10 At 1MHz 8 MIS memory with Au thin layer 6 -10_10 -20_20 -30_30 -40_40 Voltage sweep (V)

4.2.2 OMIS Memory Devices with AuNPs as Floating Gate

In this device structure, a discrete floating gate consisting of gold nanoparticles (AuNPs) became a substitute for the Au thin-film floating gate. The structure of the MIS memory device is similar to that of Fig. 4.6. The device was fabricated under the same fabrication conditions and experimental steps as those used for fabricating the MIS memory device in Fig. 4.6, with AuNPs used as the floating gate instead of the gold layer. The AuNPs were deposited using the self-assembly technique. The process of preparing AuNPs solution involved adding 1 ml of 1% aqueous solution of gold chloride (HAuCl4Á3H2O) to 100 ml of deionised water under vigorous stirring. Then, 1 ml of 1% aqueous sodium citrate was added after 1 min. This was followed by adding 1 ml of 0.075% sodium borohydride (NaBH4) in 1% sodium citrate 1 min later. The next step was to stir the solution for a further 5 min and finally the solution was stored in the refrigerator at 4 °C. To deposit the Au nanoparticles, 3-aminopropyltriethoxysilane (APTES, C6H17NO3Si) was used as seed layer. In the first stage of deposition, the glass substrates were placed in a diluted solution of APTMS (1 ml of APTMS in 10 ml methanol) for 2–3 h. Then, the substrates were rinsed thoroughly with methanol, and immersed in the Au nanoparticles solution for 15 min and rinsed with water. Control device (without AuNPs) was also fabricated for comparison and to show the effects of the floating gate in the MIS memory device. It was the same control device as for the OMIS memory device based on Au thin layer, as both devices were fabricated at the same time. The C–V characteristics of the memory device (black solid line), after the addition of AuNPs within the insulating stack to form an Al/PMMA/AuNPs/ PMMA/pentacene/Au structure, and the control device (blue solid line), are shown in Fig. 4.9. The AuNPs floating gate layer produced a significant change in the 4 Organic Floating Gate Memory Structures 133

Fig. 4.9 C–V characteristics at 1 MHz for the MIS 33.5 75 memory (black solid line) and With Au NPs Contol device 70 control (blue solid line) 33.0 structure devices (with and At 1MHz without AuNPs ﬂoating gate) 32 V 65 [30] 32.5 60 32.0 Capacitance (pF) 55 Capacitance (pF)

31.5 50

-50 -40 -30 -20 -10 0 10 20 30 40 50 Voltage (V)

flat–band voltage. Furthermore, on reversing the direction of the voltage scan, clear hysteresis was observed. The clockwise direction of the hysteresis, with a shift of the flat–band voltage to a less negative voltage, indicates that electrons originating from the Al gate become trapped on the floating gate. In this case, in accumulation, the electrons are injected from the Al electrode to the Au nanoparticles, which later become negatively charged. The opposite effect occurs in inversion, and electrons are transferred to the Al electrode from the nanoparticles. This behaviour is in good agreement with other reports [32]. The hysteresis in the C–V curve shows a memory window DV of about 32 V (larger than the hysteresis reported for Au thin layer device). On the other hand, the lack of hysteresis with the control devices strongly indicates that charge storage in the Au or AuNPs layers is responsible for the hysteresis effects. The device shows similar linear increase of DV as the voltage sweep range increased, which resulted from the increase of charges stored as the applied voltage increased. DV of about 16 V at ±10 V was reached, and about 32 V at ±40 V sweep voltage. The calculated values for the insulator capacitance CI and series resistance RS were 33.4 pF and 12.5 X, respectively, where the conductance G was 8.01 S. The thicknesses of the insulator and semiconductor layers were estimated to be about 620 and 43 nm, respectively. The decrease in capacitance of the memory device as compared to the control devices was perhaps due to the additional material being added to the device such as the second layer of PMMA and AuNPs (floating gate). In practical, the structure cannot be treated as simply as the equivalent circuit of the control device [34]. However, the accumulation capacitance value indicates almost direct relationship between the capacitance and the thickness of the PMMA layers (two layers of 300 nm each for the memory device). This also indicates that the presence of AuNPs did not change the PMMA dielectric properties such as permittivity. The number of charge carriers stored in the Au nanoparticles Q was approximately 0.74 Â 1012 cm−2. 134 S. Fakher et al.

4.2.3 OMIS Memory Devices with SWCNTs as Floating Gate

The structure of MIS memory device based on SWCNTs as a floating gate, Al/PMMA/SWCNTs/PMMA/pentacene/Au, is similar to that of Fig. 4.6 with SWCNTs used as the floating gate instead of the gold layer. Single-walled carbon nanotubeswere purchased from Carbon Nanotechnologies Inc. Before their integration into the memory devices, SWCNTs were purified until the metal content was below 5 wt%. In the purification process of the nanotubes, SWCNTs were subjected to a thermal oxidation for 90 min at 300 °C, followed by stirring in a concentrated HCl bath overnight, before finally rinsing the nanotubes with deionized water until the pH of the solution is to that of deionized water and drying overnight at 120 °C. The SWCNTs were then subjected to a chemical cutting process using mild soni- cation in a mixture of H2SO4 and HNO3 (in the ratio 1:1) for 3 h at 120 °C. The SWCNTs were separated by centrifugation, washed several times with deionized water, and dried for 18 h. The cut SWCNTs were filtered using the 0.2 lm pore size polycarbonate membranes. At the end of the procedure SWCNTs of 200 nm or shorter were produced. The floating gate of SWCNTs was deposited using Layer-by-Layer (LbL) technique, a deposition technique based on a charge reversal to build up bi-layer assemblies of oppositely charged molecules [35]. Briefly, the deposition began by functionalizing the substrate by seeds layers, which facilitates the adhesion of SWCNTs onto the substrate. This was performed by the alternate immersion of the substrate in aqueous Poly(ethyleneimine) (PEI) (Mw = 25,000) (cationic, pH = 8.5) and Poly(acrylicacid) (PAA) (Mw = 4,000,000) (anionic, pH = 6.5) solutions, for 15 min each. The substrate was then repeatedly immersed in PEI solution for 15 min then SWCNTs solution (anionic, functionalized SWCNTs dispersed in Sodium dodecyl sulphate (SDS) solution) for 30 min. After each immersion, the substrate was rinsed with deionized water and dried with nitrogen. The final SWCNTs matrix consisted of three SWCNTs—PEI bilayers with thickness of 10–20 nm. The control device without SWCNTs was also fabricated. The C–V characteristics for SWCNTs-based MIS memory structure, and the control device (without SWCNTs), are shown in Fig. 4.10a. All the measurements reported in this work were performed at 100 kHz and at a voltage scan rate of 2Vs−1. The additional layers of SWCNTs within the insulating stack to form Al/PMMA/SWCNTs/PMMMA/pentacene/Au structure produced a very noticeable change in the flat–band voltage. Furthermore, on reversing the direction of the voltage scan, significant hysteresis and shift in the flat–band voltage were observed in the C–V curve with a large memory window DV * 35 V, which is indicative of the charge storage in the SWCNT layers. As shown in Fig. 4.10a, if a certain voltage (less than −30 V) is applied, the device will be in the high accumulation capacitance and thus perform the write operation of the ON state. On the other hand if a voltage of higher than 25 V is applied (deep depletion region) the erase operation will perform and the device turns to its OFF state. Applying a voltage 4 Organic Floating Gate Memory Structures 135 between −30 and 25 V represents the reading voltage range at which the capacitance value indicates if the device in the ON or OFF state without changing it. The memory devices exhibited larger shift in the flat-band voltage as the voltage sweep range increased as shown in Fig. 4.10b. The increase in memory window with increasing sweep voltage is expected as more charges are introduced and stored in the same period. However, when the voltage sweep reached ±40 V, the memory window slightly decreased due to the polarisation effect from the SWCNTs stack. The clockwise hysteresis after sweeping the accumulation was associated with electrons charging of floating gate or polarisation of the insulator. Furthermore, it is clearly seen in Fig. 4.10 that the hysteresis centred on approximately 0 V, which indicates that the devices may operate at lower voltages. The amount of charge stored in the carbon nanotubes Q can be estimated depending on −9 −2 the Ci, which gives a value of 8.2 Â 10 Fcm , and the DVFB was 35 V; the maximum number of charge carriers stored is approximately 1.7 Â 1012 cm−2. The clockwise direction of the hysteresis, with a shift of the flat–band voltage to a less negative voltage, indicates that electrons originating from the Al gate become trapped on the floating gate. In this case, in accumulation, electrons injected from the Al electrode to the SWCNTs layer, which later becomes negatively charged. The opposite effect occurs in inversion, and electrons are transferred to the Al electrode from the SWCNTs floating gate. In summary, organic flash memory devices with MIS structure using a thin film of Au layer, Au nanoparticles and single-walled carbon nanotubes as a floating gate, has been demonstrated. Negligible hysteresis was exhibited for control devices without floating gate, while memory devices exhibited clear hysteresis; this was indicative of the memory effect and charge storage in the memory devices. The clockwise hysteresis in the memory devices (except for the Au thin-film-based memories) was attributed to the charging and discharging of the electrons from the aluminium gate. Also the hysteresis was centred close to 0 V (in particular when SWCNTs are used as floating gate), which means that a lower operation voltage

Fig. 4.10 a C–V characteristics for the SWCNTs-based MIS memory (open circle and line) and control (blue solid line) devices and b The memory window (ﬂat–band voltage shift) versus voltage sweep range [36] 136 S. Fakher et al.

Table 4.1 The electrical parameters of the OMIS memory devices Structure Memory window (V) Voltage sweep (V) Q (cm−2) Thin Au layer 22 ±40 1.07 Â 1012 AuNPs 32 ±40 0.7 Â 1012 SWCNTs 35 ±30 1.8 Â 1012 could be used to charge the memory. A higher applied sweep voltage leads to a wider hysteresis and larger memory window. The memory window reached 35 V at ±30 V sweep range for the SWCNTs-based memory devices. However, all tested devices show a memory capacity in the range of 1012 cm−2. Table 4.1 summarise the electronic properties of the memory devices.

4.3 Organic Thin Film Memory Transistors (OTFMTs)

The fabrication and electrical behaviour of organic memory devices based on pentacene thin-film transistor (TFT) structures using poly(methyl methacrylate) (PMMA) as gate dielectric is studied. In a similar systematic approach as Sect. 4.2, three different types of floating gates were used: a thin-film of gold, a layer of self-assembled metallic gold nanoparticles (AuNPs), and five layers single-walled carbon nanotubes (SWCNT).

4.3.1 OTFMTs with Thin Layer of Au and AuNPs as Floating Gates

In this section, we study the properties of pentacene-based organic thin-film memory transistors (OTFMTs) using PMMA as the insulator. The charge storage elements investigated in this section are thermally evaporated thin film of gold and a layer of self-assembled metallic gold nanoparticles (AuNPs). Devices depicted in Fig. 4.11 were fabricated by thermally evaporating Al bottom gate electrode (50 nm thickness) through a shadow mask onto a clean glass substrate. A 300 nm thick insulating layer was formed by spin coating anisole solution of PMMA on top of the gate electrode and curing at 120 °C for 1 h. Two organic devices were fabricated with different floating gates. The floating gate for “device A” was formed by evaporating a 10 nm thick gold layer, while a monolayer of self-assembled AuNPs was used as the floating gate for “device B”. The preparation of the AuNP solution and the deposition method are described in Sect. 4.2. Before the deposition of pentacene, another thin film of PMMA was deposited onto the floating gate. Pentacene was thermally evaporated at a pressure of 7.5 Â 10−7 mbar and at a rate of 0.03 nm s−1 through a shadow mask to a 4 Organic Floating Gate Memory Structures 137

Fig. 4.11 Schematic diagrams of PMMA-based OTFMTs a with thin layer of gold (device A) and b gold nanoparticles (device B) as memory stack [30] thickness of 50 nm. Following the deposition of pentacene, source and drain contacts were defined by thermal evaporation of 50 nm of Au through a shadow mask. Control devices (OTFTs) without the floating gate were also fabricated. The uniform adsorption of gold nanoparticles was confirmed using AFM images as shown in Fig. 4.12. The average diameter of the synthesised AuNP was 56.01 ± 3.5 nm. The uniform adsorption of AuNPs in the whole area of the device on 300 nm of PMMA insulator layer was also observed. The thickness of the AuNPs film was estimated to be in the range of 20–30 nm, with few bundles of 40 nm thicknesses (shiny areas in Fig. 4.12). Figure 4.13a shows the output characteristics of the fabricated OTFT. The structure of the OTFT is Al/PMMA/pentacene/Au, which is used as the control device. The only difference compared to the memory devices is the absence of the thin gold or AuNP trapping layers in the gate dielectric layer. Otherwise, all of the

Fig. 4.12 AFM images of the self-assembled AuNPs deposited on 300 nm PMMA 138 S. Fakher et al.

Fig. 4.13 a Output (a) 7 characteristics and b transfer VGS = -50 V characteristics of the OTFT 6 fabricated as the control 5 VGS = -45 V device [37] “with kind A) 4 μ permission of the European ( 3 Physical Journal” DS

-I 2 1 0 VGS = 0 V 0102030405060 -VDS (V) (b) -4 0.008 10 10-5 1/2

0.006 )] VDS= -50 V -6 A ( (A) 10 1/2 DS

) 0.004 -7 DS 10 [-I (I 0.002 -8 10 Log 0.000 10-9 -100 -80 -60 -40 -20 0 20

VGS (V) device structures and the processing conditions are kept the same. Figure 4.13a shows the typical output characteristics of p-type OTFT devices with respect to the gate voltage from 0 to −50 V with steps of 5 V. The transfer characteristic of the organic transistor is shown in Fig. 4.13b for VDS = −50 V. The OTFT device exhibited almost no hysteresis in both characteristics. The calculated threshold voltage from the transfer characteristic is estimated to be −16 V. The transistor behaviour of the memory devices was investigated by measuring the output and transfer characteristics of the OTFMT at room temperature. Figures 4.14 and 4.15 show the characteristics of OTFMTs for devices A and B, respectively, as well as the OTFT control devices associated with each memory structure. Both forward and reverse scans are shown in each measurement, at a voltage scan rate of 1 V s−1. The output characteristics of the memory and control devices exhibited good linear behaviour at low VDS values as well as good saturation region at high VDS (Figs. 4.14a and 4.15a). The transfer characteristics of the memory device (initial curve) were also obtained before programming pulses (write/erase operation) were applied, as shown in Figs. 4.14b and 4.15b. The VGS values for the output characteristics were at −50 V for device A with channel length L = 140 lmand−25 V for device B with L = 195 lm, with channel width W = 1000 lm for both devices. For the transfer characteristics, the VDS values were set at −50 V for device A and −25 V for device B. The ﬁeld-effect mobility l of the devices are calculated using Eq. (4.2). 4 Organic Floating Gate Memory Structures 139

Fig. 4.14 a Output and (a) 0.12 7 b transfer characteristics of 0.10 OTFMT of device A 0.08 6 ) 0.06 5 ) A A μ μ ( 0.04 V = -50V GS 4 (

DS 0.02 3 DS - I 0.00 - I OTFMT (device A) -0.02 2 Control OTFT -0.04 1 -0.06 0 0 10 20 30 40 50 60 -VDS (V) (b) x 10 -3 x 10 -3

2.0 8.0

1/2 OTFMT (device A) )

A 1.5 6.0 1/2 ( Control OTFT ) A ( 1/2 ) 1.0 4.0 1/2 ) DS 22 V V = -50 V

I DS ( DS I

0.5 2.0 (

0.0 0.0

-100 -80 -60 -40 -20 0 VGS (V)

lWC I ¼ i ðV À V Þ2 ð4:2Þ DS 2L GS T where Ci is the insulator capacitance per unit area and VT is the threshold voltage. The threshold voltage represents the value of the VGS at which the transistor is 1/2 turned on and can be determined from the intercept of the plot of (IDS) versus VGS. Table 4.2 summarises the electrical parameters for devices A and B, where the threshold voltages were measured for both forward and reverse directions (VTF and VTR, respectively). According to these results, the Au nanoparticle-based OTFMT structure (device B) produces an improved memory transistor performance than Au thin layer-based OTFMT structure (device A). It is also important to notice that device B operates at lower VDS and VGS (−25 V) values. On the other hand, it is very clear from Figs. 4.14 and 4.15 that the addition of the Au ﬂoating gate produces a clear hysteresis in the transfer characteristics of the transistor; similar behaviour was observed for the output characteristics. It is almost certainly the result of charging and discharging with the applied voltages. It is important to note that there is almost no hysteresis in the control transistor as the forward and reverse scans produced superimposed characteristics. The 140 S. Fakher et al.

Fig. 4.15 a Output and (a) b transfer characteristics of 25 OTFMT(Device B) 6 OTFMT of device B Control OTFT 20 5 4 ) A)

A 15 μ μ ( ( V = -25V 3 GS 30 V

10 DS DS 2 - I - I 5 1

0 0

0 102030405060

-VDS (V) (b) x 10-3 x 10-3 10 2.0 OTFMT(Device B) 8 Control OTFT 1/2

) 1.5 1/2 ) A

( 6 A ( 1/2

) 1.0 1/2 4 ) V = -25V DS DS I DS ( I 0.5 2 (

0.0 0

-60 -50 -40 -30 -20 -10 0 10 VGS (V)

Table 4.2 Electrical parameters of devices A and B Structure Mobility Threshold On/Off Memory Charge capacity, (cm2/Vs) voltage (V) ratio window (V) Q (cm−2)

VTF VTR Device A 0.04 −20 −42 2.3 Â 103 22 2.63 Â 1012 Device B 0.18 15 −10 0.3 Â 103 25 1.19 Â 1012 counterclockwise direction of the hysteresis in the transfer characteristics indicates a clear hole charging, and the floating gate can become charged from the semiconductor surface. This is in agreement with our C–V characteristics of the MIS structures, as shown in Sect. 4.2. When a high enough negative voltage is applied to the gate electrode, holes are injected from the semiconducting layer into the Au floating gate (through the top insulating layer), charging up the Au floating gate and programming the memory device. On the other hand, when a high enough positive voltage is applied to the gate electrode, holes are ejected from the floating gate through the pentacene layer (erase process). To test the memory behaviour of 4 Organic Floating Gate Memory Structures 141 the OTFMTs, successive positive and negative voltage pulses were applied on the gate electrode with VDS maintained at 0 V. The magnitude of the voltage pulse was increased for each step, but the pulse duration was kept constant at 2 s. At each stage, and after the application of the voltage pulse, the transfer characteristics of the device were measured to calculate the shift in the threshold voltage compared to the unstressed device. Figure 4.16 shows the effect of negative and positive pulses applied to the gate electrode for Device A. A clear shift to higher negative threshold voltages is observed for the application of negative pulses (write state) as shown in Fig. 4.16a, whereas, positive shifts of threshold voltages is observed due to the application of positive pulses (erase) as shown in Fig. 4.16b. These shifts are clearly presented in Fig. 4.17 for pulses of −3 and +3 V for write and erase states, respectively, of Device A. Similar behaviours are also observed for the programming of Device B. Both devices shown repeatable and reproducible memory effects as measurements were conducted on several devices based on the same structures as devices A and B. Figure 4.18a shows the dependence of threshold voltage shift on the height of the applied voltage pulses for both Devices A and B. The devices in Fig. 4.18a exhibit a clear memory window for voltage pulses over 1 V. Figure 4.18b shows the effect of programming pulses on the value of IDS when a voltage was applied to the gate electrode. The write state was achieve by a voltage pulse of −5Vfor2s while for the erase state a voltage pulse of 5 V was used with the same period of time. When a gate voltage of 10 V was applied, it was possible to distinguish if the devices were in the write or erase states from the value of the drain–source current, evident from Fig. 4.18b.

Fig. 4.16 The effect of (a) x 10 -3 a negative and b positive 2.0 pulses on transfer Initial curve V = -50 V After -1 V puls 1/2 DS characteristics of Device A ) 1.5 After -2 V pulse

A After -3 V pulse ( 1.0 After -4 V pulse

1/2 After -5 V pulse ) After -6 V pulse

DS 0.5 I ( 0.0 VT -100 -80 -60 -40 -20 VGS (V) (b) x 10 -3 2.5 Initial curve 2.0 After +1 V puls

1/2 V = -50 V After +2 V pulse ) DS After +3 V pulse A

( 1.5 After +4 V pulse After +5 V pulse 1/2 ) 1.0 After +6 V pulse DS I

( 0.5

0.0 VT -100 -80 -60 -40 -20 VGS (V) 142 S. Fakher et al.

Fig. 4.17 Transfer x 10-3 characteristics of the OTFMT 2.5 of Device A after the application of positive and 2.0 Before Programming negative pulses of 3 V for 2 s V = -50 V DS After -3 V Pulse After +3 V Pulse 1/2 ) 1.5 A ( 1/2

) 2s 1.0 DS I ( +3 V Pulse 0.5 2s 0.0 -3 V Pulse write erase -100 -80 -60 -40 -20 VGS (V)

The non-volatile behaviour of the OTFMTs was also investigated by monitoring IDS after the application of voltage pulses for write and erase states. IDS was periodically measured at regular time intervals with a ﬁxed reading voltage of 10 V. Figure 4.19 shows the data retention capability as a function of time for devices A and B in the write/erase states under ambient condition at room temperature. In fact, the memory behaviour was retained for more than 12 months in the case of OTFMTs stored under vacuum.

Fig. 4.18 Programming 30 (a) Device A,V = -50 V 25 DS characteristics of OTFMT. Device B,V = -25 V 20 DS a The effect of the 15 programming voltage 10 Write

(2 s pulses) on the threshold (V) 5 T voltage shift, DV . b Write V 0 T Δ -5 Erase and erase processes by -10 applying a negative and -15 positive pulse voltage, -20 respectively [30] 123 456 Programming Voltage (V)

(b) 10-6 Erase 10-7 ) A ( 10-8 DS Write I 10-9 Device A 10-10 Device B 10 15 20 25 30 35 VGS (V) 4 Organic Floating Gate Memory Structures 143

Fig. 4.19 Charge retention 10-5 characteristics of the Device A OTFMTs Devices A and B 10-6 Device B [30]

-7 ) 10 A ( Erase DS 10-8 I

10-9 Write 10-10 0 100 200 300 400 500 Time (min)

When negative pulses (2 s pulses for devices A and B) are applied to the gate electrode (write state), it is believed that the holes are transferred from the channel to the floating gate through the pentacene semiconductor. This charging process generates an internal electric field with a direction opposite to that of the applied negative voltage. As a result, a higher negative gate voltage is required to turn on the transistor, leading to a shift in the threshold voltage to a more negative value compared to the unstressed device. Correspondingly, when a positive pulse is applied to the gate electrode (erase state), holes stored in the floating gate are ejected into the transistor channel. A smaller negative gate voltage is then needed to turn on the transistor. This behaviour is evident in Fig. 4.18a as the shift in threshold voltage increases with increase in the applied voltage pulses. The characteristics in Fig. 4.18a exhibit a clear memory window for voltage pulses as low as 1 V only. The amount of charge stored in the floating gate Q can be estimated from Q = Ci DVT [37–39] where Ci was measured using a simple pentacene/PMMA MIS structure. This gives a value of 7.8 Â 10−9 and 3.7 Â 10−9 Fcm−2 for devices A and B, respectively; thus, the number of charge carriers stored is approximately 1.07 Â 1012 and 0.7 Â 1012 cm−2, respectively, at a programming voltage of 6 V.

4.3.2 OTFMTs with SWCNTs as Floating Gate

In this section, we report on the performance of non-volatile memory effects of SWCNT-based ﬁeld-effect transistors structure. Similar to the previous devices, PMMA is used as the dielectric layer, and pentacene as the active layer in this device structure. Layer-by-Layer assembled composites were used for deposition of carbon nanotube as the charge storage layer. The transistor behaviour of the memory devices was investigated by measuring the output and transfer characteristics of the OTFMT at room temperature. Figure 4.20 shows the output characteristic of SWCNTs-based OTFMT and the OTFT control device which is associated with memory structure. Both forward and reverse scans are shown in 144 S. Fakher et al.

−1 each measurement at a voltage scan rate of 2 Vs and with a VGS value of −30 V. The output characteristics of the memory and control devices exhibited good linear behaviour at low VDS values as well as good saturation region at high VDS. It is also evident from Fig. 4.20 the memory transistor shows negligible gate leakage current indicating good transistor behaviour. Figure 4.20b shows the transfer characteristics of the memory device (initial curve) as well as control device, the VDS value was set at −25 V. The channel length was L = 147 lm, and the channel width was W = 1000 lm for this memory device. The effect of addition SWCNTs floating gate produces a clear hysteresis in both the output and the transfer characteristics of the transistor, as shown in Fig. 4.20. The hysteresis is the result of the charging and discharging of the SWCNTs floating gate with the appropriate applied voltages; when a high enough negative bias is applied to the gate electrode, holes are injected from the semiconducting layer into the SWCNTs floating gate (through the top insulating layer), charging up the SWCNTs floating gate and programming the memory device. On the other hand, when a high enough positive voltage is applied to the gate electrode, holes are ejected from the floating gate through the pentacene layer (erase process). Large memory windows were clearly evident in Fig. 4.20; a memory window of DV = 35 V was observed in the output characteristics and a memory window of DV = 15 V was observed in the transfer characteristics. Such large memory window for SWCNTs-TFMT devices is significantly dependent on dVG/dt, which is the sweeping rate of the gate voltage due to the charge storage effect [40]. Clockwise hysteresis loop is observed for the output characteristic, whilst a counterclockwise hysteresis loop is observed for the transfer characteristic when the gate voltage sweeps from positive to negative voltages. Such hysteresis loops are in satisfactory agreement with our recent studies for gold thin layer [37] and for gold nanoparticles [5]. The calculated value of the field-effect mobility l for the control device was 0.212 cm2 V−1 s−1, with a threshold voltage of −18 V and an on/off current ratio of 2.9 Â 103. Besides of the large memory window exhibited in SWCNTs-OTFMT devices, a relatively good field-effect mobility; µ = 0.319 cm2 V−1 s−1 has been observed. The threshold voltages were estimated of about −22 and −45 V for

Fig. 4.20 a The output and b transfer characteristics of the OTFMT device with and without the SWCNTs floating gate [36] 4 Organic Floating Gate Memory Structures 145 forward and reverse directions, respectively, and the on/off current ratio was 0.23 Â 103. The amount of charges stored in the carbon nanotubes (Q) can be −9 −2 estimated depending on the Ci (10.53 Â 10 Fcm ) and DVT (35 V). The number of charge carriers stored was calculated to be in the range of 1.7 Â 1012 cm−2. The memory operation was again characterised by measuring the threshold voltage shift after charging the floating gate, as successive positive and negative voltage pulses were applied on the gate electrode with VDS maintained at 0 V. The magnitude of the voltage pulse was increased for each step but the pulse duration was kept at 1 s. Figure 4.21a shows the programming pulses of SWCNT-based OTFMTs, where the threshold voltage shift as a result of the applied negative and positive pulses. The write state happens when negative pulses (1 s pulses here) are applied to the gate electrode leading to threshold voltage shift to more negative values compared to the unstressed device, while the application of a positive pulse to the gate electrode leads the transfer characteristic to shift rigidly toward positive gate voltages, erase state. These behaviours are evident in Fig. 4.21a as the shift in threshold voltage increases with increase in the applied voltage pulses. Clear memory behaviour in terms of writing and erasing for voltage pulses as low as 2 V, are shown in Fig. 4.21a. It is also important to report that the mobility of memory transistors did not vary due to the applied write or arase pulses as mobilities of 0.3–0.33 cm2 V−1 s−1 were estimated for all conditions. The non-volatile behaviour, and for the purpose of measuring the endurance properties, of the OTFMTs was investigated by monitoring the drain–source current after the application of voltage pulses for write and erase states. The write/erase operations were repeated with continuous application of bias pulses of ±20 V for 1 s. After a certain number of write/erase cycles the reading process was carried out to confirm the change in the drain current. Figure 4.21b shows the test pulse sequence for endurance measurements of the SWCNT-based TFMTs device at room temperature. As shown in Fig. 4.21b, there are three write/erase cycles in the first period with an initial decay of 60 s for each cycle, and then the drain current is measured by an applied reading bias of −10 V. After a retention time of one hour, the write/erase operations were repeated (two cycles, as shown in Fig. 4.21b) and were followed with a reading process. This process was repeated for over 200 cycles and the IDS value of the memory transistor was measured accordingly. It is observed that the current remains almost constant in both writing and erase states as shown in Fig. 4.21c. The average current recorded for the write and erase states are 7.12 Â 10−11 A and 2.5 Â 10−8 A, respectively. The non-volatile behaviour of the OTFMT was also investigated by monitoring IDS after the application of voltage pulses for write and erase states. IDS was periodically measured at regular time intervals with a fixed reading voltage of 10 V. Figure 4.22 shows the data retention capability as a function of time for SWCNTs-based OTFMT in the write/erase states under ambient condition at room temperature. In fact, the memory behaviour was retained for more than 12 months in the case of OTFMTs stored under vacuum. 146 S. Fakher et al.

Fig. 4.21 a Programming characteristics, b pulses sequence and c retention current for the SWCNT-based OTFMT [36]

Fig. 4.22 Charge retention capability as a function of retention time for the SWCNT-based OTFMT [36] 4 Organic Floating Gate Memory Structures 147

Figure 4.23 represent the relative energy diagrams for the materials used in the fabrication of the device, where the work functions for Al, Au, and SWCNTs are 4.3, 5.1 and 4.8 eV, respectively. The highest occupied molecular orbital (HOMO) and the lowest-unoccupied molecular orbital (LUMO) levels of pentacene are −5 and −3 eV, respectively, while the energy band gap of PMMA is 5.7 eV with a work function of 5.1 eV [41]. The charging process (writing) is shown in Fig. 4.23 where under a negative bias applied to the gate electrode, holes emitted from the highest occupied molecular orbital (HOMO) level are injected through the PMMA and captured by the SWCNTs floating gate. The presence of holes in the insulating stack of the transistor leads to higher negative voltage required to activate the transistor (higher negative threshold voltage). Based on the experimental results and the energy band diagram in Fig. 4.23, we believed that transfer of holes from the pentacene to SWCNTs floating gate occurs by tunnelling through the PMMA. The charge transfer may be supported by the localised defects present in the SWCNTs floating gate. Also, charge carriers can cross the PMMA energy barrier as the HOMO level of pentacene and the work function of SWCNTs are very close (as shown in Fig. 4.23). This is characterised by a large negative shift of threshold voltage of the transfer characteristics during the reverse sweep. In turn, erasing occurs when a positive bias is applied to the gate electrode. In summary, the electrical properties of the organic TFMTs could be improved by the use of Au nanoparticles layer as the floating gate compared with that of an Au thin film. Using appropriate negative or positive voltages, the floating gate may be charged and discharged, resulting in a clear shift in the threshold voltage of the transistors. The charge trapping effect is attributed to the presence of the floating gate, as carriers are injected from the pentacene surface through the top insulating layer. Negative and positive pulses of 1 V resulted in clear write and erase states in both devices. For OTFMTs devices using SWCNTs as a floating gate, large memory windows (DV > 35 V) as well as high carrier mobility (µ = 0.319 cm2 V−1 s−1) are demonstrated. The electrical properties of the organic TFMTs using SWCNTs as the floating shows much improved parameters compared with that of Au floating gate based OTFMTs devices. Additionally, these organic memory devices exhibited good programmable memory characteristics with respect to the write/erase

Fig. 4.23 Energy band diagram of the SWCNT-based memory transistor [36] 148 S. Fakher et al. operations, leading to a large threshold voltage shifts. The data retention and endurance measurements conﬁrmed that OTFMTs exhibited mechanical stability as well as good electrical reliability. Furthermore these data retention and endurance measurements conﬁrmed the non-volatile memory properties for our devices in this study.

4.4 SWCNTs as Charge Traps in MIM Memory Structure

Significant research has been devoted to developing organic bistable devices (OBDs) in the metal-embedded insulator-metal (MIM) structure utilising inorganic nanoparticles embedded inside an organic insulator to form the charge storage stack [42–44]. In this section, we present the fabrication and characterization of OBDs based on SWCNTs as charge storage nodes embedded between two PMMA insulating layers to form the active layer of the organic bistable memory devices. SWCNTs were deposited using the LbL technique, which ensures that the SWCNTs form a “thin-film” matrix. This technique will also ensure that the SWCNTs are confined between the bottom and top PMMA layers, allowing for switching behaviour and the out–of-plane charge transport within the memory structure. The position of the charge traps in the middle of the insulating layer is believed to enhance the performance of the OBDs in terms of stability and retention [45]. A 100 nm thick aluminium (Al) bottom electrode was thermally evaporated on a clean glass substrate. PMMA (20 wt% in chlorobenzene) was then spun coated to a thickness of 40 nm (6000 rpm for 50 s) and baked for 75 min at 120 °C. SWCNTs were deposited using LbL technique detailed earlier in Sect. 4.2. A second layer of 40 nm PMMA was then deposited on the device to complete the SWCNTs encapsulation. Finally, the top Al electrode was thermally evaporated to finalise the fabrication of the device in a crossbar structure, with a surface area of 1 mm2. A schematic diagram of the fabricated structure is shown in Fig. 4.24a. The structure ensures that the memory device benefit from the SWCNTs as a middle trap layer confined between two “thick” potential barriers. The band model depicted in Fig. 4.24b is used to explain the switching behaviour in the I–V characteristics and carriers transport in the structure, as will be discussed later in this section. Figure 4.25 shows the I–V characteristics for an Al/PMMA/SWCNTs/ PMMA/Al memory device in the linear scale (Fig. 4.25a) and in the logarithmic scale (Fig. 4.25b). The voltage applied to the device was split into two consecutive parts, a positive scan starting from 0 V towards 5 V and then back to 0 V, then a negative scan starting at 0 V towards −2.1 V and then back to 0 V. The I–V characteristics for the devices show clear electrical hysteresis behaviour. Initially the device was in the low-conductivity state (OFF state) during the positive scan. The conductivity of the device switches from its low conductivity to high conductivity (ON state) when the voltage exceeded a threshold voltage of 4.4 V, which represents the writing voltage. The high-conductivity state was sustained even when 4 Organic Floating Gate Memory Structures 149

Fig. 4.24 a Schematic diagram and b band diagram of the Al/PMMA/SWCNTs/PMMA/Al memories [22]

(a) (b)

-4 80.0μ 10 4 3 10-5 60.0μ -6 5 2 3 10 40.0μ -7 10

-8 20.0μ 2 10

Current (A) 6 10-9

Current (nA) 1 0.0 10-10 6 1 -20.0μ 5 4 10-11 10-12 -3 -2 -1 0 1 2 3 4 5 -2 -1 0 1 2 3 4 5 Voltage (V) Voltage (V)

Fig. 4.25 I-V characteristics a in linear and b in log scale of the MIM memories [22] the power was turned off (after sweeping back to 0 V) as shown in Fig. 4.25.On the other hand, the negative scan causes the devices to switch from the ON to the OFF state; the transition to the OFF state was achieved by applying a reverse voltage of −2.1 V which represents the erase voltage. The maximum current ratio between the ON and OFF states for the tested devices is about 2 Â 105 using a low reading voltage of 1 V. The stability and retention characteristics of the bistable memory devices were tested by monitoring the current in both ON and OFF states at a constant applied reading voltage of 3.5 V for more than 1000 s. The device was switched ON by 150 S. Fakher et al.

Fig. 4.26 Retention of the ON and OFF states of the fabricated memories [22]

applying a 1 s pulse of 4.5 V, then the retention of the ON state was recorded. The retention ability of the OFF state was also observed after switching the device back to the OFF state using a 1 s pulse of −2.1 V. The current–time characteristics of the ON and OFF states are shown in Fig. 4.26, at a reading voltage of 3.5 V. The current maintained the original value of 40 lA in the ON state, and 20 nA in the OFF state (representing a 2 Â 103 ON/OFF ratio at reading voltage 3.5 V). A systematic analysis of all the devices produced during this investigation showed that voltages of 4.4 ± 0.2 and −2.1 ± 0.2 V were sufficient to turn the device to its ON and OFF states, respectively. In addition, the bistable behaviours of the devices were observed when the voltage sweep was repeated several times. The devices show reproducible memory behaviour with a small shift to slightly lower voltages in the ON voltage after more than 25 measurements cycles. This kind of switching from ON to OFF and from OFF to ON states at different low voltages and the reliable retention characteristics make these devices potential candidates for applications in organic non-volatile memory and in particular, where low power operation is a necessity. In order to explain the memory behaviour and the carrier transport mechanism of the fabricated devices, the I–V characteristics in Fig. 4.25 were fitted using different conduction models (e.g. Poole-Frenkel, space charge limited conduction, Thermionic emission and Fowler-Nordheim Tunneling effect). The space charge limited conduction (SCLC) model showed the best fit to the data and thus was used to understand the carriers’ behaviour in both the ON and OFF states of the devices. The current equation of the SCLC model is expressed by [17]

a ISCLC ¼ b V ð4:3Þ where b is a constant and a is the slope of the linear ﬁtting of ln(I) versus ln(V). Figure 4.27 shows the ln(I) versus ln(V) plot for the data in Fig. 4.25. The out-of-plane conduction mechanisms in the OFF and ON states, in both the positive (Fig. 4.27a) and negative (Fig. 4.27b) voltage scans were investigated. The data were ﬁtted for the ON state and for the OFF state (before and after switching the device to the ON state). As shown in Fig. 4.27a, the initial OFF state of the device 4 Organic Floating Gate Memory Structures 151

Fig. 4.27 Ln-ln plots for the data in Fig. 4.25 and ﬁtting curves for the SCLC conduction mechanism during a positive and b negative voltage sweeps. Inset Current versus square root of voltage at voltages below 2.5 V

in the positive scan (i.e. before switching to the ON state) can be divided into two regions, which contributes to two different linear fitting behaviours. At voltages below 2.5 V in the initial OFF state, the slope of the fitting line is 1.33, which lies between the Ohmic conduction (a = 1) and the ideal case of SCLC (a = 2) and cannot really help understand the conduction mechanism. But the same region of the initial OFF state (i.e. below 2.5 V) shows an almost ideal fit to the thermionic emission model at which ln(I) versus V1/2 exhibits a linear behaviour as shown in the inset of Fig. 4.27a. This behaviour shows that at low voltages electrons were accumulating at the barrier formed due to the potential profile between Al and PMMA and a thermionic conduction is taking place. This is consistent with similar behaviour at similar potentials profiles in organic memory devices at low voltages [46]. As the voltage exceeds 2.5 V, the slope of the SCLC linear fitting increased gradually to 6.12 consistent with an increase in the number of charge carriers captured by the SWCNTs inside the PMMA. This high slope in the linear fitting of the SCLC is attributed to a conduction mechanism where the carriers are filling empty traps (SWCNTs) inside the out-of-plane medium (PMMA), the so-called trap-limited-SCLC [47]. After the transition to the ON state at 4.4 V, the I–V characteristics follow ohmic behaviour: linear fitting of ln(I) versus ln(V) shows a slope equals 1 where the current is proportional to the applied voltage. Furthermore, this behaviour extended into the ON state in the negative voltage scan; the slope of the linear fitting again is 1 as 152 S. Fakher et al. shown in Fig. 4.27b. There are several models been proposed to explain the switching in conductivity for such structures. Lauters et al. [48] suggested that the conduction mechanism in the ON state is due to the formation of a metallic filament within the PMMA stack at the transition state from OFF to ON states. According to this model, a local conducting path with very low resistance is generated at high voltages allowing charges to be transported easily within the device. However, as only one-third of SWCNTs are metallic while the other two-thirds are semiconducting, it is very difficult to form a filament across the device structure. Therefore, we believe that the switching behaviour is due to trapping and detrapping of electrons in the SWCNTs layer. Thus, in the ON state the carrier conduction in the devices follows an ohmic law which suggests that the SWCNTs where totally filled with injected electrons and the conduction mechanism follow a filled-traps SCLC [24]. As electron capturing inside the SWCNTs layer no longer exists, as it is totally filled with electrons, the electrons flow is free from the influence of traps and electrons are able to reach the counter electrode much easier and thus the device conductivity switches to a high-conductance state (ON state). When the device was turned OFF at −2.1 V, the electrons were detrapped from the SWCNTs. A linear fit with a slope of 2.65 for the SCLC model is observed (negative scan in Fig. 4.27b). Similar to the OFF state in the positive scan, the current in this voltage range is attributed to the empty-traps SCLC mechanism, where the electrons being captured by the SWCNTs traps inside the PMMA rather than reaching the other electrode which explains the low-conductivity behaviour of the devices. Simplified band diagrams of the conduction mechanism of the devices in the OFF and ON states is depicted in Fig. 4.28. In addition to the fitting of the I–V characteristics to the proposed conduction models in the ON and OFF states, we are able to extract the density of traps inside the device at the trap-filled voltage (VTFL); i.e. the switching voltage at which the traps are totally filled with electrons and the transition happens to the filled-traps conduction (4.4 V in our devices). The density of traps (Nt), is given by [49]

3 ee V N ¼ 0 TFL ð4:4Þ t 2 qd2 using the dielectric constant of the PMMA to be between 2.89 and 3.66 [33], the density of SWCNTs charge traps inside the device was estimated to be between 2.19 Â 1017 and 2.78 Â 1017 cm−3. In summary, SWCNTs-based MIM memory devices exhibit an electrical bistability and non-volatile memory characteristics in terms of switching between ON and OFF states due to the application of positive and negative voltages, respectively. The retention characteristics showed two stable and distinct conduction states. The fabricated memory devices operate below 5 V in terms of writing, reading, and erasing and have an ON/OFF ratio of *2 Â 105 at a 1 V reading voltage. The electrical bistability of the devices was attributed to the trapping and detrapping of electrons by SWCNTs. 4 Organic Floating Gate Memory Structures 153

Fig. 4.28 A simpliﬁed schematic of the band diagram and conduction mechanism of the devices in a the OFF state (traps empty) and b the ON state (traps ﬁlled) [22]

Acknowledgments This work is adapted from: Sundes Juma Fakher, “Advanced Study of Pentacene-Based Organic Memory Structures”, Ph.D. Thesis, School of Electronic Engineering, Bangor University, Bangor, UK, 2014. Adam Ahmad Sleiman, “Two terminal organic nonvolatile memory devices”, Ph.D. Thesis, School of Electronic Engineering, Bangor University, Bangor, UK, 2014.

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E. Verrelli and D. Tsoukalas

5.1 Introduction

Nanoparticles (NPs) are of great scientiﬁc interest as they are effectively a bridge between bulk materials and atomic or molecular structures. The interest in NPs with typical sizes in the range 1–100 nm is due to the fact that the magnetic, optical, and electronic behavior of bulk materials can be modiﬁed when they approach the nanometer scale. In the last 20 years, research has focused on understanding the origin of these new properties. There are two major phenomena that are responsible for these differences [1–3]. Firstly, some interesting and sometimes unexpected properties of NPs are largely due to the large surface area of the material, which dominates the contributions made by the small bulk of the material. As the size of a crystal is reduced, the number of atoms at the surface of the crystal compared to the number of atoms in the crystal itself, increases. For example, a 4-nm-diameter CdS nanoparticle has about 1500 atoms, of which about a third are on the surface. Properties, which are usually determined by the molecular structure of the bulk lattice, now become increasingly dominated by the defect structure of the surface. There are some properties that directly depend on the average coordination number of the participating atoms, such as the melting point or the solid–solid phase

E. Verrelli (&) Á D. Tsoukalas Department of Applied Physics, National Technical University of Athens, Heroon Politechniou 9, Zographou (Athens) 15780, Greece e-mail: [email protected] D. Tsoukalas e-mail: [email protected] E. Verrelli Department of Physics and Mathematics, University of Hull, Cottingham Road, HU67RX, Kingston upon Hull, UK

© Springer International Publishing AG 2017 157 P. Dimitrakis (ed.), Charge-Trapping Non-Volatile Memories, DOI 10.1007/978-3-319-48705-2_5 158 E. Verrelli and D. Tsoukalas transition in a crystal. As a result of the reduction in the number of neighboring atoms, surface atoms have narrower d-bands, so that the density of states can vary considerably. The second phenomenon occurs noticeably only in metals and semiconductors. It is called size quantization and arises because the size of a nanoparticle is comparable to the de Broglie wavelength of its charge carriers. Due to the spatial confinement of the charge carriers, the edge of the valence and conduction bands split into discrete, quantized, electronic levels. Thus, NPs lie in between the atomic and molecular limit of a discrete density of electronic states and the extended crystalline limit of continuous bands. In this work the focus is to present results concerning the use of NPs deposited using a novel room temperature cluster beam technique and show their applications in an emerging nonvolatile memory (NVM) technology: initially proposed by Rana et al. [4], it represents an evolution of the standard floating gate NVM (which is the building block of the Flash architecture) and consists in the replacement of the floating gate with an NP layer, namely Flash-like NP NVMs. This work, except presenting new results, provides also a review and in-depth insight into the main results obtained by the authors in the last decade on Flash-like NP NVMs [5–14].

5.2 Cluster Beam Generation of Metallic NPs

In Flash-like NPs NVMs, the use of metallic NPs represent an important advantage over Si NPs since the wide variety of materials available provide a variety of work functions that allow the engineering of the barrier seen by the charges stored into the NPs. The synthesis techniques of NPs, relevant for microelectronic applications, are basically three: Colloidal, Metal Evaporation with subsequent thermal annealing, Gas condensation. The preparation of NPs in colloidal systems is one of the most well-known methods for the synthesis of nanomaterials. Another well-known technique is based on the evaporation of the thin metallic films on the substrate which drive to the formation not of a continuous film but metallic islands [15]. In some cases the thermal annealing of the film helps in the formation of the NPs [16]. The drawback of this technique is the nonspherical shape of the NPs and the impossibility to perform size selection. The gas condensation technique is the one adopted in this work and is based on the nucleation and growth in flight of the metallic atoms from the gas phase. In this work the gas phase is realized by DC magnetron sputtering of the metallic target. This process takes place in a small chamber, NanoGen,1 attached through a small aperture (*5 mm) to the main one, where the samples are placed (Fig. 5.1a, b). As the sputtering goes on, the high pressure difference between the NanoGen and the main chamber (10−2 and 10−4 mbar, respectively) sweeps the atoms sputtered from the target material through the NanoGen toward the small aperture. During this phase, nucleation and

1www.mantisdeposition.com. 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 159

Fig. 5.1 a and b picture and schematic of the cluster beam generator used in this work; c schematic of the Flash-like NP NVM devices presented in this work growth of the NPs takes place until they reach the aperture and enter the main chamber to be soft landed on the sample’s surface. The whole process takes place at room temperature and is schematically represented in Fig. 5.1b. It is clear that two are the main parameters governing the size and flux of the NPs: the gas pressure in the NanoGen, which depends mainly on the Ar flow and DC sputtering power, and the distance between the target and the final aperture. The latter can be varied from a minimum of *10 cm (namely position 0) to a maximum of *20 cm (namely position 100) and has direct effect onto the size of the generated NPs. The larger is the distance the bigger is the nanoparticle diameter. As is, this technique allows fabricating NPs with size distributions with standard deviations of 20–30% the mean size. Since the 80–90% of the NPs result to be charged with 1 electron, they can be manipulated in flight using appropriate electric fields [17, 18]. The details of the physics governing this nanoparticle fabrication technique have been recently published by Quesnel et al. [19]. 160 E. Verrelli and D. Tsoukalas

The samples discussed in this work are based on the deposition of metallic NP ﬁlms by DC sputtering of pure Ni, Pt, Au targets in our cluster beam generator. Ni, Pt, and Au NPs were used in Flash-like NVMs which consist of metal–oxide– semiconductor (MOS) diodes, as shown in Fig. 5.1c, with the following gate structure: a p-Si substrate, a 3.5-nm-thick tunneling oxide (TO) of thermally grown SiO2, a layer consisting of NPs deposited by the cluster beam,, followed by the deposition by RF sputtering of an optimized high-k HfO2 insulating layer as control oxide (CO) [8–10, 13] with thicknesses of 20–30 nm.

5.2.1 Cluster Beam Synthesis of NPs Films

The cluster beam used in this work is based upon DC sputtering and thus the NP films’s properties like NP size and NP deposition rate are found to be affected from the DC sputtering power used, the Ar flow, the length of the aggregation zone, and the target material used. In order to clarify this point we present in Fig. 5.2a–d the TEM images of Ni NPs deposited on TEM copper–carbon grids using the same sputtering conditions but at different aggregation zone lengths. It is clear that both NP size and density are affected as shown in Fig. 5.2e–f. It is interesting to note here the cubic shape of Ni NPs generated in this process. On the other hand, as shown in Fig. 5.3, the Ar flow mainly affects the NPs density and only slightly the NPs size. As mentioned in the introduction, the NP size is extremely important in determining its electronic properties, especially because of the onset of quantum confinement effects. From the point of view of Flash-like NP NVMs, small NPs are of particular interest due to the corresponding scaling advantages. The minimum size of Ni NPs achievable with the system presented in this work is, as shown above, *3.5 nm. This minimum size was found to be highly dependent on the material used. Much smaller NPs have been obtained using noble metals like Pt or Au, which, as shown in Fig. 5.4, clearly allow the production of NPs with sizes approaching the 1 nm diameter. Another interesting feature of the NPs produced with this technique is that they result to carry a charge of 1 electron [17], acquired inside the agglomeration zone depicted in Fig. 5.1b. In order to investigate more in detail this feature we designed an experiment to allow us to study how the NPs respond to an external electric field. The set up considered is the one shown in Fig. 5.5a where it is visible the sample stage with the quartz crystal thickness monitor (QCM) placed along the direction of the NP beam (in-beam) and a second sample stage connected to the positive high voltage and placed off-beam in order to attract negatively charged particles and consequently removing them from the beam being detected by the QCM. The changes in the deposition rate recorded as we varied the high voltage applied to the off-beam stage allowed us to estimate the composition of the beam (fraction of uncharged and charged NPs). Using a pure Ti target to generate and accelerate Ti NPs, it was found that Ti NP beams are by 80% formed of charged NPs. As shown 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 161

Fig. 5.2 a–d TEM images of nickel NPs deposited on copper–carbon grids for four different distances target-aperture and with DC sputtering power of 30 W, Ar ﬂow 25 sccm, deposition duration 10 min; e–f summary of results extracted from the TEM images 162 E. Verrelli and D. Tsoukalas

Fig. 5.3 TEM images showing the effect of the Ar ﬂow on the deposited Ni NP ﬁlm. DC sputtering power of 30 W, deposition duration 10 min, position 35. The NP density in a is of the order of 5 Â 109 cm−2 while in (b) the NP density is well above 1012 cm−2. The mean NP size on the other hand only slightly changes: in a it is *4.5 nm while in b it is 5.5 nm

Fig. 5.4 TEM images of Pt a and Au b NPs deposited on TEM copper–carbon grids under same sputtering conditions (position 0). The slight deviation between the mean NP diameter and the most abundant one is related to NPs creating larger clusters upon landing onto the substrates. In these images the Pt NPs density is 1.6 Â 1012 cm−2 while the Au NPs density is 3.5 Â 1012 cm−2 in Fig. 5.5b, no matter what the length of the agglomeration zone is, the amount of charged NPs in the beam is always 80%, value approached at high voltages of 5 kV. It is interesting to note that the curve corresponding to position 0 differs slightly from the other two. The reason is that in this experiment we are not just 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 163

Fig. 5.5 a setup used to determine the composition (fraction of charged and uncharged NPs) of the NP beam generated with the cluster beam generator. b and c evolution of the amount of Ti NPs left in the beam with the increasing applied high voltage selecting the particles according to their charge state but according to their m/q ratio, where m is mass of the NP and q its charge. Under the assumption that the NPs in the beam can acquire at most the charge of 1 electron, it becomes clear that the differences in the curves in Fig. 5.5b are directly related to the different mean mass of the NPs being accelerated. So, heavier particles will require higher voltages to be effectively deflected from the original beam direction while on the other hand lighter particles will respond at low voltages already. The above considerations allow us to conclude that the Ti NPs generated at position 0 are lighter, i.e., smaller, than those generated at position 50 or 100, which on the other hand seem having similar mass. It should be noted that this result is in very good agreement with the result shown in Fig. 5.2e for Ni NPs (Ni NPs at position 50 or 100 have similar sizes and are bigger than those generated at position 0). Also Fig. 5.5c seems to confirm a result previously mentioned for Ni NPs, i.e., the Ar flow does not seem to affect the mass (i.e., the size) of the NPs. Very similar results, not shown here, with the above-mentioned ones hold for Ni, Pt, Au, Hf, Cu, and Ag NPs. 164 E. Verrelli and D. Tsoukalas

5.3 Dielectrics for NVM

A very crucial point in the fabrication of our Flash-like NP NVM is represented by the dielectric layer deposited on top of the NP layer, the so-called CO. Achieving a trap-free and leakage-free dielectric layer is a challenge, for this reason here below we present an in depth investigation of the trapping properties and leakage properties that, depending on the conditions used, characterize all the dielectric ﬁlms that are relevant for NVM applications providing at the end of this section with the process we found in order to fabricate dielectric ﬁlms suitable for our Flash-like NP NVM devices. In our particular case we will focus on HfO2.

5.3.1 Trapping Properties of HfO2 High-k Dielectric Films

When high-k dielectric thin films are deposited (using any of the available techniques, i.e., physical or chemical) it is very likely that they will contain defects in their matrix. These defects are responsible for the existence of electronically active trap sites in the band gap of the dielectric film, capable of trapping electrons with efficiencies and durations that vary depending upon the material and the nature of the defect. This property of the high-k dielectric layers actually makes them particularly attractive for the NVM industry as the metal-oxide-nitride-oxide-semiconductor (MONOS) structure has a good potential to replace the floating gate type memory. In order to illustrate the trapping properties of high-k films, hafnium oxide films have been deposited from a high-purity HfO2 target by PVD, namely RF sputtering. Films were deposited on SiO2, thermally grown using dry oxidation of silicon substrates at 850 °C. During all depositions the argon flux was at 60 sccm, the pressure at 8 Â 10−3 mbar, the deposition rate was kept constant at 0.1 Å/s at 200 W power and the thickness of the deposited film ranged between 10 and 30 nm. After deposition of the HfO2 film, aluminum was evaporated and patterned to form MIS capacitors. Except showing how intense trapping phenomena can be in hafnium dioxide films, what we would like also to discuss here is how the deposition conditions affect the spatial distribution of the traps. The deposition parameters which are investigated in this work are the deposition temperature and deposition ambient. Details about the deposition conditions are presented in Table 5.1. Reference samples with only the SiO2 film as dielectric do not exhibit any hysteresis of the C–V characteristics as it is shown in the inset of Fig. 5.6. For the samples in Table 5.1, the hysteresis observed is counterclockwise indicating that charging from the Si substrate is predominant [27]. A common feature of all samples discussed here is the similarity of their electrical characteristics regarding hysteresis and charge retention. As an illustrating example, in Fig. 5.6 the C–V characteristics for different amplitude of the bias sweep cycle are presented for sample A. Then, in Fig. 5.7 we present the flat-band voltage shift dependence upon 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 165

Table 5.1 Fabrication details of the samples discussed in this work Sample code A B1B2B3I1I2I3 Substr. type p p p p p p p

Nominal SiO2 thick. (nm) 3.5 3.5 3.5 3.5 3.5 3.5 8

Nominal HfO2 thick. (nm) 30 10 20 30 30 15 30

HfO2 dep. Temp. (°C) 25 200 200 200 300 300 300

HfO2 dep. Ambient Ar Ar:O2 Ar:O2 Ar:O2 Ar:O2 Ar:O2 Ar:O2 2:1 2:1 2:1 6:1 6:1 6:1

Postdeposition annealing 400 °C, N2:H2, No No No No No No (PDA) 20 min

Fig. 5.6 C–V characteristics for sample A. Four sweeps are shown: 4 V (4 V ! −4V! 4V) up to 15 V (15 V ! −15 V ! 15 V). Large hysteresis is observed above the 8 V cycle. In the inset: C–V characteristics for reference Al-SiO2-pSi structures. Four sweeps are shown: 1 V (1 V ! −1V! 1V) up to 4V (4V! −4V! 4 V). No hysteresis or drift in the characteristics is found. From the capacitance in accumulation a value of 3.8 nm is extracted for the SiO2 layer thickness the sweep amplitude as extracted from Fig. 5.1. Large hysteresis is observed for sweeps above 8 V. The upper branch (electrons storage) and lower branch (holes storage) of Fig. 5.7 present different turning points. From that figure it is clear that electron trapping starts above 7 V while hole trapping starts above 11 V. According to Ref. [20] when extracting the flat-band voltage from C–V measurements, the amount of stored charge can be evaluated using Eq. 5.1 where Vfb is the flat-band voltage, Qot is the charge present in the dielectric layer, and Cox is the accumulation capacitance of the capacitor. Since for the present experiments we are dealing with a mixed dielectric structure it is convenient to note that Cox, is given by Eqs. 5.2, 5.3, and 5.4, where d is the thickness of the dielectric layer and k is the relative dielectric constant. 166 E. Verrelli and D. Tsoukalas

Fig. 5.7 Hysteresis plot showing the ﬂat-band voltage dependence upon the bias sweep amplitude for sample A. The upper branch corresponds to backward sweeps

Qot DVfb ¼À ð5:1Þ Cox e k A C ¼ 0 SiO2 ð5:2Þ ox EOT ¼ þ ðÞÀ1 ð : Þ EOT dSiO2 KR dHfO2 5 3 ¼ = ð : Þ KR kHfO2 kSiO2 5 4 – In the present work, dSiO2 is 3.8 nm (determined also experimentally from C V measurements on reference capacitors) while dHfO2 is estimated using the deposition data. In Table 5.2 we show a summary of the parameters EOT and KR extracted from the experimental values of Cox. The ratio, KR, between the k of the two dielectric layers is not constant for our set of samples (because the kHfO2 changes with the deposition conditions). Thus, when comparing the hysteresis of these samples it is convenient to consider not the flat-band voltage shift with respect to the ideal (uncharged) dielectric stack but the charge stored into the dielectric stack following (1). Furthermore, instead of applied voltage it is mandatory to consider the equivalent electric field in the oxide stack (EEOX) derived by dividing the voltage applied across the device with the EOT (EEOX represents also the electric field within the tunneling silicon dioxide layer). It should be noted that Eq. 5.1 is accurate in relating DVfb with Qot under the assumptions that (1) the density of interface states at the SiO2-Silicon substrate interface remain unaltered when

Table 5.2 Dielectric constant relative to silicon dioxide and equivalent oxide thickness as extracted from electrical measurements. A ±10% error should be considered for these quantities Sample code AB1B2B3I1I2I3

KR 4.8 3.2 3.6 3.1 5.1 4.8 4.7 EOT (nm) 9.8 6.6 9.1 13.3 9.3 6.6 14.4 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 167 comparing two C–V characteristics from which DVfb will be extracted, and (2) the traps, within the dielectric stack, responsible for the C–V shifts are placed at the border with Si substrate. In Refs. [20, 21] it is shown that in general, when the charge centroid Xot, measured from the metal gate, is not placed at the interface with the semiconducting substrate, the correct relation to consider is Eq. 5.5:

Qot DVfb ¼Àc ; ð5:5Þ Cox where c = Xot/dox is in the range [0,1] depending on the trapped charge distribution. The above equation was derived considering an MOS capacitor with a single insulating layer. When a dielectric stack is considered instead, Eq. 5.5 should be modiﬁed accordingly as described in Refs. [22, 23]. For MOS capacitors like the one discussed in this work, with the trapping layer (HfO2) placed between a trap-free tunneling insulator (SiO2) and the metal gate (Al), the relation to be used is Eq. 5.6:

D ¼À Qot Xot ð : Þ Vfb e 5 6 0kSiO2 A KR

with Xot measured from the Al-HfO2 interface and such that Xot < dHfO2 . It is interesting to consider two limit situations: (1) the trapped charge within the hafnium oxide layer is distributed homogeneously, i.e., we have a constant density q of bulk trapped charges. (2) the trapped charge within the hafnium oxide layer is placed at or very close to its interface with SiO2, i.e., we have a constant density r of interface trapped charges. q In the former case, we have that Xot = dHfO2 /2, Qot = AdHfO2 and from Eq. 5.6 D 2 it is concluded that Vfb should be proportional to (dHfO2 ) . In the latter case we r D have Xot = dHfO2 , Qot = A and from Eq. 5.6 it is concluded that Vfb should be 1 proportional to (dHfO2 ) [24, 25]. Following Eq. 5.6 it is possible to calculate the surface charge density r = Qot/A using the following relation, Eq. 5.7: D r ¼Àe Vfb ð : Þ 0kSiO2 KR 5 7 dHfO2

where Xot has been replaced by dHfO2 . We remark that Eq. 5.7 holds exactly when considering interface traps while in the case of bulk traps the right-hand side of the equation is multiplied by a factor 2

(since in that case Xot = dHfO2 /2). It is thus easily concluded from Eq. 5.7 that when r * r bulk traps prevail, dHfO2 , i.e., /dHfO2 should be independent upon the hafnium oxide layer thickness. On the other hand when interface traps prevail, r should be independent of dHfO2 . Samples B1, B2, and B3 have been fabricated under the same conditions, and differ only by the thickness of the hafnium oxide film. It is interesting to note that their KR values are quite similar in the range 3.1–3.6 and quite smaller than the 168 E. Verrelli and D. Tsoukalas value of 5–6 expected for the ideal HfO2 matrix. In Fig. 5.8 the comparison of their electrical properties is shown. For fixed electric field the amount of hysteresis depends on the oxide thickness. In particular, as the thickness decreases also the width of the hysteresis decreases. In order to connect this observation with the trap distribution two conditions should be fulfilled: (1) the trap distribution in samples prepared under the same experimental conditions which differ only by the hafnium oxide layer thickness has to be the same, (2) for fixed EEOT the amount of injected charge into samples prepared under the same experimental conditions which differ only by the hafnium oxide layer thickness has to be the same. The former condition is a fundamental assumption in this work while the latter is ensured by the fact that the current density for fixed EEOT is independent from the thickness of the hafnium oxide thickness as presented in Fig. 5.9. Under the above conditions, our method is equivalent to the one applied by Hosoi et al. [24] or Young et al. [25] where the trap distribution (either homogeneous in the bulk or interfacial) is extracted studying the

Fig. 5.8 Hysteresis plot showing the amount of charges per cm2 against the absolute value of the equivalent oxide ﬁeld corresponding to the amplitude of each sweep bias cycle. The upper branch of each curve corresponds to forward sweeps while the lower branch to backward sweeps

Fig. 5.9 J–E characteristics for samples B1, B2, and B3 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 169

Fig. 5.10 Total trapped charge density per unit volume (in one hysteresis cycle) against the absolute value of the equivalent oxide ﬁeld. In the inset, the same plot in log–log scale showing the dependence of the trapped charge upon the electric ﬁeld. It is almost linear up to 4 MV/cm and superlinear above 5 MV/cm

relation between the trapped charge and the injected charge. Since the same equivalent electric field results in the same current through each of our devices, we conclude that same equivalent electric field would result in the same injected charge into the devices. This last comment is important to understand that under the experimental conditions described above, hysteresis plots do provide information about the spatial trap distribution in a similar manner with [24, 25]. In particular, for samples B1, B2, and B3, our findings are in agreement with a model that assumes charges to be trapped into the bulk of the hafnium oxide, i.e., in a three-dimensional region. In order to illustrate this point, we present in Fig. 5.10 the total trapped volume charge density involved in a hysteresis cycle for sweep measurements (for measurements under pulsed regime, not shown here, a similar result holds). This total trapped volume charge density is obtained from hysteresis plots like the ones presented in Fig. 5.8 as the algebraic difference, between the upper branch and the lower branch charge values at a fixed electric field divided then by the hafnium oxide layer thickness. The trapped volume charge densities of B1, B2, and B3 are very similar for any value of the electric field. These results confirm that the traps responsible for the observed hysteresis are bulk traps. In a similar way with the previous set of samples, I1 and I2 have been fabricated under the same conditions, but also differ by the thickness of the hafnium oxide film. For this set of samples we have calculated a higher value of KR that equals 5 instead of 3 calculated in the previous set. In Fig. 5.11 the comparison of their electrical properties is shown. Unlike the previous set of samples, no dependence of the charge involved in a hysteresis cycle upon the hafnium oxide thickness is observed. Using similar considerations to those presented for the previous set of samples and also considering that for this set the current density for fixed EEOT is independent from the thickness of the hafnium oxide thickness, not shown here for brevity, it is concluded that the trapping in the case of hafnium oxide deposition at 300 °C in Ar:O2 6:1 is related to traps with a two-dimensional spatial distribution, most likely at the interface between the dielectric layers, as observed in [26]. This is 170 E. Verrelli and D. Tsoukalas

Fig. 5.11 Hysteresis plot showing the amount of charges per cm2 against the absolute value of the equivalent oxide field corresponding to the amplitude of each sweep bias cycle. The upper branch of each curve corresponds to forward sweeps while the lower branch to backward sweeps confirmed also by the graph shown in Fig. 5.12 where following the same approach as for the previous set of samples, we present the total trapped surface charge density involved in a hysteresis cycle for sweep measurements (for measurements under pulsed regime, not shown here, a similar result holds). The trapped surface charge densities of I1 and I2 are very similar for any value of the electric field. This result shows that the observed hysteresis is generated by interface/border traps placed within the hafnium oxide but close to its interface with SiO2. As a final remark, it is interesting to note here how the presence of bulk traps in the hafnium oxide film is the indication of a more relaxed dielectric network (lower dielectric constant) as compared with the case where traps have been observed only at the interface with silicon dioxide where the dielectric constant was clearly higher and closer to ideal values.

Fig. 5.12 Total trapped charge density per unit surface area (in one hysteresis cycle) against the absolute value of the equivalent oxide ﬁeld. In the inset, the same plot in log–log scale showing the dependence of the trapped charge upon the electric ﬁeld. It is almost linear up to 4 MV/cm and superlinear above 5 MV/cm 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 171

5.3.2 Optimization of the HfO2 High-k Dielectric Film

As demonstrated here above, the as deposited hafnium oxide exhibits a high concentration of traps that need to be eliminated/passivated if that material is to be used as control oxide in nonvolatile memories. For the above reason, in this section will be presented and discussed the optimization route of hafnium oxide that we developed in order to use this insulator as control oxide in nonvolatile memories based on metallic nanoparticles. The samples prepared were CMOS capacitors as shown in Fig. 5.13 while their fabrication details are summarized in Table 5.3. The dielectric stack considered consists of silicon dioxide and hafnium oxide. The silicon dioxide layer, with a thickness of 4 nm, was thermally grown at 850 °C on p-Si. The hafnium oxide was deposited by RF magnetron sputtering in an ultra-high-vacuum (UHV) system. Deposition took place at different temperatures, according to Table 5.1. RF sputtering was carried out at 200 W directly from a high-purity hafnium oxide target. The argon ﬂow during deposition was 60 sccm and for oxygen, sample D, was 10 sccm. The set of samples, A to D, were fabricated to investigate which process has to be used to ensure that no charging effects will take place in the hafnium oxide. Aluminum evaporation and patterning to form MIS capacitors followed the hafnium oxide deposition step. For samples C and D a post-metal annealing in N2: H2 at 320 °C for 20 min was also performed. Characterization was performed by C–V sweeps at 1 MHz using an Agilent 4284A impedance analyzer while I–V measurements were performed with an HP4140B picoamperometer. In Fig. 5.14a the C–V sweep bias measurements on sample A are presented. These measurements are performed by sweeping the bias in forward and backward directions increasing the sweep amplitude at each cycle, i.e., from

Fig. 5.13 Schematic of a capacitor showing the mixed dielectric stack considered in this work. The SiO2 and HfO2 layers represent the tunneling oxide and the control oxide, respectively, of a hypothetic nanoparticle memory (nanoparticles not considered here) 172 E. Verrelli and D. Tsoukalas

Table 5.3 Experimental details concerning the samples discussed in the paper. The row headers in capital letters, from A to D, are the four samples. In the column headers, d stays for the thickness of the ﬁlm and PMA for post-metal annealing

Structure HfO2 HfO2 deposition HfO2 deposition PMA (N2:H2, d (nm) Temp. ambient 320 °C, 20 min)

A p-Si/SiO2/HfO2 30 RT Ar –

B p-Si/SiO2/HfO2 30 300 °C Ar –

C p-Si/SiO2/HfO2 30 300 °C Ar ✓

D p-Si/SiO2/HfO2 25 300 °C Ar:O2 (6:1) ✓

2V! −2V! 2V,3V! −3V! 3V,4V! −4V! 4 V, and so on. In Fig. 5.14b the flat-band voltage shifts extracted from Fig. 5.14a are shown. It can be noted that as the amplitude of the bias sweep increases the C–V curve drifts toward negative voltages indicating that a positive charge is permanently trapped inside the dielectric stack. At the same time counterclockwise hysteresis at low voltages is also present indicating that charging takes place from the silicon substrate [27]. Control sample with only 4 nm silicon dioxide layer as insulator, not shown here, exhibits no charging effects taking place in this dielectric layer. The above considerations bring us to the conclusion that for sample A charge trapping in the hafnium oxide close to its interface with the silicon dioxide layer must be responsible for the observed behavior. For what it concerns sample B, Fig. 5.15a, b, a beneficial effect of having deposited the hafnium oxide layer at 300 °C is clearly visible. A smaller amount of drift is present with respect to sample A. Counterclockwise hysteresis is still present but starts at higher voltages than A. Thus, with respect to sample A we can conclude that a smaller amount of traps are present in the hafnium oxide film of B. Traps responsible for hysteresis should be deeper than in A since higher voltages are needed to charge them [28, 29].

Fig. 5.14 a C–V sweep bias measurements performed on sample A. In the legend 2 V stays for the sweep 2 V ! −2V! 2V.b Flat-band voltage shift extracted from a as a function of the sweep amplitude. The upper branch corresponds to backward sweeps of type 2 V ! –2 V while the lower branch to forward sweeps of type −2V! 2V 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 173

Fig. 5.15 a C–V sweep bias measurements performed on sample B. b Flat-band voltage shift extracted from a as a function of the sweep amplitude

A possible argument that could explain the above result is film densification, i.e., atomic rearrangement of the hafnium oxide matrix to a more compact and stable configuration [30–32]. In sample C, Fig. 5.16a, b, the post-metal annealing performed had positive effect on the electric properties of the dielectric stack. No drift is observed at low voltages while counterclockwise hysteresis still exists. It is worth noticing also that the C–V characteristic became steeper in depletion region with respect to A or B sample. This is the signature that N2:H2 annealing had also a positive effect onto the density of interface states Dit at the interface between the insulator and the silicon substrate [33]. Densification of the film and defect passivation at the interfaces could be considered to explain the results [34, 35]. Finally, for sample D as it is shown in Fig. 5.17, the effect of depositing in a mixture of argon and oxygen 6:1 ratio is to highly improve the quality of the hafnium oxide film. As a result the drift has disappeared and hysteresis smaller than 100 mV is observed. The deposition at 300 °C together with the post-metal annealing in N2:H2

Fig. 5.16 a C–V sweep bias measurements performed on sample C. b Flat-band voltage shift extracted from a as a function of the sweep amplitude 174 E. Verrelli and D. Tsoukalas

Fig. 5.17 a C–V sweep bias measurements performed on sample D. b Flat-band voltage shift extracted from a as a function of the sweep amplitude and Oxygen incorporation seems to be able to remove/passivate most of the traps responsible for the hysteresis and drift observed in sample A. In recent years has become clear that most of the charge trapping phenomena occurring in hafnium-based dielectrics are related with oxygen vacancies [36]. It is clear from experimental [37, 38] and theoretical observations [39] that such vacancies could be present in different charged state conﬁgurations. The above result seems to indicate that at least in the case of the dielectric stack studied here, hafnium oxide on silicon dioxide, the process followed and especially the oxygen incorporation succeeded in decreasing the amount of active vacancies to a negligible level [40]. A beneﬁcial effect is also observed on the leakage current, Fig. 5.18, which is highly reduced in sample D with respect to the nonoptimized sample A. Although

Fig. 5.18 Comparison between the measured (samples A and D) and simulated J–V characteristics. Below the dielectric breakdown voltage (*8.5 V), the measured leakage current of sample D is much higher than the simulated one (considering a trap-free insulating stack) but also much lower than the leakage current of the nonoptimized sample A 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 175 traps do not induce hysteresis in sample D, they should be responsible for the increased leakage current shown in Fig. 5.18 when comparing the measured J–V characteristic with the simulated one obtained considering the combination of Fowler–Nordheim (F–N) conduction, direct tunneling (DT), and modiﬁed F–N conduction through the dielectric stack (Fig. 5.19). A plot of the Log (J/E) versus E1/2, Fig. 5.20, demonstrates that the Poole–Frenkel (P–F) emission might be the dominant mechanism underlying the leakage current mechanism through the dielectric stack of sample D.

Fig. 5.19 Band diagrams representing the different conduction mechanisms theoretically expected in the dielectric stack considered in this work in absence of any trap: modiﬁed F–N (3 V), DT (5 V) and F–N(8V)

Fig. 5.20 P–F plot of the experimental leakage current of sample D shown in Fig. 5.5 indicating that in the range 3–8VP–F conduction is the dominant leakage mechanism 176 E. Verrelli and D. Tsoukalas

5.3.3 Leakage Current of HfO2 High-k Dielectric Films

Hafnium oxide has been widely investigated in the last few years in order to determine its dielectric and physical properties. Particular attention has been given to the assessment, theoretically [41] and experimentally [42], of the properties of the defects of this high-k material. What becomes clear by reviewing the existing literature on HfO2 is that there is a wide range of conduction mechanisms and trap energies that have been identified experimentally. Sahoo et al. [42] observe Poole– Frenkel (PF) conduction in fresh and stressed devices (trap energy of 0.36 eV) together with ohmic conduction at low fields. Paskaleva et al. [43] observe PF conduction with traps located at 0.64 eV while the ohmic conduction at low fields is ascribed to traps located at 20 meV. By spectroscopic ellipsometry measurements, Takeuchi et al. [44] bring evidence of a band of traps located in the range 1.2–0.7 eV below the conduction band (CB) which could be broadened by changing the processing temperature. They also show that the larger the trap density, the larger will be the leakage current and the hysteresis of the devices. Theoretical [41, 45] and review works [46] show that the defects in HfO2 thin films are generally related to oxygen vacancies which could give rise to trap depths as large as 1.5 eV from the CB edge. Recently, the interest in the energy location of defects in the HfO2 matrix has increased due to the development of resistive switching memories based on this material [47–49]. In this section, we would like to present an in depth investigation of the leakage current characteristics of hafnium oxide thin films. The devices considered in this section are MIS capacitors with the insulator stack consisting of silicon dioxide and hafnium oxide. The silicon dioxide layer, with a thickness of 3.5 nm, was thermally grown at 850 °C on p-Si(100). The hafnium oxide was deposited by RF magnetron sputtering in an ultra-high-vacuum (UHV) system. Two different conditions/samples will be investigated in this work which drive to a nearly trap-free high-k film or to a charge-trap layer: sample A has an hafnium oxide layer deposited at 300 °C, namely “trap-free sample” [10], while for sample B the deposition took place at room temperature (25 °C), namely “charge-trap sample” [9]. RF sputtering was carried out at 200 W directly from a high-purity hafnium oxide target and the final nominal thickness of the deposited films was 25 nm. The argon flow during deposition was 60 sccm and for oxygen, only sample A, was 10 sccm. For sample B a postdeposition annealing step was performed at 400 °C for 20 min in N2:H2. Aluminum evaporation and patterning to form MIS capacitors followed the hafnium oxide deposition step. A post-metal annealing in N2:H2 at 320 °C for 20 min was also performed. Characterization was performed by C–V sweeps at 1 MHz using an Agilent 4284A impedance analyzer, I–V measurements were performed with an HP4140B picoamperometer together with a Janis cryogenic system while XRD measurements took place using an X’Pert Pro PANalytical system. X-ray diffraction (XRD) measurements performed on the two samples, Fig. 5.21, reveal a completely different physical structure of the two hafnium oxide films: the trap-free is polycrystalline while the charge-trap one is mainly amorphous. Regarding the former, the diffraction peaks 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 177

Fig. 5.21 XRD patterns for the trap-free and charge-trap samples discussed in this work

observed are in very good agreement with the ones reported in the literature (see for example [50, 51]) and can be attributed to the different crystalline phases of this material: monoclinic [52], orthorhombic [53], tetragonal [54], and cubic [55]. The intense peak at *30° represents the signature of a strong monoclinic component in the polycrystalline film, in agreement with Kukli et al. [56]. Regarding the latter, the broad peak at *55° is normally observed in amorphous films [57]. The trap-free and the charge-trap sample present as well different dielectric properties: the former has a negligible amount of electrically active traps within the dielectric stack while the latter has a very large amount of such traps, more than 1013 cm−2 with an exponential spatial trap distribution [11]. These different characteristics can be easily visualized by performing capacitance–voltage (C–V) sweeps in forward and backward directions as shown in Fig. 5.22. The 12 V amplitude C–V sweeps on the trap-free sample reveal a negligible hysteresis of the curves (only few hundreds of mV) while on the charge-trap sample the hysteresis is Qot Xot of *4.6 V. Thus, recalling that DVFB ¼Àc ,withc ¼ , where V is the Cox tox FB flat-band voltage, Qot is the charge trapped in the oxide, Cox the accumulation capacitance, tox the thickness of the dielectric layer, and Xot the centroid of the trapped charge measured from the gate electrode, becomes clear that the trap-free sample has an amount of electrically active traps much smaller than the charge–trap sample. The question that we explore here is whether the traps’ energy location is

Fig. 5.22 C–V sweep measurements performed on the trap-free sample and the charge-trap sample 178 E. Verrelli and D. Tsoukalas

Fig. 5.23 I–V temperature measurements for the trap-free sample A and the charge-trap sample B the same or not in the two samples. In order to clarify this point I–V measurements have been carried out at different temperatures in the range 80–400 K and are shown in Fig. 5.23. It is clear that the charge-trap sample presents a much stronger temperature dependence of the I–V characteristics with respect to the trap-free sample. The above observation preludes to intense differences among the trap energy locations and the mechanisms at play in the two samples which will be presented in the next section. In presence of traps in the high-k dielectric material, as in the samples presented in this work, it is quite common to encounter typical trap-related current leakage mechanisms like: (1) hopping, i.e., ohmic conduction at low fields generally related with shallow traps and given by (Eqs. 5.2, 5.8) Poole–Frenkel (P–F), i.e., field assisted emission of carriers from deep traps at high fields and given by (Eq. 5.3, 5.9) the space-charge-limited current (SCLC), especially evident in presence of very large amounts of traps and given by Eq. 5.10. Except the above “bulk limited” leakage mechanisms, there is a further leakage mechanism, relevant for our samples, which belongs to the “electrode limited” mechanisms and this is the Fowler– Nordheim tunneling (F–N) given by Eq. 5.11. In the above-mentioned equations, q Á Ut is the height of the barrier seen from a trapped carrier, Eox is the electric field within the oxide, eox is the absolute dielectric constant of the oxide, n is a real number 2, mox is the electron mass in the oxide while m0 is in vacuum, and Ub is the barrier height at the electrode–oxide interface injection point. In the next two sections, the above models will be applied to the I–V characteristics depicted in Fig. 5.23.

qÁUt À Á Jh Eox Á e k T ; Hopping current ð5:8Þ pffiffiffiffiffiffi q3 pffiffiffiffiffi qÁU À Á E t pÁeox ox À Á JPÀF Eox Á e k T ; P À F current ð5:9Þ 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 179

n JSCLC ðÞEox ; SCLC current ð5:10Þ

B À ¼ Á 2 Á Eox ; À JFÀN A Eox e F N current with q3 m 1 m 1 A ð5:11Þ A ¼ Á 0 Á ¼ 1:54 Â 10À6 Á 0 Á ; Á p Á U U 2 8 h mox b mox bV Á ðÞÁ 1=2 1=2 ¼ 4 2 mox U3=2 ¼ : Â mox Á U3=2 MV B b 68 3 b 3 Á q Á h m0 cm

5.3.3.1 Trap-Free Sample

At low ﬁelds (depending on temperature) the characteristics of the trap-free sample show a clear ohmic behavior as evidenced in Fig. 5.24a. By applying the hopping model, i.e., by plotting the conductivity versus q/kT as shown in Fig. 5.24b, c, it was possible to estimate the activation energies involved in the hopping process. For both positive and negative biases the graphs are very similar as well as the

Fig. 5.24 Hopping model applied to the trap-free I–V characteristics: a linear–linear I–V plot in the low-field region evidencing the ohmic behavior, b and c log-linear graphs of the conductivity versus q/kT showing the presence of two shallow traps involved in the hopping process 180 E. Verrelli and D. Tsoukalas extracted activation energies. Thus, it is probable that for both polarizations the traps involved in the hopping process are the same. It is interesting to note that in the temperature range investigated, there is evidence of two shallow traps: one located at few tens of meV below the conduction band edge, active at temperatures below room temperature (300 K), while at higher temperatures a trap located at 0.13–0.14 eV becomes active. The results are in agreement with previously reported results by Paskaleva et al. [43] although they perform measurements up to 300 K and thus do not provide evidence for the latter shallow trap observed in this work. P–F plots consist in plotting ln(J/E) versus E−1/2 and from such plots it is possible to get qualitative information (i.e., straight lines represent a first indication of a possible match with the model) and quantitative information (i.e., trap energy location and the definitive confirmation of the match). The latter can be understood through Eq. 5.12.OnaP–F plot, the intercept, ln(A) of the best linear fitofthe experimental data carries the information relative to the trap energy, on the other hand the slope is directly related the dielectric constant of the high-k and thus can be used to validate the procedure. qffiffiffiffiffiffiffi pffiffiffiffiffiffiffi J 1 q3 ln ¼ ln A þ Á Á Eox; Eox kÁT pÁeox with ð5:12Þ ¼ : À q Á U ln A const kÁT t

In the high-field and high-temperature (above room temperature) regime, it was found that for both positive and negative biases the P–F model applies very well to the experimental I–V characteristics. The P–F plots in Fig. 5.25a, c show clear straight lines and from the graphs shown in Fig. 5.25b, d the value of the trap energy can be extracted: 0.23 eV for negative biases and 0.38 eV for positive ones. The dielectric constant value extracted from the P–F analysis, also known as dynamic dielectric constant, lies between the optical dielectric constant value (*5 for most high-k materials [58]) and the static dielectric constant one (*18 for the samples discussed in this work) thus confirming the validity of the whole procedure [59]. From these last three graphs just mentioned above, it becomes clear that the P–F model applies only above room temperature. Thus, at high fields and low temperatures it is reasonable to expect that F–N mechanism contributes to the total leakage current as shown in Fig. 5.26a. Due to the coexistence with P–F, the F–N analysis is not possible simply through Eq. 5.11. The above point is well represented in Fig. 5.26b where we see that as the temperature decreases, at high fields the I–V characteristics tend to follow a specific straight line on the F–N plot (the F–N is basically a temperature independent phenomenon). The B parameter extracted from this graph allows the estimation of the Si–SiO2 barrier height at around 1.9 eV, considering mox = 0.42 m0. It is clear that the underestimation of this barrier height with respect to its standard *3 eV value is due to the coexistence of the F–N with the P–F mechanism. 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 181

Fig. 5.25 a and c P–F plots regarding the trap-free sample; b and d intercept of P–F best ﬁts versus q/kT and extraction of trap depth

Fig. 5.26 a Band diagram of the trap-free sample biased with +10 V, showing the F–N injection from the Si substrate. This graph has been obtained with the Poisson solver developed in [11]. b F–N plot for positive biases 182 E. Verrelli and D. Tsoukalas

5.3.3.2 Charge-Trap Sample

Similarly with the trap-free sample, the I–V characteristics of the charge-trap sample show at low fields an ohmic behavior as shown in Fig. 5.27a. By applying the hopping model to those characteristics it is possible to extract the trap depth, which is around 0.3 eV as shown in Fig. 5.27b, c. It is interesting to note that for positive biases in Fig. 5.27a can be recognized a second linear region, beyond the one crossing the origin previously considered. By separately fitting these parts as well, the extracted activation energy is only 0.12 eV. The fact that these curves do not cross the origin together with the fact that the activation energy is much lower than the other one, allows us to conclude that these secondary linear branches are not related to hopping but most probably to the contribution of other conduction mechanisms that we will analyze below. At high fields the I–V characteristics of the charge-trap sample look definitely more complicated than those of the trap-free sample. The characteristic point that

Fig. 5.27 Hopping model applied to the charge-trap I–V characteristics: a linear–linear I–V plot in the low-ﬁeld region evidencing the ohmic behavior, b and c log-linear graphs of the conductivity versus q/kT showing the presence of one shallow trap involved in the hopping process. The 0.12 eV trap, as explained in the text, is not believed to be a real hopping center 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 183

Fig. 5.28 a SCLC plot and b the extracted SCLC exponent is constant throughout the temperature range separates the hopping regime from the high-field one is a characteristic kink, with sudden increase of the current, present on every I–V curve of this sample (especially clearly visible at low temperatures). This kink point is considered to be the signature that a trap-filling phenomenon involving a large amount of traps, probably with a sharp energy distribution, has been triggered [60, 61]. Furthermore, this process is self-limited, since beyond the kink the current increases less abruptly than at the kink. The above description fits very well with the SCLC model [60] which is found indeed to be responsible for the conduction at medium fields, as shown in Fig. 5.28. It should be stressed that according to the SCLC model, in presence of a trap-free SCLC conduction, an exponent n = 2 should be observed while higher exponents, as the n = 3 in our charge-trap devices, are generally found when a trap-filling process is also involved [62]. On the other hand, at very high fields, i.e., up to breakdown, the electric field is intense enough to trigger the P–F mechanism as shown in Fig. 5.29 and the extracted trap depth is around 1.7 eV. Please note that historically the P–F has been often misunderstood for SCLC with very high exponents (e.g., n 2), and the reason is the very strong similarity between the P–F plots and the SCLC plots which is evident also in this work. From the above analysis, it is clear how in the trap-free sample the only traps left in the hafnium oxide layer are a small amount of shallow traps, which explain the absence of any hysteresis in Fig. 5.22. Indeed, being the traps shallow, the room temperature C–Vs would not present much hysteresis because the traps would have been emptied by the time the sweep is completed. The charge-trap sample on the other hand, has both shallow and deep traps, the latter explaining the large hysteresis in the C–Vs and long charge retention time. 184 E. Verrelli and D. Tsoukalas

Fig. 5.29 a P–F plot regarding the charge-trap sample; b and c intercept of P–F best ﬁts versus q/kT and extraction of trap depth

5.4 Use of Metallic NPs for Flash-like NVM Applications

In the last decade, nanoparticle (NP) memory devices have generated a lot of interest, and many research papers have highlighted NP’s advantages over the standard floating gate technology which is the basis for the Flash nonvolatile-memory (NVM) architecture. The key advantages of the NP array over the floating gate are the ability for more aggressive scaling and for band engineering of the device by appropriately choosing the NP’s material. The most common NP materials used in memory devices are silicon [63] and, more recently, germanium [64] which are both fully compatible with CMOS technology. On the other hand, metallic NPs present advantages over semiconducting NPs in nanocrystal memory applications. The higher electron affinity of several metals compared to those of Si allows one to engineer the potential well of the storage nodes in order to create an asymmetric barrier between the Si channel and storage nodes [65]. Unfortunately, metals are a contaminant in the silicon substrate and attention must be paid to avoid possible diffusion of metal atoms. Therefore, the NP formation process and all subsequent steps must be performed at low temperature. A critical process step after NP formation is the deposition of the control oxide (CO). A promising candidate for the CO is HfO2 film which has been successfully used to replace the silicon dioxide 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 185 gate dielectric [66]. It is clear that in this work we always deal with a mixed dielectric stack. The advantage of using a mixed dielectric stack in the nonvolatile memory scheme, with silicon dioxide as the tunneling oxide (TO) and hafnium oxide as the CO, is the reduction of the voltage required for the writing/erasing operation of the memory device. From simple electrostatic arguments, it can be shown that the use of a high-k material for the CO results in an enhanced electric field in the TO for the same applied gate voltage [67]:

k ¼ HfO2 ffi ; ð : Þ ESiO2 EHfO2 6EHfO2 5 13 kSiO2 fi where ESiO2 and EHfO2 are the electric elds in the TO and CO, respectively, while fi kSiO2 and kHfO2 are their respective relative dielectric constants. De ning the equivalent oxide thickness of the hafnium oxide layer as

k ¼ SiO2 ð : Þ EOTHfO2 dHfO2 5 14 kHfO2 it can be shown that the voltage drop, DV across the dielectric stack splits into the following two voltage contributions:

D ¼ a Â D VSiO2 V DV ¼ð À aÞDV HfO2 1 ð5:15Þ d a ¼ SiO2 ðÞ with þ known as gate coupling factor dSiO2 EOTHfO2 Å Å For example, by assuming dSiO2 =35 and dHfO2 = 300 , which are also the D ﬃ % Â D design parameters we often used, it turns out that VSiO2 41 V. Electrical characterization of the Flash-like NP NVMs was accomplished with capacitance–voltage (C–V) measurements using an HP4284a and using I–Vmeasure- ments obtained with an HP4140b picoammeter. In order to characterize the memory behavior of the memory devices we have performed C–Vmeasurementsatroom temperature on all samples under sweeping bias conditions of increasing amplitude (frequency 1 MHz, sweep rate 1 V/s). Namely, from 2 V ! −2 V (backward sweep) and from −2V! 2 V (forward sweep), then 3 V ! −3Vand−3V! 3V,andso on until hard breakdown conditions of the dielectric are reached. No waiting time was applied between two consecutive sweeps. The probe light was kept on during each electrical measurement in order to ensure a good minority carrier concentration level in the inversion regime.

5.4.1 Ni NPs Prototypes

In this section, we present the fabrication of Ni NP memory devices processed at low temperatures (<400 °C) with an optimized high-k CO11 and different NP sizes 186 E. Verrelli and D. Tsoukalas and densities aiming at the optimization of the device performance. The use of nickel or a nickel silicide material for the nanoparticles has been investigated by several other research groups, and promising memory performance in terms of endurance or retention has been demonstrated [68–72]. In the present work we present an analysis of the influence of nanoparticle size and areal density on NP memory device performance and demonstrate the ability to estimate the quasi-bound state in the Ni nanoparticles through combined C–V and I–V measurements. The devices considered are MOS diodes, as shown in Fig. 5.30, with the following gate structure: a p-Si substrate, a 4-nm-thick TO of thermally grown SiO2,a layer consisting of nickel NPs deposited by a room temperature physical process, followed by the deposition of an insulating layer of 30 nm of HfO2 by RF sputtering. A reference device was also fabricated by omitting the NP deposition step. The NP deposition was performed using our cluster beam generator. A pure Ni target was used at a sputtering power of 30 W with an Ar flow of 75 sccm. By varying the distance between the Ni target and the entrance to the main chamber the NP size was varied from 4 to 7 nm, and by varying the deposition time the density was also varied from 8 Â 1011 to 1.6 Â 1012 cm−2, as confirmed by TEM images analysis. A complete list of the samples considered in this work is shown in Table 5.4.

Fig. 5.30 Schematic of the cross section of the Ni NP memory devices

Table 5.4 Design details for the samples considered in this work. Throughout this work we will refer to the 8 Â 1011 Ni NP density as “low density” and the 1.6 Â 1012 Ni NP density as “high density”

Sample code Ni NP size Ni NP density HfO2 thickness (nm) (cm−2) (nm) N81R (reference sample) –– 30 N85 4 8.0 Â 1011 30 N86 4 1.6 Â 1012 30 N82 7 8.0 Â 1011 30 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 187

Fig. 5.31 a C–V curves under sweep bias conditions for sample N85 and b the ﬂat-band voltage shift extracted from the hysteresis observed in a. The upper (lower) branch of the hysteresis loop corresponds to backward (forward) sweeps

The samples fabricated in this work show a large hysteresis at voltages below 10 V. The best performing devices were those with 4 nm Ni NPs of low-density, labeled sample N85, and in the following we will highlight the physical mechanisms underpinning this result. In Fig. 5.31 we present the C–V sweep bias measurements showing a very large hysteresis (Fig. 5.31a) and the ﬂat-band voltage shift extracted from the hysteresis curves of sample N85 (Fig. 5.31b). It should be stressed that the hysteresis loops are always counterclockwise, indicating that the NP charging is occurring predominantly because of the injection/extraction of carriers from/to the substrate. By observing that the top (bottom) branch in Fig. 5.31b corresponds to backward (forward) sweeps we are able to conclude that the top branch corresponds to the injection of electrons into the NPs from the substrate (positive biases or pulses) while the bottom branch corresponds to the extraction of electrons from the NPs toward the substrate (negative biases or pulses). It is well known that the relation existing between the ﬂat-band voltage shift and the charge injected into the NP layer is given by [9] the following equation (derived specializing Eq. 5.5 to the case of NPs):

Q DVFB ¼Àc Cox ð5:16Þ with c ¼ Xot and Q ¼ q Â \n [ Â r Â A dox where Xot is the charge centroid, dox is the total dielectric stack thickness (for sample N85 c ﬃ 0:85), q is the elementary charge (± e), is the mean number of charges stored in each NP, A is the device area, Cox is the oxide capacitance (measured in strong accumulation), and r is the NP density. The above relation can be inverted to evaluate , as shown in Fig. 5.32, and it is found that a large amount of elementary charges can be stored in each NP of these devices. For example, using 8 V sweeps, sample N85 has a memory window of 5 V which 188 E. Verrelli and D. Tsoukalas

Fig. 5.32 The memory window as a function of the bias sweep amplitude, as extracted from Fig. 5.3b, and the corresponding mean number of elementary charges per NP involved in the memory operation during one write/erase cycle

corresponds to a total number of 15 e/NP involved in the memory operation (write/erase). It is also interesting to observe from Fig. 5.31b that the top branch starts to deviate from the bottom one above *+3 V. According to Eq. 5.15 this bias corresponds to *1.2 V applied across the TO. This is a rough overestimate since we are assuming the 3 V bias to be applied directly across the insulators without taking into account the surface potential of the semiconductor, which could be in the range 0.5–1 V in inversion. This applied voltage is not able to induce the Fowler– Nordheim (F–N) tunneling through the Si/SiO2 barrier and inject electrons from the substrate. In fact, assuming that the above-mentioned barrier is 3.0 eV and given the tunneling length is 3.5 nm, the electric field needed to initiate the F–N injection would be 8 MV/cm, i.e., 2.4 V applied across the TO, which happens at *+5 V applied across the device. This causes us to conclude that, at least at these very low biases, the injection is not based on F–N tunneling but most probably to resonant tunneling with quasi-bound levels (particle in a box) located 1.2–2.0 eV below the SiO2 conduction band (CB). This value should give us an estimation of the energy level of the quasi-bound state into which electrons are injected from the substrate. We should remark that the bulk Ni work function places the Fermi energy of this material *3–3.5 eV below the SiO2 CB. Thus, the energy levels we are actually charging lie well above the Fermi energy of the bulk material and appear due to the quantum confinement of electrons resulting from the small size of the NP which is, in turn, responsible for the quantization of the energy bands. On the other hand, the bottom branch of the hysteresis loops shows that electron extraction starts at *−5 V which corresponds to *−2.0 V applied across the TO. Even if we take into consideration the surface potential of the substrate (now in accumulation) which is neglected in this estimation, we are still in the correct range where F–N tunneling can start from the quasi-bound levels. Indeed, by assuming that the effective Ni/SiO2 barrier is 2 eV and given the tunneling length is 3.5 nm, the electric field needed to initiate the F–N tunneling extraction would still be 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 189

8 MV/cm, i.e., −1.6 V applied across the TO. This analysis allows us to roughly estimate the energy location of the Ni NP quasi-bound energy levels that are involved in the memory operation. We will show in the next paragraphs that the energy location we propose allows us to qualitatively explain the charge retention behavior of these devices. As the applied bias is increased and the amount of trapped charges in the NPs correspondingly increases, Coulomb screening phenomena are expected to come into play by inducing a saturating behavior of the memory window, which is clearly depicted in Fig. 5.32 for voltages above 8 V. The NVMs based on the storage of charges in an insulating matrix are devices whose operation relies upon the charge continuity equation, JIN – JOUT =dN/dt, where N is the amount of charge in the charge storage layer, JIN is the current injected from the gate electrode into the NP layer, and JOUT is the current flowing out from the NP layer toward the Si substrate. Increasing the applied gate voltage causes N to increase but, because of the electrostatic energy acquired by the storage layer (U = N2/8peR * 0.092 eV/el. for 4 nm NPs, where e is the dielectric constant of the material used and R is the radius of the NP), dN/dt decreases. The electric field in the TO does not increase as it would have done in the absence of trapped charges, but instead is almost constant. The decrease in dN/dt means that JOUT is approaching JIN since the electric field in the CO is the field that is increasing, and Eq. 5.13 does not hold anymore. The above results demonstrate that the conditions used in sample N85 clearly provide memory behavior with a large hysteresis at low voltages. Now we wish to understand what would happen to the memory operation if we slightly change the design details of the Ni NP layer, i.e., the size and density of the NPs. Figure 5.33 shows the comparison between the memory operation of devices with Ni NPs of the same density but different size [4 nm (N85) and 7 nm (N82)], and Fig. 5.34 shows the comparison between the memory operation of devices with Ni NPs of same size

Fig. 5.33 The a ﬂat-band voltage and the b memory window of samples N85 and N82 as a function of the sweep bias amplitude. The ﬂat-band voltage is extracted from C–V sweep measurements where the upper (lower) branch corresponds to backward (forward) sweeps. The memory window in b is extracted from a for samples N85 and N82, which have identical NP densities and particle diameter sizes of 4 and 7 nm, respectively 190 E. Verrelli and D. Tsoukalas

Fig. 5.34 The a ﬂat-band voltage and the b memory window of samples N85 and N86 as a function of the sweep bias amplitude. The ﬂat-band voltage is extracted from C–V sweep measurements where the upper (lower) branch corresponds to backward (forward) sweeps The memory window in b is extracted from a for samples N85 and N86, which have identical NP sizes and low- and high-density particle distributions, respectively

(4 nm) but different densities [low (N85) and high (N86)]. It is clear that the devices with the largest memory window are the ones with low-density 4 nm Ni NPs (N85). The superior memory behavior of the devices with low densities can be explained by considering the interparticle tunneling in high-density samples. In the low-density sample the interparticle mean distance is 8.6 nm, while in the high-density sample this distance is decreased to 4.8 nm. The decreased interparticle distance could enhance the tunneling of electrons among neighboring particles and thereby lower the efﬁciency of the memory devices compared to low-density ones. This interparticle tunneling could also play a role in explaining the superior memory behavior of devices with smaller particles since the interparticle distance in the 7 nm Ni NP sample is 5.6 nm, much less than the 8.6 nm distance found in the 4 nm Ni NP sample. Although a *5 nm interparticle distance might seem too large for tunneling to occur, it is the concomitant presence of a small barrier between the Ni NP quasi-bound state and the HfO2 (estimated to be *0.5 eV) that makes the tunneling probability large enough to become appreciable. Another possible effect that could explain the smaller memory window of the N82 devices can be revealed through the charge continuity equation, JIN − JOUT =dN/dt. The less steep memory window curve of sample N82 (Fig. 5.7b) indicates that we are approaching saturation earlier than in sample N85. This means that JOUT in N82 is much larger than in N85 (for the same biases) which highlights a possible degradation of the CO deposited onto the larger sized NPs. This argument could also be used for the high-density sample, N86, as evidenced by the I–V measurements performed on the devices and shown in Fig. 5.35. Both the high-density sample and the 7 nm NP sample show leakage currents much higher than the N85 sample, indicating the possibility of CO with deteriorated quality induced by the higher roughness of the surface onto which it was deposited. 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 191

Fig. 5.35 I–V characteristics at room temperature of the reference device N81R (black) and a samples N85 (red) and N82 (green) showing the NP size effect, and b samples N85 (red) and N86 (green) showing the NP density effect

Fig. 5.36 The charge retention of sample N85 found by measuring the ﬂat-band voltage for the write (+6 V) and erase (−8V) states as a function of log(t). The extrapolation of the ﬂat-band voltage to t = 10 years shows that the extrapolated memory window should be around 0.5 V

A fundamental property of an NVM is charge retention in the absence of any bias. In order to perform the charge retention measurement on sample N85, the device is first charged in one of the two possible states (positively or negatively charged) and the flat-band voltage shift is monitored for at least 24 h. Figure 5.36 shows the charge retention measurement for sample N85. These charge loss measurements are consistent with the tunneling discharge [73, 74] because a linear charge loss behavior is observed against log(t). Extrapolating to 10 years’ retention time, we observe that the extrapolated memory window is *0.5 V. The charge loss rate for the write state is 373 mV/dec while that of the erase state is much lower, at 186 mV/dec. These charge loss rates are quite large, especially that of the write state (+6 V), and clearly fit the model placing the quasi-bound state in the Ni NPs just 2 eV below the TO CB, i.e., almost at the edge of the CO CB. According to the proposed model, during write retention the charges could escape either by tunneling through the TO toward the substrate or through the very low CO barrier toward the 192 E. Verrelli and D. Tsoukalas gate. On the other hand, during erase retention the only way charges could be lost is the tunneling of electrons from the substrate through the TO. This process is much less probable than the corresponding effect during write retention because of the higher 3 eV barrier (as compared to 2 eV), thus giving an explanation for the smaller charge loss rate of the erase state compared to the write state.

5.4.2 Pt NPs Prototypes

The disadvantage in using Nickel, as mentioned in the previous section, is that it has the tendency to oxidize and for this reason the nanoparticles generated with our system seem to have an Ni core with an NiO outer shell. In order to avoid such oxidation of the nanoparticles, the target material was changed to platinum which, at the temperature considered here, does not react with oxygen and also provide a higher work function respect to nickel. The cross section and the band diagram of the ﬁnal memory device are shown in Fig. 5.37. The TO was always a 4 nm thermally grown SiO2 and the HfO2 CO had a thickness of 20 nm. Four conditions have been considered here and are summarized in Table 5.5. These conditions should give further insight on the effect of nanoparticle size and density on the electrical behavior of the Pt NVM devices which will be presented and analyzed in the next sections.

Fig. 5.37 a Cross section of a platinum nanoparticle memory device, b band diagram of a for VG =0V

Table 5.5 Platinum Sample Pt NPs density Pt NPs size (nm) nanoparticles density and size * Â 11 −2 * for the four memory devices A1 3 10 cm 6 11 −2 fabricated A2 *5 Â 10 cm *6 B1 *1 Â 1012 cm−2 *2 B2 *2 Â 1012 cm−2 *2 Ref. –– 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 193

5.4.2.1 Samples A1 and A2 (6 nm NPs)

The C–V sweep bias measurements performed on these samples revealed that charging starts at *4 V. The ﬂat-band voltage shifts extracted from the above measurements are shown in Figs. 5.38 and 5.39 for samples A1 and A2, respectively. Sample A1 presents slightly smaller hysteresis widths than A2 for same sweep bias amplitude. For instance, for 8 V sweeps, A1 presents a hysteresis width of *2 V while A2 * 2.6 V. According to the nominal fabrication parameters and in particular to the almost double nanoparticle density in A2 respect to A1, someone would expect an almost double hysteresis width in A2 respect to A1. The experimental ﬁndings, although they show an increase in the hysteresis width for

Fig. 5.38 Flat-band voltage shift as function of the sweep bias amplitude as extracted from C–V sweep measurements for sample A1

Fig. 5.39 Flat-band voltage shift as function of the sweep bias amplitude as extracted from C–V sweep measurements for sample A2 194 E. Verrelli and D. Tsoukalas

Fig. 5.40 Comparison of the leakage currents in A1, A2, and reference sample (no nps) increased density, do not confirm the above expectations. Furthermore, A2 shows above 8 V a drift in the memory characteristic, already observed in Ni samples, that might indicate high leakage currents through the gate oxide. Also in the case of Ni nanoparticles, the diameter considered was *6 nm and density similar to those of A2. This observation might indicate that the nanoparticle size and density affects the quality of the hafnium oxide film grown on top of the nanoparticle layer. TEM analysis has shown that the hafnium oxide layer has a disordered structure with large grains which must be the reason of the leakage deduced from the hysteresis plots and that is also confirmed by I–V measurements shown in Fig. 5.40. When compared to the reference sample, A2 shows a leakage current more than 3 orders of magnitude higher. The high leakage present in sample A2 is responsible for the very small charge retention time of the order of 104 s, as shown in Fig. 5.41.

5.4.2.2 Samples B1 and B2 (2 nm NPs)

Samples B1 and B2, with much smaller nanoparticles than A1 and A2, present much better electrical performance. The C–V sweep bias measurements performed on these samples revealed that electrons injection into the NPs starts at *2 V. The ﬂat-band voltage shifts extracted from the above measurements are shown in Figs. 5.42 and 5.43 for samples B1 and B2, respectively. Sample B2 has a nominal NP’s density that is twice the density in B1, thus as in the previous section, a double hysteresis width is expected in B2 respect to B1. The above expectation is reasonably conﬁrmed this time by the measurements since, for instance, 8 V sweeps produce a hysteresis of *2.5 and *1.5 V in B2 and B1, respectively. Taking into 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 195

Fig. 5.41 Charge retention in sample A2 after a gate pulse with height +8 V and duration 1s

Fig. 5.42 Flat-band voltage shift as function of the sweep bias amplitude as extracted from C–V sweep measurements for sample B1

Fig. 5.43 Flat-band voltage shift as function of the sweep bias amplitude as extracted from C–V sweep measurements for sample B2 196 E. Verrelli and D. Tsoukalas consideration the discussion concerning the role of leakage in A samples, the above result might indicate that in the B samples leakage through the hafnium oxide layer does not affect so heavily the operation of the devices. Indeed TEM analysis confirmed that the hafnium oxide in B2, unlike A2, does not have any large grains that might favor leakage. As already evidenced in Chap. 3, also in B2 the hafnium oxide has a columnar polycrystalline form clearly highlighted by the dark field TEM image. In the TEM analysis of B samples was not possible to identify the Pt nanoparticles mainly for three reasons: (1) because of their small size (*2 nm), (2) because of the bad signal/noise ratio of the TEM system, (3) the low contrast between Pt and Hf. Leakage current measurements (Fig. 5.44) agree with the previous observations since the leakage currents of B samples are very similar to the one of the reference sample. Recalling the problems with A samples, we can thus conclude safely that indeed the size of the nanoparticles affects the quality of the hafnium oxide layer grown on top of the nanoparticle layer. The behavior under pulsed regime of B2 is presented in Fig. 5.45. The flat-band voltage shift after

Fig. 5.44 Comparison of the leakage currents in B1, B2, and reference(no nps) samples

Fig. 5.45 Memory behavior under pulsed regime for pulse durations of 1 s and 10 ms on sample B2 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 197

Fig. 5.46 Charge retention measurements for the write and erase state of sample B2

positive (upper branch) and negative (lower branch) pulses of duration 1 s show larger memory windows than in sweep bias measurements as was already observed in Si NC memories. +8 V/−8 V 1 s pulses correspond to a memory window of *4 V. Charge retention measurements for B2 are presented in Fig. 5.46 for positive and negative pulses with duration 1 s. The electron retention time is deﬁnitely much longer than in A2 but still below the 10 year limit. The improvement observed in charge retention has to be ascribed mainly to the use of smaller nanoparticles which allow for a better quality hafnium oxide ﬁlm.

5.4.3 Au NPs Prototypes

Our work on Ni NPs NVMs and Pt NPs NVMs has clearly pointed out the challenges in the fabrication of efﬁcient NP-based NVM devices and it has become clear that in order to improve nonvolatility the NPs used have to be as small as possible and as dense as possible but always keeping in mind the CO degradation effects that show up with using large-sized or high-density NP layers. Although Au NPs make no exception to the above results, they also show peculiar characteristics that we will discuss in this section. The peculiarity we refer to has its origins in the capability that Au nano-objects have to coalesce and modify their arrangement at substrate level. The devices considered here are MOS diodes, as shown in Fig. 5.47a–b, with the following gate structure: a p-Si substrate, a 3.5-nm-thick TO of thermally grown SiO2, a layer consisting of Au nanoclusters formed by nucleation and coalescence of Au NPs deposited by a room temperature physical process, followed by the deposition of an insulating layer of 20 nm of HfO2 by RF sputtering. In the next section, will be shown that the generated NPs have initially a mean diameter of 1.3 nm. A reference device was also fabricated by omitting the NP deposition step. A pure Au target was used at a sputtering power of 30 W with an Ar ﬂow of 75 sccm. By varying the deposition time it was possible to vary the NP load in the range 0–1 lg/cm2 and fabricate in such a way four different samples, A to D, with 198 E. Verrelli and D. Tsoukalas

Fig. 5.47 a schematic of the memory devices fabricated; b band diagram of the devices in b

Table 5.6 The samples considered in this work differ only by the amount of Au NPs deposited on the tunneling oxide, which was realized by simply increasing the deposition time. The load is theoretically defined as the film thickness multiplied by the material’s density: Load = thick. Â density. A 1-nm-thick Au thin film corresponds to a load of 1.93 lg/cm2 Sample Reference A B C D Tunneling Oxide 35 35 35 35 35 (Å, SiO2) NPs Load (lg/cm2, Au) 0 0.209 0.532 0.810 1.231 Control Oxide 200 200 200 200 200 (Å, HfO2) increasingly higher NP load as shown in Table 5.6. As will become clear in the next section, the above conditions drove to NP densities in the range 1012–1013 cm−2. The hafnium oxide in the devices was deposited from a high-purity HfO2 target at a sputtering power of 200 W with an Ar flow of 60 sccm and O2 flow of 10 sccm. A quartz crystal monitor was positioned close to the samples during the sputtering depositions, allowing us to monitor precisely and in real time the amount of material deposited. A complete list of the samples considered in this work is shown in Table 5.7. From TEM plane view images analysis of the samples A–D prepared in this work it is possible to extract the statistical information of the lateral size

Table 5.7 Data concerning Au NP Sample A B C D the properties of the Au NP l 2 films as extracted analyzing Load ( g/cm ) 0.21 0.53 0.81 1.2 12 −2 the TEM images of the four Density (Â10 cm ) 3.5 5.1 4.2 2.9 samples considered in this Mean diameter (nm) 1.6 2.0 2.4 2.9 work Diameter st. dev. (nm) 0.54 0.64 0.78 1.2 Film coverage 0.077 0.17 0.21 0.22 Nearest neighbor distance (nm) 3.7 3.3 3.8 4.4 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 199 distributions and results are summarized in Table 5.7 and should support the idea of a nucleation and subsequent coalescence processes taking place on the landing substrate, a known characteristic of Au NPs. The results show that the average NP size increases with load while the NP areal density does not change too much. On the other hand it is observed an increase of the size dispersion for increasing load. The NP density increases from sample A to sample B (maximum), which we argue characterizes the nucleation regime, and then decreases for sample C and also for sample D, which we speculate that could represent the coalescence regime. The above claim is further supported by the dependence upon the load of the nearest neighbor distance (NN) data obtained analyzing the TEM images with the GIAS software [75]. It is interesting how also in this case it is possible to distinguish between two clear growth regimes: during nucleation (A–B) the NN distance decreases while during coalescence (B–D) the NN distance increases steadily. The NP lateral size increases almost linearly with the load and, by extrapolating to 0, it is also possible to infer the average diameter of the NP generated from the cluster beam which is estimated to be 1.3 nm. Finally, the sample coverage clearly presents a saturating behavior toward 0.23–0.24 for increasing NP load. The physical characteristics of the nanocluster film that affect the final performance of a nonvolatile memory are the NP size, shape, density, and average nearest neighbor distance. These parameters have often opposite effect over device performance although the main idea is always to have, for any given size of the NPs, the highest NPs’ areal density possible under the constraint of a nearest neighbor (NN) distance greater than *3.5 nm. Pedersen et al. [76] have shown that such a value represents the boundary separating the highly resistive tunneling regime (NN distance greater than 3.5 nm) from the highly conductive percolation one (NN distance smaller than 3.5 nm) for the electronic transport through 2D assemblies of Ag NPs deposited using a system similar to the one used in this work. Thus the 3.5 nm limit roughly assures that no lateral relevant charge loss may occur. The number of charges that can be stored into an NP, for the same given charging energy, increases with NP size (or number of atoms) [77] but large NPs represent an obstacle to the aggressive scaling of NVMs and they may also require thicker COs, thus higher operating voltages, so NPs with diameter below 5 nm are preferred [78]. Using small NPs means that their areal density can be increased and thus the same does the amount of charge/cm2 that the device can store but up to a point where the nearest neighbor distance becomes lower than the 3.5 nm limit mentioned above when lateral charge loss may cause a degradation of the performance. Regarding the shape of the NP, it is obvious that for a given lateral size of the Au NP (the one measured in plane with the NP layer, which is the dimension subject to the nearest neighbor distance constraint), the sphere is the NP shape among the possible shapes for an Au NP, i.e., island, hemisphere or sphere, that provides the largest volume or number of atoms and thus maximizes also the number of charges that can be stored into the NP. Since the seminal work of Buffat and Borel [79] and subsequent improvements like the one from Plech et al. [80], it is now well established that the melting temperature as well as other physical quantities of NPs are inversely related to their size [81]. In a similar manner, 200 E. Verrelli and D. Tsoukalas

Fig. 5.48 a C–V sweep bias measurements on sample A showing the very large hysteresis obtained at relatively low voltages; in the inset is shown the corresponding behavior of the reference device; b flat-band voltage shift as extracted from (a) quantum mechanical quantities like the density of states, the energy gap, etc., strongly depend on the dimensionality of the nanostructure considered, as pointed out by Sattler [82]. Nevertheless, it suffices to recall that the above statement is a direct consequence of the particle-in-a-box model and it was recently shown by Schouteden et al. [83] that such model is valid for both Au nanowires and Au nanoislands. In Fig. 5.48a are shown the results from C–V measurements carried out on sample A showing very large hysteresis at relatively low sweep amplitudes. It should be noted that the hysteresis is counterclockwise indicating that charges are injected/extracted mainly from/to the Si substrate. A clearer picture of the dependence of the hysteresis or memory window upon the sweep amplitude is obtained from Fig. 5.48b where are plotted the flat-band voltages extracted from the C–V curves. In this graph, the top branch corresponds to backward sweeps, i.e., to electron injection while the bottom one to forward sweeps, i.e., to electron extraction. It is clear that electron injection starts at voltages as low as +3.0 V while electron extraction at −4.0 V. In order to gain insight into the physics behind this result it should be stressed that the low voltages achieved in this work are result of the device structure. The advantage of using a mixed dielectric stack in the nonvolatile memory scheme, with silicon dioxide as the tunneling oxide (TO) and hafnium oxide as the CO, is the reduction of the voltage required for the writing/erasing operation of the memory device. From simple electrostatic arguments, it can be shown that the use of a high-k material for the CO results in an enhanced electric field in the TO for the same applied gate voltage [84]. Indeed, Å Å using Eq. 5.15, assuming dSiO2 =35 and dHfO2 = 200 , which are the design ¼ : parameters used in this work, and by considering that EOTHfO2 6 7 nm in this D ¼ a Â D ffi % Â D work, it turns out that VSiO2 V 34 V. Using the above relation, it is possible to show that the +3 V electron injection onset bias cannot be explained by F–N tunneling and the reason is that such a bias 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 201 voltage is too low. Indeed, considering that *0.8 V are lost across the p-Si substrate in inversion, the above-mentioned +3 V would correspond to *2.2 V across the oxide stack and thus to *0.75 V across the TO, i.e., to an electric field of 2.1 MV/cm in the SiO2, according to the above equations. On the other hand, F–N injection from the Si CB through the TO (barrier height 3.2 nm and length 3.5 nm) would start at *7–8 MV/cm [85] which would have required a much higher bias voltage. Thus we could speculate that at least at such low voltages the injection of electrons into the AU NPs is dominated by resonant tunneling between the Si conduction band and a quasi-bound state in the Au NPs, while at voltages much higher than +3 V both D–T and F–N could be responsible for the injection of electrons. Recalling that the work function of bulk Au is 5.1 eV [86], the electron affinity of SiO2 is 1.0 eV [87] and the Si-SiO2 barrier height is *3.2 eV, it is possible to evince that while the Fermi level of the bulk Au would be 4.1 eV below the CB of the TO, the quasi-bound state mentioned above should be *2.5 eV below the CB of the TO (difference between the TO CB and potential energy lowering due to the 0.75 V across the TO). Quantum confinement [82] should be responsible for the fact that the first available electron state in these small Au NPs is *1.6 eV above the Fermi level of the bulk material. On the other hand, the onset of electron extraction is at *−4.2 V which corresponds to *1.4 V across the TO. Since the quasi-bound state/SiO2 barrier is *2.5 eV, it is possible to realize that the onset of extraction correspond to the onset of the F–N tunneling from the quasi-bound state toward the Si substrate. In Fig. 5.49a are shown the evolutions with the sweep bias amplitude of the flat-band voltage for forward (electron extraction) and backward (electron injection) sweeps while in Fig. 5.49b are shown the memory windows as extracted from Fig. 5.49a. Similar results hold for the measurements performed under a pulsed regime. From these figures it is clear that the memory window of our samples improves as the NP load is increased. In our case though the load is not affecting

Fig. 5.49 Comparison of the C–V sweep bias measurements results on the samples mentioned in Table 5.6; a and b Flat-band voltage shift as a function of the sweep amplitude showing that as the Au NP load increases, the corresponding memory window (hysteresis) increases as well 202 E. Verrelli and D. Tsoukalas

Fig. 5.50 a The number of elementary charges/NP as a function of the sweep amplitude as extracted from Fig. 5.49a and using the data obtained from the TEM analysis. At each bias, the most efficient memory devices are in D (highest load, i.e., largest NPs and largest size dispersion) while the least efficient are in B (onset of coalescence). b Total number of elementary charges/NP involved in the memory operation during a backward/forward sweep with a given amplitude. Note that in a the top branch corresponds to electron extraction while the bottom one to electron injection just one NP property, i.e., the areal density but, as explained in the previous section, all of them, i.e., NP size, density, and size dispersion are all affected by the increasing load. Thus, in order to normalize the data respect to the areal density (in order to eliminate the dependence upon the parameter that is neither constant nor linearly dependent upon the load), following Eq. 5.16, the flat-band voltage shifts and the memory window plots have been translated into the corresponding number of elementary charges (electrons) per NP that we present in Fig. 5.50. The most striking feature that arises from these graphs is that the devices in sample D (largest NPs) seem to be by far the most efficient ones while the devices in sample B (onset of coalescence) seem to be the least efficient. A last remark concerns the dependence from the size of the NPs of the onset bias of electron injection/extraction into the NPs. As shown in Fig. 5.51, the write (W) onset voltage extracted from Fig. 5.49 decreases for increasing NP load, i.e., NP size. From sample A (1.6 nm) to sample D (3 nm) the onset voltage decreases of *1 V which, according to the electrostatic of the devices, corresponds to a lowering in the Au NP quasi-bound energy level of *−0.35 eV which is qualitatively in agreement with quantum confinement effects. According to the particle in a 3D box model, the expected energy change of the quasi-bound energy level is given by the following equation:

p2n2 1 1 D ! ¼ ð À Þ; ð : Þ EA D 2 2 5 17 2me RD RA where RD and RA are the average radius of NPs in samples A and D, respectively. Using the above equation the estimated lowering would be *−0.4 eV which, 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 203

Fig. 5.51 Dependence of the voltage corresponding to the onset of the write (W) and erase (E) from the load

considering the approximation of the model and the experimental errors, is in very good agreement with the experimental result. On the other hand, quite unclear is yet the behavior of the erase (E) onset voltage. Indeed, a lowering of the quasi-bound energy level for increasing load should induce, together with a lowering of the W onset voltage, an increase in the voltage required to erase the devices (due to the higher barrier electrons have to overcome) while it seems that such voltage is rather constant for increasing load. The devices fabricated in this work show nonvolatility in their memory behavior. For this reason, the performance of these devices under a pulsed regime has been investigated and results are shown in Fig. 5.52. Using pulses of 8 V amplitude and duration of 10 ms, the charge retention time was also estimated for both the write

Fig. 5.52 Evolution of the ﬂat-band voltage shift with the pulse width used to program the devices on sample A 204 E. Verrelli and D. Tsoukalas

Fig. 5.53 a Charge retention measurements performed on the four samples with programming pulses of 8 V and duration of 1 s. The measurements were performed at room temperature in the dark on fresh devices. The four samples present very similar behavior with excellent retention and a 10-year extrapolated window of *3 V. The estimated charge loss is less than 40%. b Charge loss rate as a function of the load for both the erase and the write states during the initial 1000 s of the retention measurements shown in a; it is clear that the increasing load induces an increased loss rate of the write state while the erase state remains reasonably unaffected and erase states as shown in Fig. 5.53a. Measurements are carried out by charging a device in one of the two states and then following the evolution with time for *24 h of the ﬂat-band voltage of the MOS capacitor. The four samples show an extrapolated memory window at 10 years retention period of *3 V which, compared to the initial *5 V window, indicates a charge loss of *40%. It should be noted that the above-mentioned charge loss is all concentrated during the ﬁrst 3 h of the retention period. Further analysis of the retention characteristics, Fig. 5.53b, reveals that the charge loss rate for the write state almost doubles between samples A and D while the charge loss rate for the erase state is practically independent from the load and its magnitude is quite smaller than the corresponding values of the write states. A possible explanation for the latter arises by identifying the cause of the loss of the stored charge: in erase retention (NP positively charged) it is the tunneling of electrons from the Si CB through the TO barrier (3 eV) while in write retention (NP negatively charged) it is the tunneling of electrons from the NP quasi-bound state through the Au NP/TO barrier (*2 eV) or through the Au NP/CO barrier (*0.5−1 eV). Thus it is a higher tunneling barrier that makes the magnitude of the charge loss rate in erase state retention much smaller than the one for the write state. The above conclusion is also in agreement with results concerning Ni and Pt NP NVMs. Regarding the reason why the charge loss rate of the write state increases for increasing load, we should note that this result is rather surprising but again explanations as those given for the case of Ni and Pt NP NVMs could be valid also in this case. 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 205

5.5 Comparison of Flash-like NVMs Based on Metallic NPs

Using an optimized high-k CO, it is possible to use the previously mentioned Ni, Pt, and Au NPs films to produce Flash-like NP NVMs with very large hysteresis and low operating voltages. We focus here on the smallest NPs, i.e., agglomeration zone lengths corresponding to position 0, and NP densities in the range of 1012 cm−2. More specifically, in Fig. 5.54 are presented the C–V sweep bias measurements carried out on Ni, Pt, and Au NP NVM with the following device structures: Ni) TO with thickness of 3.5 nm, Ni NP layer with density of 8 Â 1011 cm−2 and mean diameter 4 nm, CO with thickness of 30 nm; Pt) TO with thickness of 3.5 nm, Pt NP layer with density of 2.8 Â 1012 cm−2 and mean diameter 2.3 nm, CO with thickness of 20 nm; Au) TO with thickness of 3.5 nm, Au NP layer with density of 3.5 Â 1012 cm−2 and mean diameter 1.6 nm, CO with thickness of 20 nm. As general remarks we should note that the three samples mentioned above show (1) very large hysteresis of 7–8 V at voltages below 10 V and (2) counterclockwise hysteresis which denote that the charging/discharging processes are dominated by the injection/extraction of carriers from/to the Si substrate. Furthermore the three samples show the characteristic saturating behavior of the flat-band voltage shift as “high” enough voltages are approached (in the Au case the saturation is much more clear for plots up to 12 V) which is the signature of the coulomb blockade effect. In principle the work function of the metal used to produce the NP layer should help in understanding the charging/discharging process and generally the operation of the NVM devices but we should also recall that the work function is a parameter that relates to bulk materials and thus, as mentioned in the introduction, it might differ sensibly from the real energy location of free quantum states in NPs as small as those discussed in this section (the smaller the NP the higher will be the actual energy of the first available quantum state). The above observation allows us to understand the results shown in Fig. 5.55a where is shown the memory window of the devices as extracted from Fig. 5.54b, d, and f. The estimated turn-on voltage of the charging/discharging process is extremely low, in the range 2.7–3.7 V; it is interesting to note that although Au and Pt have very similar work functions (−5.1 eV for Au and −5.65 eV for Pt [88]), the devices with the lowest turn-on voltage are clearly those with Pt NPs. We believe that this result is not just orig- inated from the slightly smaller work function of Pt compared to that of Au but also from the slightly different NP sizes between Au and Pt samples: 1.6 nm for the Au sample and 2.3 for the Pt sample. We believe that it is the quantum confinement effect, more intense in the Au NPs rather than in the Pt NPs, that adds up to the small work function difference and determines a *1 V lower turn-on voltage in Pt devices compared to Au ones. The graph in Fig. 5.55b allows us to discuss another important point in the design of NP NVMs which is related to the size and density of the NPs. Larger NPs, like the Ni NPs in this section, show a weaker quantum confinement effect and have higher density of states which can accommodate much more charges than smaller NPs. This is clearly represented in Fig. 5.55b. It would 206 E. Verrelli and D. Tsoukalas

Fig. 5.54 a, c, e Symmetric C–V sweep bias measurements performed on Flash-like NP NVMs with Ni, Pt, and Au NPs, respectively. b, d, f ﬂat-band voltage shift as extracted from the corresponding C–V curves in the same ﬁgure. Note that the top branch corresponds to electron injection from the Si substrate in the NPs through the TO while the bottom branch corresponds to the extraction of electrons from the NPs toward the substrate 5 Nanoparticles-Based Flash-like Nonvolatile Memories … 207

Fig. 5.55 a Memory window of the Ni, Pt, and Au NP NVMs as extracted from Fig. 5.54; the estimated “turn-on” voltage is also shown; b plot of the total number of elementary charges exchanged by each NP during a complete C–V sweep, as extracted from (a) seem at this stage that it is better to use NPs with diameter 4 nm rather than 1–2 nm. Except the obvious disadvantage in terms of scaling, it has been shown in the previous sections that in an attempt to increase the memory window of NVMs using large NPs by increasing their density, actually it drives to a quick deterioration of device performance due to increased roughness of the NP layer and the creation of percolation paths. In order to obtain devices with large memory windows it is mandatory to use NPs with diameters in the range of 1–3 nm and optimized densities, generally as high as possible but such to keep the nearest neighbor distance above a certain limit that according to our investigations, should be around few nanometers.

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C O Cluster beam, 158, 160, 163, 186, 199 Organic memory devices, 124, 136, 147, 151 Coulomb Blockade, 60 Organic metal insulator semiconductor, 129 Organic thin ﬁlm memory transistors, 136 D Data retention, 30 P Dielectrics for NVM, 164 Pentacene, 129–131, 136, 137, 143, 144, 147

F R Flash memory structure, 73, 74, 81 Redox molecules, 95 Flexible electronic, 69, 80 Resistive switching, 128 Floating gate, 124, 125, 127, 129–137, 139, 140, 143–145, 147 S Silicon nanowires, 62 H Single walled carbon nanotubes, 129, 134, 135 History of SONOS, 1, 4, 6, 7, 15, 27 Sputtering, 158, 160, 161, 164, 176, 197 SWCNTs as charge traps, 148 L Leakage current, 17, 174, 176, 180, 194, 196 T TANOS device, 34 N Temperature acceleration, 31 Nanoparticles, 157, 186, 192, 194, 197 Trapping, 164, 165, 172, 174 Nanotechnology and nanomaterials, 55, 61 Trap memories, 45, 49 NVM Roadmap, 51 2T cell, 13