C) Solution Processed Tunable Flash Memory Device Without Tunneling

Low temperature (< 200◦C) solution processed tunable flash memory device without tunneling and blocking layer Sandip Mondal1;2, V Venkataraman2 1SanDisk India Device Design Center, Bangalore 560103, India and 2Department of Physics, Indian Institute of Science, Bangalore 560012, India Intrinsic charge trap capacitive non-volatile temperature[28]. However the high temperature heating flash memories take a significant share of the process lowers leakage current but reduces trap density. semiconductor electronics market today. It is a Hence, the main challenge is to simultaneously achieve challenge to create intrinsic traps in the dielec- deep intrinsic charge traps together with very low leak- tric layer without high temperature processing age current at low processing temperatures. There are a steps[1]. While low temperature processed mem- few reports on solution processed flash memory by using ory devices fabricated from polymers have been polymer materials[29, 30], but these devices degrade af- demonstrated as an alternative[2{7], their per- ter only few cycles of operation in normal environmental formance degrade rapidly after a few cycles of conditions and they are not capable of working at higher operation[8{14]. Moreover conventional memory temperatures. devices need the support of tunneling and block- In the last few years, a novel inorganic, completely ing layers since the memory dielectric or polymer carbon free, water soluble dielectric Aluminium Oxide is incapable of preventing memory leakage[15{17]. Phosphate (ALPO), has been successfully employed as The main issue in designing a memory device gate dielectric in high performance TFTs that are com- is to optimize the leakage current and intrinsic petitive with a-Si TFTs[31]. Due to its very low leakage trap density simultaneously[18]. Here we report current density, it was used recently as tunneling and a tunable flash memory device without tunneling blocking layer to fabricate fully solution processed two and blocking layer by combining the discovery of terminal capacitive flash memory devices[32] with CdTe- high intrinsic charge traps (>1012 cm−2) together NP as the charge storage center. Nevertheless a fully with low leakage current(<10−7 A.cm−2) in so- spin−coated low temperature processed (below 200◦C) lution derived, inorganic, spin−coated dielectric high−performance flash memory device without tunnel- films which were heated at 200◦C or below. In ing and blocking layers has not been reported so far. addition, the memory storage is tuned systemat- Here we report the discovery of ultra-high number of ically upto 96% by controlling the trap density intrinsic charge traps (>1012cm−2) in low temperature with increasing heating temperature. solution processed inorganic ALPO dielectric. At the Today's semiconductor memory technology is dom- same time, the leakage current is sufficiently low (< 10−7 inated by silicon-oxide-nitride-oxide-silicon (SONOS) A.cm−2) for flash memory operation without incorporat- non-volatile flash memory which is based on intrinsic ing tunneling or blocking layers. In addition, the number charge traps in silicon-rich silicon nitride films deposited of traps can be varied with heating temperature, which is by high temperature (∼ 780oC) compatible chemical va- strongly correlated with the oxygen vacancy concentra- por deposition[19, 20]. The intrinsic charge traps in tion in the film. Furthermore, we demonstrate optimized silicon-rich silicon nitride films were first reported in 1967 robust high performance fully solution processed inor- [21] and the first flash memory device incorporating sil- ganic oxide precursor based flash memory devices with- icon nitride charge storage was demonstrated in 1980's out tunneling and blocking layer, where the processing [22]. However the trap density and distribution are dif- temperature does not exceed 200◦C. Our devices outper- ficult to control in such material[23]. Traps can be in- form other similar memory devices reported earlier[2{7]. creased by ion bombardment and plasma-passivation[20], A schematic of typical device architecture is depicted in but the leakage current increases. Alternate high-k di- Fig. 1a. ALPO is deposited by spin-coating a completely electrics such as TiO2, HfO2, ZrO2, etc. are excellent inorganic, carbon free and aqueous precursor solution on insulators for transistor applications [24{27], but do not low-doped p-silicon substrate (p ∼4×1015 cm−3). After have the intrinsic charge trapping properties as silicon ni- deposition various substrates are heated at different tem- ◦ tride. Although solution processed HfO2 has been used peratures including at low temperature such as 200 C. arXiv:1902.10076v1 [physics.app-ph] 26 Feb 2019 to fabricate SONOS type flash memory[1], the devices The inset of Fig. 1a shows a schematic of molecular struc- required the support of additional dielectric layers which ture of the low temperature (200◦C) processed ALPO. were deposited by sophisticated ultrahigh vacuum tech- The thickness of the deposited film is measured by el- niques with high temperature processing steps to improve lipsometry (see Section I, Supporting Information) and the memory leakage. For most dielectrics, precursor solu- verified by cross-sectional scanning electron microscope tions with organic solvents result in poor leakage current (SEM) image (Fig. 1b). Such prepared films are found which can be improved to some extent by high heating to be atomically smooth showing surface roughness to be 2 nm (a) (b) (c) 0.9 500 nm 0.6 0.3 ALPO 20 µm 0.0 p-Si Al H O P (d) (e) 12.9 V 17.5 V 2.2 V FIG. 1. Device and deep level charge trapping response: (a) Schematic of device architecture. (b) Cross-sectional SEM image of a typical device (thickness ∼139 nm). (c)(top-panel) AFM topography of the surface of the devices. (bottom-panel) Optical image of an array of devices. (d) C − V traces of as prepared (AP), heated at 200◦C and 600◦C respectively (also see Section II, Supporting Information). The heating was done for 1 hr for each sample. C − V was measured with the up-down DC sweep of ± 20 V at a rate of 2V min−1 on the gate (Gate Bias) of the MIS while imposing a small AC with amplitude and frequency of 100 mV and 100 kHz respectively. (e) Variation of hysteresis window (4VFB ) as a function of heating temperature. (inset) variation of trap density as a function of heating temperature. ∼0.08 nm[28, 33] which is determined by the atomic force tion of the CV curve it is inferred that gate injection of microscopy (AFM) with an areal scan over 50µm×50µm carriers controls the memory operation. Although con- (top-panel,Fig. 1c). An aluminum contact is deposited ventional flash memory architecture follows channel in- thereafter by thermal evaporation for the purpose of elec- jection of carriers[20], the interface degrades fast in such trical measurement. The deep level charge storage in the devices[34]. Thus, compared to channel injected devices, deposited ALPO is characterized via capacitance-voltage gate-injected devices show higher endurance which is one (CV) measurement. An optical image of device on chip of the key requirements of memory operation[35]. Be- has been shown in the bottom-panel of Fig. 1c. cause of such advantages, the quest for efficient gate- injected flash memory devices is ongoing[34{37]. A sys- Intrinsic trap levels in ALPO cause a hysteretic out- tematic change in the hysteresis window as a function of put of the CV traces highlighting the memory-like be- heating temperature is presented in Fig. 1e, where, solid havior of the devices (Fig. 1d). Further, the trap den- squares are the experimental data, shaded region is guide sity can be varied by heating the samples at different to the eye and the width of the shaded region indicate temperatures which alters the hysteresis-window. For the standard deviation around their mean vertical posi- example, an as-prepared sample shows a memory win- tion estimated from similar results. Use of higher heat- dow of ∼12.9 V (left-panel) which corresponds to a trap ing temperature (> 600◦C) causes a dramatic reduction density of n ∼5.65×1012 cm−2, where as, an ALPO-film in trap density, thus reducing the hysteresis window. A heated at 200◦C for one hour shows a hysteresis window 96% reduction in trap density (n ∼ 2:19×1011 cm−2) is of ∼17.5 V which corresponds to the trap density of n ∼ observed at an heating temperature of ∼800◦C resulting 6.37×1012 cm−2. When the film is heate at 600◦C, the a memory window of 0.7 V only. In addition, a negli- trap density drastically reduces (n ∼ 1011 cm−2) causing gible degradation in CV hysteresis is obtained from as a significantly low hysteresis window (∼ 2:2 V, right- prepared devices even after 5 years of storage in ambi- panel). A similar variation of electronic traps with heat- ent conditions (see Section IV, Supporting Information). ing temperature is also observed from the devices which This demonstrates that the devices are very stable for are made with lower thickness ALPO film, however, there long term application, in spite of the water absorbing is no affect due to change in device dimension (see Sec- property of ALPO[38, 39]. tion III, Supporting Information). From the sweep direc- 3 (a) (b) (c) t Program (P) +V1 +V2 Read -V2 Erase (E) -V1 t FIG. 2. Program-Disturb(PD) Measurement: (a) PD measurement with 20 times C − V sweep on same device. Inset: th C − V curve of first and 20 measurement. (b) Flatband voltage shift (∆VFB ) as a function of gate sweep voltage and frequency of sweep voltage. (Inset) Charge density (nALP O) variation as a function of gate voltage (VG).

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