Explanation of the Charge-Trapping Properties of Silicon Nitride Storage

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011 2483 Explanation of the Charge-Trapping Properties of Silicon Nitride Storage Layers for NVM Devices Part I: Experimental Evidences From Physical and Electrical Characterizations Elisa Vianello, Francesco Driussi, L. Perniola, Gabriel Molas, Jean-Philippe Colonna, B. De Salvo, and Luca Selmi

Abstract—In part I of this paper, we study the physicochemical and their superior scaling capabilities compared with standard structure and the electrical properties of low-pressure-chemical- floating-gate Flash memory devices. Moreover, the program vapor-deposited silicon nitride (SiN) aimed to serve as storage and erase (P/E) operation by hot carriers and the possibility of layers for nonvolatile memory applications. An in-depth material analysis has been carried out together with a comprehensive multibit storage can be exploited to further increase the storage electrical characterization on two samples fabricated with recipes density [5], [6]. yielding rather standard SiN and Si-rich SiN. The investigation However, ultimately optimized cells have not been defined points out the impact of SiN stoichiometry and hydrogen content yet, and many alternative device structures have been recently on the electrical characteristics of gate stacks designed in view of proposed to improve WRITE, erase, and retention times [7], channel hot-electron/hole-injection program/erase (P/E) operation and tunnel P/E operation. The extensive and detailed characteriza- [8]. In particular, the optimization of the performance of tion establishes a sound experimental basis for the development of SONOS/MANOS cells is constrained by the tradeoff between the physics-based trap models proposed in the companion paper. the erase speed and the charge loss through the tunnel and top Index Terms—Charge trapping, nonvolatile memory devices, oxides during retention at high temperatures [9]–[11]. Instead, silicon nitride (SiN). in cells that are programmed/erased by the localized injection of hot carriers, the lateral charge drift and the recombination of the trapped charge are particularly worrisome because they give I. INTRODUCTION rise to data-retention issues [5], [12]–[14]. HARGE-TRAP nonvolatile memory devices based on The SiN composition plays a fundamental role on the per- C silicon nitride (SiN) storage layers are good candi- formance and reliability of the memory cells [8], [15]–[17]. dates to extend the current floating-gate technologies beyond The understanding of the electrical properties of SiN films with the 22-nm node [1]. In particular, metal-gate–Al2O3–nitride– different stoichiometry thus is of great importance in order to oxide–silicon (MANOS) devices are widely studied in the optimize the charge-trap memory technologies. Nevertheless, literature as a solution for a NAND architecture [2]–[4], which no clear and in-depth physical explanation of the impact of SiN is due to their intrinsic robustness to defects in the tunnel oxide composition on the memory behavior has been achieved yet. To shed new light on this relevant topic, we extended and completed the material analysis and the device characterization Manuscript received June 18, 2010; revised November 12, 2010, January 20, partly reported in [18]–[20] by carrying out a thorough study 2011, and March 21, 2011; accepted March 23, 2011. Date of publication of the chemical composition and the material structure of SiN May 2, 2011; date of current version July 22, 2011. This work was supported in part by the French Public Authorities through the NANO 2012 Program; layers deposited with different recipes by means of physical, by the Italian Ministry of Information, University, and Research through chemical, and electrical characterizations (e.g., secondary ion the Basic Research Investment Fund under Project RBIP06YSJ; and by the mass spectometry (SIMS), multiple internal reflection (MIR) European Union through the Seventh Framework Programme under Contract 214431 “GOSSAMER.” The review of this paper was arranged by Editor spectroscopy, spectroscopic ellipsometry, X-ray reflectometry, H. S. Momose. capacitance–voltage (C–V ) measurements, etc.), in order to E. Vianello is with the Department of Electrical, Management and Me- chanical Engineering, University of Udine, 33100 Udine, Italy, and also better understand the carrier transport and trapping character- with the Atomic and Laboratory of Electronics, Technology, and Instru- istics of the SiN storage layers. Furthermore, we investigated mentation, Atomic and Alternative Energies Commission, Micro and Nano- the operation of memory test structures with two distinctly technology Innovation Centre Campus, 38054 Grenoble Cedex 9, France (e-mail: [email protected]). different SiN films, particularly suited to study the impact of F. Driussi and L. Selmi are with the the Department of Electrical, Manage- SiN stoichiometry on the program/erase/retention characteris- ment, and Mechanical Engineering, University of Udine, 33100 Udine, Italy. tics of both MANOS test structures (i.e., written and erased L. Perniola, G. Molas, J.-P. Colonna, and B. De Salvo are with the Atomic and Laboratory of Electronics, Technology, and Instrumentation, Atomic and by tunneling) and thick tunnel-oxide test structures written by Alternative Energies Commission, Micro and Nanotechnology Innovation channel hot electrons (CHEs) and erased by hot-hole injection Centre Campus Campus, 38054 Grenoble Cedex 9, France. (HHI). The experimental data suggest that the SiN composition Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. does not alter appreciably the density and energy of the traps Digital Object Identifier 10.1109/TED.2011.2140116 with respect to the bottom of the SiN conduction band.

TABLE I PROCESS PARAMETERS FOR THE SiN FABRICATION RECIPES USED IN THIS PAPER.THE GAS FLOWS ARE MEASURED IN STANDARD CUBIC CENTIMETER PER MINUTE (SCCM)

In part II of this paper, we exploit atomistic- and device- level simulations to develop, with the help of the experiments, realistic models of the SiN films. The models suggest a simple Fig. 1. Immaginary part of the dielectric constant obtained from spectroscopic ellipsometry spectra and experimentally extracted values of the bandgap of std interpretation of the electrical properties of films with different and Si-rich SiN. SiN compositions, which is then confirmed experimentally.

II. CHARACTERIZATION OF THE LPCVD SiN LAYERS Thin SiN films have been fabricated by low-pressure chemical-vapor deposition (LPCVD), i.e., with two different recipes, to produce relatively standard (std) and silicon-rich (Si-rich) SiN films. The main process parameters are reported in Table I. In particular, the SiN composition has been modulated by varying the precursor gas-flow ratio R =[SiH2Cl2]/[NH3]. The std SiN films have been grown at R = 0.1 sccm, whereas for the slightly Si-rich samples, R = 5 sccm has been chosen. The std film turned out to be stoichiometric Si3N4 within an accuracy value of 3%. The recipes have been used to deposit 6-nm-thick std and Si-rich SiN films on flat wafers for the material analysis with physicochemical measurements. In order to emulate the thermal processes involved in the fabrication of the source/drain (S/D) implants in full devices, a rapid anneal of ≈1 min at 1050 ◦C has been performed as well.

A. Physicochemical Analysis The composition and the structure of the SiN layers grown on the flat wafers have been studied by means of different experimental techniques. First, we performed spectroscopic ellipsometry on nearly stoichiometric SiN and the films enriched with Fig. 2. (a) SIMS distributions of elements along the vertical direction of excess silicon, obtaining a refractive index of 2 and 2.4, respec- the structure with std SiN after baking at 1050 ◦C. Note the presence of a tively, i.e., in agreement with the literature data [21], [22]. Fig. 1 considerable amount of hydrogen in the SiN layer. Note that the SIMS profiles shows the imaginary part of the dielectric function 2 obtained of the different species are not directly quantitatively comparable because, to be translated in an element concentration, they need relative sensitivity from the spectroscopic ellipsometry spectra and the calculated factors that are dependent on the considered species. (b) Comparison of the bandgap-energy value EG for the std and Si-rich samples [8]. H concentrations obtained with the SIMS and MIR measurements in std and It is worth pointing out that annealing has no significant effect Si-rich SiN before and after baking. on the EG value (not shown). The bandgap of std SiN is ≈5.3 eV, which is in agreement with previously published interfaces between the layers, and it is possible to see the piling results of a nearly stoichiometric (noncrystalline) LPCVD SiN up of hydrogen in the bulk of the SiN layer [25], which we layer, which is obtained by X-ray photoelectron spectroscopy found to be present both before and after the S/D annealing and Bremsstrahlung isochromat spectroscopy [23], [24]. The step (not shown) [18]. The SIMS measurements also show that excess silicon reduces the energy bandgap to a value of about the oxygen content inside the SiN bulk is very limited and it is 4.7 eV, which is consistent with [8]. identical in the std and Si-rich SiN films (not shown). Fig. 2(b) Fig. 2(a) shows the SIMS distribution of elements, i.e., after (white bars) shows the ratio between the secondary ion intensity baking at 1050 ◦C, which is along a gate-stack structure with values for the H and Si atoms, and it is worth noting that the H std SiN. The vertical lines show the estimated positions of the atoms are present in both SiN recipes, although the H content VIANELLO et al.: CHARGE-TRAPPING PROPERTIES OF SIN LAYERS FOR NVM DEVICES I 2485

TABLE II N–H AND Si–H BOND CONCENTRATIONS ESTIMATED FROM THE ABSORPTION BANDS OF THE STRETCHING LOCAL VIBRATIONAL MODES OF N–H AND Si–H BONDS MEASURED BY MIR. MATERIAL DENSITY,WHICH IS MEASURED BY XRR, AND MECHANICAL STRESS,WHICH IS MEASURED BY THE CURVATURE METHOD USING THE STONEY FORMULA,ARE ALSO REPORTED FOR BOTH THE std AND Si-RICH SiN BEFORE AND AFTER BAKING

is larger in std SiN compared with Si-rich SiN. Furthermore, the SIMS measurements indicate the very small oxygen content inside the bulk of both SiN layers (not shown). The large concentration of hydrogen in SiN has been confirmed by MIR spectroscopy, which is able to quantify the number of N–H and Si–H bonds present in the SiN layer through the analysis of the absorption spectra of the material excited by infrared radiation [18], [26]. In particular, each atomic bond has a specific wavelength for the rotational and vibrational modes, and the concentration of such bonds can be extracted for the peaks in the measured MIR spectra. Table II reports the N–H and Si–H concentrations measured on the flat wafers with the two recipes of SiN. In agreement with the results in [27], the concentration of N–H bonds is larger than that of Si–H ones, particularly for std SiN. These results (black circles) have been compared with SIMS (white bars) in Fig. 2(b), and good mutual agreement is found. The higher hydrogen content in std SiN is due to the higher N–H concentration, whereas the two samples have a comparable number of Si–H bonds. Furthermore, annealing leads to an important decrease in the Si–H and N–H bond concentrations (see Table II). Table II also reports the material density ρ and the mechanical stress of SiN films grown on a p-doped Si substrate. The density measurements were done by means of XRR, and the SiN layers in the four specimens exhibit densities of about 2.8– 2.9 g/cm3 [28]. Stress measurements instead are done by the curvature method by using the Stoney formula, which relates Fig. 3. Comparison between measurements (symbols f = 100 kHz) and 1-D the film average stress to the substrate curvature [29]. Tensile Schroedinger–Poisson simulations (lines, [33]) of the C–V curves of virgin stress with values ranging from 600 to 1280 MPa has been samples with std and Si-rich SiN layers. (a) ONO stacks with an n-type measured [30]. Both stress and density slightly increase upon substrate. (b) Complete memory devices with a p-type substrate. annealing, which is probably because of the desorption of hydrogen evidenced by SIMS and MIR measurements. The trilayer oxide–nitride–oxide (ONO) dielectric stack, which is stress level measured in the two samples is different probably composed by a 3-nm SiO2 tunnel oxide thermally grown on because of the different deposition temperature during fabrica- an n-doped Si substrate, followed by a 6-nm SiN layer (i.e., tion and the different material stoichiometry. In particular, con- deposited with the same recipes, i.e., std or Si-rich, as described cerning the Si-rich sample, stress is reduced by excess silicon, in Table I) and covered by a 10-nm high-temperature-oxide whereas the density is similar to that of stoichiometric nitride. (HTO) top dielectric. Fig. 3(a) reports the 100-kHz C–V curve Indeed, the Si atoms have larger atomic mass than nitrogen of the two virgin gate stacks. A negative shift of flatband voltage atoms, but the Si–Si bond length is 2.35 Å against 1.73 Å for is found for the sample with Si-rich SiN (filled circles) with the Si–N bond. Therefore, as the film becomes more Si rich, respect to the std one (open triangles) [32]. The native charge the volume also increases, thus explaining why the density is density responsible for the flatband shift in the two samples almost constant. was estimated by means of comparison with 1-D self-consistent Schrödinger–Poisson simulations based on the model in [33] (see lines in Fig. 3). Without introducing any charge in the B. Electrical Characterization stack, the simulations well reproduce the flatband voltage of The std and Si-rich SiN layers have been also electrically the ONO structure with std SiN (solid line) for the nominal characterized. In particular, C–V measurements have been Hg work function of 4.5 eV. On the contrary, the experimental done with a mercury probe [31] on full-sheet wafers with a data of the sample with Si-rich SiN were fitted by adding a 2486 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011

Fig. 4. Sketch of the fabricated devices: The two type-A test structures, with both std and Si-rich SiN trapping layers, feature a thick tunnel oxide, whereas the two type-B cells have a MANOS gate stack, which is again with both std and Si-rich layers. Fig. 5. Program characteristics of the type-A test structures [(a) is pro- · 18 −3 grammed by CHE injection] and the type-B MANOS devices [(b) is pro- positive-charge concentration of 2.25 10 cm uniformly grammed by tunneling] with both std and Si-rich trapping layers. Note that distributed in the SiN layer (dashed line), corresponding to an the program transients are not influenced by the SiN composition in both cell areal charge density of 1.35 · 1012 cm−2. The origin of this types. charge will be discussed in part II of this paper. Consistent results have been obtained from C–V measurements performed on n-channel MANOS memory cells featuring both the two SiN compositions (i.e., the devices are described in detail in the next section). Fig. 3(b) reports the C–V curves of the virgin cells (symbols). The flatband voltages of the two devices have been successfully reproduced by using the same charges adopted in the simulation of the two full-sheet ONO stacks, assuming the nominal work function for the TiN metal gate (4.3 eV [34]). Thus, virgin std SiN is almost neutral, whereas it appears that there is a small positive charge in virgin Si-rich SiN. Another evidence from the data in Fig. 3 is that the samples with std and Si-rich SiN show the same equivalent oxide Fig. 6. Erase characteristics of the (a) type-A and (b) type-B test structures thickness (EOT). The physical thickness of the ONO layers with std (triangles) and Si-rich (circles) SiN layers, starting from the same program state VT . The SiN composition influences the erase transients of the was verified to be the same for the std and Si-rich SiN samples MANOS cells (faster erasing in the Si-rich sample), whereas it has no effect on by means of high-resolution transmission electron microscopy the HHI in the type-A test structures. images (not shown) [18], and hence, we conclude that the dielectric constant is not much affected by the SiN fabrication A. P/E Characteristics recipe. The program transients of the cells are reported in Fig. 5. The program curves are essentially independent of the SiN composition for both the type-A [see Fig. 5(a)] and type-B [see III. ELECTRICAL PERFORMANCE OF DEVICES WITH Fig. 5(b)] test structures because both the CHE programming DIFFERENT SiN STOICHIOMETRY and the tunneling programming are limited by the electron Complete memory-cell devices with SiN storage layers de- injection from the substrate and not by the trap concentration posited with the std and Si-rich SiN recipes reported in Table I in the SiN layer [12], [35]. Now, since Fig. 3(b) shows that the were also fabricated. The gate structure and the dimensions of EOT of the gate stack is independent of the SiN composition, the samples are reported in Fig. 4. The type-A test structures the electric field across the tunnel oxide in the area of injection have a thick bottom oxide (5 nm) to prevent the back tunneling (i.e., near the drain in type-A, which is along the channel in of the trapped charge to the substrate, and unless otherwise type-B) is approximately the same for a given bias, thus leading stated, (e.g., see Fig. 7) they have been programmed and erased to approximately equal electron-injection currents and, hence, by hot-electron injection and band-to-band-tunneling hole in- to similar program speed. jection, respectively. The type-B devices feature a MANOS Fig. 6 shows the erase characteristics of the cells. We note gate stack with a thinner tunnel oxide (2.2 nm) and a bilayer that the erase operation of the type-A test structures is not composed of HTO SiO2 and HfAlO as the top dielectric, in influenced by the SiN composition [see Fig. 6(a)]. On the order to favor the P/E by tunneling. Note that these devices contrary, in the type-B devices, the erase operation is faster were not optimized to reach high performance, but they are test in the presence of Si-rich SiN rather than in the case of the devices particularly developed for this paper. std SiN device (as shown in Fig. 6(b) and in agreement with The fabricated devices have been extensively characterized [8] and [36]). This difference is explained by the fact that two in order to investigate the impact of the SiN composition on the mechanisms contribute to the erase operation: the tunneling program/erase and retention characteristics. out of the electrons injected during programming from the VIANELLO et al.: CHARGE-TRAPPING PROPERTIES OF SIN LAYERS FOR NVM DEVICES I 2487

are strongly influenced by the SiN composition. This behavior is confirmed also by the high-temperature retention tests performed on the type-A cells programmed by tunneling [see Fig. 7(c)]. These latter data show an activation energy of the retention time for the two SiN compositions that are ∼1.2–1.3 eV in the 150 ◦C–185 ◦C range and differ by approximately 0.1 eV, which is a value likely close to the accuracy limit of the extraction procedure itself, thus suggesting a similar thermal emission behavior. Therefore, the large difference in the retention characteristics is likely due to the back tunneling of the electrons, that is very large in the Si-rich sample (compare the room-temperature characteristics of the two devices) [19]. Fig. 7. Retention characteristics at different temperatures of the type-A test Hence, there is once again the evidence of a different rate of structures programmed by (a) hot-electron injection and (c) Fowler–Nordheim electron emission from the traps of std and Si-rich SiN through tunneling, and (b) the MANOS (type-B) test structures programmed by tunneling. The SiN composition impacts the retention transients of the test the tunnel oxide. structures programmed by tunneling (i.e., faster charge loss in the Si-rich sample), whereas it has no effect on the retention performance of the structures programmed by hot-electron injection. IV. DISCUSSION AND CONCLUSION traps toward the substrate and the injection of holes from the The in-depth material analysis on SiN layers with different substrate. Since that, in our case, the cells with different SiN stoichiometry and the detailed electrical characterization of have equal EOT, the hole injection flux during erase opera- type-A (thick tunnel oxide) and type-B (thin tunnel oxide) tion is approximately the same in the two MANOS samples; memory test structures provide a set of experimental evidences therefore, the different dynamics in Fig. 6(b) should be ascribed that can be summarized as follows. to a different electron emission from traps. This interpretation As expected, the excess silicon reduces the bandgap of Si- also agrees with the erase characteristics of the type-A test rich samples with respect to the std SiN case. The dielectric C V structures; in fact, at the selected bias conditions, the thicker constant, i.e., the – curves, instead, are essentially unaf- tunnel oxide essentially prevents the electron emission, and fected. The virgin std SiN appears uncharged, whereas the Si- hence, the erase is dominated by the hole injection, which is rich films present a small native positive charge, whose value approximately the same due to the equal EOT. is essentially independent of the gate-stack structure where the SiN layer is integrated and, therefore, likely related to the bulk properties of the material. B. Retention Characteristics The results of the SIMS and MIR measurements highlight Fig. 7 reports the retention characteristics from the pro- the presence of a considerable amount of hydrogen in the grammed state of the (a) type-A test structures and (b) the SiN film. Although the excess silicon in the Si-rich samples MANOS cells for different temperatures T . We can observe reduces the H concentration, the number of Si–H bonds in the that, in the former case, the curves are independent of the SiN film remains comparable to that in std SiN. The presence of composition regardless of the temperature. Since the experi- hydrogen (low-mass atoms) in the SiN film can also explain ment is carried out on devices that have been programmed only the reduced mass density (≈2.85 g/cm3) with respect to the 3 once, holes do not affect the retention transient [13], and the theoretical one for the crystalline Si3N4 (3.1 g/cm ,[18]). charge loss is manly due to the lateral redistribution of the Therefore, it can be concluded that the H concentration in the trapped electrons across the SiN storage layer [5], [14]. In this layer seems to play a nonnegligible role in the physicochemical respect, although not quantitatively comparable (i.e., the test structure of the LPCVD SiN for memory applications. This structures and the charge distributions for the two experiments suggests that the presence of hydrogen could be relevant for are very different), the retention transients in Fig. 7(a) are the electrical behavior of the films and, in particular, for the essentially consistent with the Kelvin-force-microscopy (KFM) trapping properties responsible for the memory effect [37]. experiments in [20], in which the lateral spreading of the charge The retention transients of type-A test structures showed trapped in the SiN has been detected directly by KFM. In par- very similar lateral charge spread in the samples with different ticular, both experiments show that the lateral charge diffusion SiN stoichiometry [20]. Since the charge diffusion in this case inside the SiN layer [i.e., causing the VT shift in Fig. 7(a)] is driven by the emission of a trapped charge in the SiN does not show any dependence on the SiN composition, thus conduction band, this suggests similar detrapping rates and, suggesting similar detrapping rates of the charge toward the SiN therefore, similar energy depth of the traps in both std and Si- conduction band and similar transitions toward adjacent traps rich SiN [18]. and, hence, similar trap energy depth ET . The impact of the SiN composition on the program/erase In the MANOS memory devices, the charge distribution measurements of the type-A test structures and the program- after the tunneling programming instead is uniform over the ming curves of type-B MANOS devices is negligible. Instead, channel, and the electron emission through the top and bottom there is a large impact of the SiN composition on the erase oxides is the dominant discharge mechanism [9], [10]. Fig. 7(b) and retention transients of MANOS memory devices, in which shows that the retention characteristics of the MANOS cells the emission from the traps of the stored electrons is very 2488 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011

important. Note that, in previous studies, such different electron [15] S. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, emission (i.e., larger in the Si-rich SiN devices) has been L. D. R. Hung, J. M. Vasi, and S. Mahapatra, “Effect of SiN on performance and reliability of charge trap flash (CTF) under Fowler–Nordheim ascribed to traps that are slightly shallower in energy in the case tunneling program/erase operation,” IEEE Electron Device Lett., vol. 30, of cells featuring Si-rich SiN layers [15], [38]. Nevertheless, it no. 2, pp. 171–173, Feb. 2009. should be said that this conclusion was rather qualitative and [16] G. V. den Bosch, A. Furnémont, M. B. Zahid, R. Degreave, L. Breuil, A. Cacciato, A. Rothschild, C. Olsen, U. Ganguly, and J. V. Houdt, sometimes contradictory. In addition, in view of the results “Nitride engineering for improved erase performance and retention of reported in part II of this paper [39], we believe that the very TANOS NAND flash memory,” in Proc. IEEE NVSMW/ICMTD, 2008, slight difference in energy depths reported in the literature for pp. 128–129. [17] D. Gilmer, N. Goel, H. Park, C. Park, S. Verma, G. Bersuker, P. Lysaght, Si-rich SiN traps compared with std SiN ones [38], [40] cannot H. Tseng, P. Kirsch, K. Saraswat, and R. Jammy, “Engineering the com- exhaustively explain the experimental results of MANOS cells. plete MANOS-type NVM stack for best in class retention performance,” Furthermore, as aforementioned, the retention behavior of type- in IEDM Tech. Dig., 2009, pp. 439–442. E [18] E. Vianello, L. Perniola, P. Blaise, G. Molas, J. Colonna, F. Driussi, A test structures appears to suggest similar T values for the P. Palestri, D. Esseni, L. Selmi, N. Rochat, C. Licitra, D. Lafond, two SiN, thus highlighting the need for a deeper understanding R. Kies, G. Reimbold, B. D. Salvo, and F. Boulanger, “New insight on of the SiN composition dependence of MANOS characteristics. the charge trapping mechanisms of SiN-based memory by atomistic simulations and electrical modeling,” in IEDM Tech. Dig., 2009, pp. 83–86. At this regard, we note that the microscopic nature of SiN traps [19] E. Vianello, E. Nowak, L. Perniola, F. Driussi, P. Blaise, G. Molas, is not fully assessed yet, and different physicochemical features B. D. Salvo, and L. Selmi, “A consistent explanation of the role of the of such defects can play an important role in the emission rates. SiN composition on the program/retention characteristics of MANOS and NROM like memories,” in Proc. IMW, 2010, pp. 106–109. These aspects will be investigated in the accompanying paper [20] E. Vianello, E. Nowak, D. Mariolle, N. Chevalier, L. Perniola, G. Molas, [39] by means of atomistic and electrical simulations. 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[35] E. Vianello, F. Driussi, A. Arreghini, P. Palestri, D. Esseni, L. Selmi, Gabriel Molas was born in 1979 in Paris, France. N. Akil, M. van Duuren, and D. Golubovic, “Experimental and simulation He received the M.S. degree in physics engineer- analysis of program/retention transients in Silicon Nitride-based NVM ing, with a specialization in microelectronics from cells,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1980–1990, Polytechnics Institute of Grenoble, France, in 2001 Sep. 2009. and the Ph.D. degree in micro- and nanoelec- [36] C. Sandhya, A. Oak, N. Chattar, A. Joshi, U. Ganguly, C. Olsen, tronics from the Grenoble Institute of Technology, S. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, “Impact of SiN Grenoble, France, in 2004, with a thesis on few- composition variation on SANOS memory performance and reliability electron memory devices. under NAND (FN/FN) operation,” IEEE Trans. Electron Devices, vol. 56, In 2004, he joined the Laboratory of Electronics, no. 12, pp. 3123–3132, Dec. 2009. Technology, and Instrumentation (LETI), Atomic [37] M. Petersen and Y. Roizin, “Density functional theory study of deep traps and Alternative Energies Commission (CEA), Mi- in silicon nitride memories,” Appl. Phys. Lett., vol. 89, no. 5, p. 053511, cro and Nanotechnology Innovation Centre (MINATEC) Campus, Grenoble, Jul. 2006. as a Research Engineer. From 2004 to 2008, he was a Research Scientist [38] T. H. Kim, I. H. Park, J. D. Lee, H. C. Shin, and B.-G. Park, “Electron with the Silicon Nano-Device Laboratory, LETI, CEA, MINATEC Campus, trap density distribution of Si-rich silicon nitride extracted using the mod- where he was working on the processing of innovative memory devices. ified negative charge decay model of silicon–oxide–nitride–oxide–silicon Since 2008, he has been a Research Scientist with the Technology Labo- structure at elevated temperatures,” Appl. Phys. Lett., vol. 89, no. 6, ratory, LETI, CEA, MINATEC, and responsible of the charge-trap-memory p. 063508, Aug. 2006. activity in the advanced memory devices. He was responsible from the LETI [39] E. Vianello, F. Driussi, P. Blaise, P. Palestri, D. Esseni, L. Perniola, side of various industrial and institutional projects. He is a reviewer of G. Molas, and L. Selmi, “Explanation of the charge trapping properties of several international journals. He is the author or coauthor of more than silicon nitride storage layers for NVM’s—Part II: Atomistic and electrical 60 publications in international conferences and 20 papers in refereed journals. modeling,” IEEE Trans. Electron Devices, submitted for publication. His research interests include the processing, engineering, electrical character- [40] A. Suhane, A. Arreghini, R. Degraeve, G. van den Bosch, L. Breuil, ization, and modeling of innovative nonvolatile memory devices (charge-trap memory devices, tantalum aluminum oxide–nitride–oxide–silicon, nanocrys- M. Zahid, M. Jurczak, K. D. Meyer, and J. Van Houdt, “Validation of k retention modeling as a trap-profiling technique for SiN-based charge- tals, high- , silicon-on-insulator fin-shaped Flash architectures, single-electron trapping memories,” IEEE Electron Device Lett., vol. 31, no. 1, pp. 77–79, memory devices, etc.). Jan. 2010. Dr. Molas is a member of the Memory Technology Subcommittee of 2010–2011 International Electron Devices Meeting.

Jean-Philippe Colonna was born, in 1974, in Elisa Vianello received the Laurea degree in elec- Rouen, France. He received the French Diploma tronic engineering and the Ph.D. degree from the in engineering with a specialization in microelec- University of Udine, Udine, Italy. tronics from the Grenoble Institute of Technology, Between 2008 and 2009, she was with the Grenoble, France, in 1998 and the M.Sc. degree Laboratory of Electronics, Technology, and Instru- in semiconductor science and technology from the mentation, Atomic and Alternative Energies Com- Imperial College London, London, U.K., in 1999. mission, Micro and Nanotechnology Innovation In 1999, he joined STMicroelectronics Crolles, Centre Campus, Grenoble, France, working on the k Crolles, France, and worked as a Process Engineer electrical characterization of charge-trap high- - in the Diffusion Group for three years. In 2002, he based memory devices. During her doctoral years moved to Intel Ireland, where he worked as a Process in May 2010, she worked on the simulation and Engineer in the Rapid Thermal Processing Group. In 2005, he joined the characterization of Flash memory devices, from the Department of Electrical, Laboratory of Electronics, Technology, and Instrumentation, Atomic and Al- Management, and Mechanical Engineering, University of Udine, and from ternative Energies Commission, Micro and Nanotechnology Innovation Centre, the Grenoble Institute of Technology, Grenoble. Her research interests include Grenoble, France, where he worked as a Research Engineer. He is the author or modeling, characterization, and reliability of nonvolatile memory devices, fo- coauthor of more than 40 publications in international conferences or papers in cusing on reliability issues related to the statistical distribution of stress-induced refereed journals. His research interests include materials and their integration leakage current and on the modeling and characterization of silicon–oxide– in nonvolatile memory devices (nanocrystals, high-k, charge traps, etc.). nitride–oxide–silicon/tantalum aluminum oxide–nitride–oxide–silicon memory cells. B. De Salvo, photograph and biography not available at the time of publication.

Francesco Driussi received the Laurea and Ph.D. Luca Selmi was born, in 1961. He received the Ph.D. degrees in electronic engineering from the University degree in electronics from University of Bologna of Udine, Udine, Italy, in 2000 and 2004, respec- in 1992. tively, working on the reliability of Flash memory From 1989 to 1990, he was a Visiting Scien- devices. tist with Hewlett Packard Microwave Technology From October 2002 to September 2003, he held a Division, Santa Rosa, CA. In 2000, he became student position with Philips Research Leuven, Leu- a Full Professor of electronics with the Univer- ven, Belgium. In 2005, he was a Research Associate sity of Udine, Udine, Italy. He had conducted re- with the University of Udine. In particular, he has search in cooperation with international research worked on substrate-enhanced hot-electron phenom- centers such as Bell Laboratories, IBM T.J. Wat- ena and has investigated their implications for Flash son Research Center, Philips Research Laborato- electrically erasable programmable read-only memory devices. More recently, ries, NXP Semiconductors, Grenoble Institute of Technology, and the Lab- he has worked on the development of physical and statistical models for the oratory of Electronics, Technology, and Instrumentation Grenoble. He is study of stress-induced leakage current in large Flash memory arrays and the the author or coauthor of approximately 200 papers, including more than generation and distribution of oxide traps. His main research interests include 30 International Electron Devices Meeting (IEDM) papers. His research in- nonvolatile-memory-cell reliability and the characterization of device degra- terests include the characterization and simulation of silicon devices, with an dation and gate-dielectric reliability. His current research interests include the emphasis on nanoscaled complementary metal–oxide–semiconductor (CMOS), characterization and modeling of silicon–oxide–nitride–oxide–silicon/tantalum Monte Carlo transport techniques, hot-carrier effects in MOS ﬁeld-effect aluminum oxide–nitride–oxide–silicon memory cells, the in-depth investigation transistors and nonvolatile memory cells, leakage currents and reliability of of the trapping properties of silicon nitride, and the experimental characteriza- ultrathin oxides, and device optimization. tion and modeling of the carrier mobility in metal–oxide–semiconductor ﬁeld- Dr. Selmi is a Technical Pogram Committtee member of several international effect transistor devices featuring strained silicon and high-k gate stacks. conferences of the electron device community. He has been a member of the IEDM technical subcommittees on “Modeling and Simulation,” “Circuit and Interconnect Reliability,” and “CMOS devices.” He is an Associate Editor of L. Perniola, photograph and biography not available at the time of publication. the IEEE Electron Devices Letter.