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Nanostructures for Tera-Bit Level Charge Trap Flash Memories NanostructuresNanostructures forfor TeraTera--bitbit LevelLevel ChargeCharge TrapTrap FlashFlash MemoriesMemories Byung-Gook Park, Il Han Park, Jung-Hoon Lee, Gil Sung Lee, Jang-Gn Yun Inter-University Semiconductor Research Center School of Electrical Eng. and Computer Sci. Seoul National University NanoForum'09 Outline I. Introduction II. NAND Cell Structure III. NOR Cell and Array Structure IV. AND Cell and Array Structure V. STAR NAND Flash Structure VI. Conclusions NanoForum'09 SNU SoEECS & ISRC Flash Memory and Mobile Equipments 32 NanoForum'09 SNU SoEECS & ISRC Expedited Growth Theory - NAND Flash 100 ITRS (2008) 1000 Hwang’s law Capacity (Giga Bit) 100 10 Technology Node (nm) 10 2002 2004 2006 2008 2010 2012 2014 2016 2018 Year of Development q Expedited growth theory of NAND flash memories è Year 2011 1Tb capacity with 20nm feature size NanoForum'09 SNU SoEECS & ISRC Hard Disk Drive and Flash Memory NanoForum'09 SNU SoEECS & ISRC Growth of Storage Capacity HDD 10T ODD FGF 1T CTF 100G FeRAM 10G MRAM PRAM 1G 100M 10M 1M Capacity (bit) 100k 10k 1k 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 Year NanoForum'09 SNU SoEECS & ISRC Floating Gate vs. Charge Traps Floating Gate SONOS structure ONO structure Composite Ø No floating gate Dielectrics Gate - FG-FG space Gate - FG-active space - Single gate structure n+ n+ n+ n+ P-Si P-Si Ø Defect immunity - Non-conductive trap layer Tunnel Blocking Poly Si Si SiO2 Si3N4 SiO2 - Discrete trap storage 1.05 3.1 3.1 e e e Ø 3D structure compatibility h h h 8.0 - Insulating storage node 3.8 3.8 - Simple fabrication 1.85 NanoForum'09 SNU SoEECS & ISRC Outline I. Introduction II. NAND Cell Structure III. NOR Cell and Array Structure IV. AND Cell and Array Structure V. STAR NAND Flash Structure VI. Conclusions NanoForum'09 SNU SoEECS & ISRC Arch Structure (1) q Utilization of curved surfaces for field enhancement - fast “program”and “erase” - increased effective area r2 r1 Poly ONO Arch type Planar type 12.0M 10.0M SiO2 8.0M 6.0M 4.0M Bottom 2.0M Top Oxide Silicon Nitride Oxide Si Electric Field (V/cm) 0.0 0 2 4 6 8 10 12 14 Position (nm) NanoForum'09 SNU SoEECS & ISRC Arch Structure (2) q Fabrication procedure Hard mask Si Si SiO2 Si NanoForum'09 SNU SoEECS & ISRC Arch Structure (3) q Utilization of HSQ mask characteristic q Planarization by TEOS, HSQ and etch back NanoForum'09 SNU SoEECS & ISRC Arch Structure (4) <Programming characteristics> <Erase characteristics> 0.5 5.5 0.0 5.0 -0.5 4.5 -1.0 4.0 -1.5 3.5 -2.0 3.0 -2.5 -18V (V) 2.5 -3.0 (V) th -20V 2.0 th -3.5 V 20V V -22V D 1.5 D -4.0 1.0 22V -4.5 -24V 0.5 24V -5.0 0.0 -5.5 -0.5 -6.0 -7 -6 -5 -4 -3 -2 -1 0 1 Initial10 10 10 10 10 10 10 10 10 Initial10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101 Time(s) Time(s) q Radius of Si channel = 15 nm NanoForum'09 SNU SoEECS & ISRC Outline I. Introduction II. NAND Cell Structure III. NOR Cell and Array Structure IV. AND Cell and Array Structure V. STAR NAND Flash Structure VI. Conclusions NanoForum'09 SNU SoEECS & ISRC Cone Structure (1) q Utilization of field and current concentration - field concentration in the horizontal direction - current concentration in the vertical direction Cut line Drain junction Cut line Drain junction ONO layer Gate Gate ONO layer Electric field high flux density high flux density r2 flux Si r1 Drain O O ER Er N Source Gate low flux density low flux density NanoForum'09 SNU SoEECS & ISRC Cone Structure (2) q Simple array structure - common source architecture - word line connection through small spacing of cones NanoForum'09 SNU SoEECS & ISRC Cone Structure (3) <Plan view> <Cross-sectional view> NanoForum'09 SNU SoEECS & ISRC Cone Structure (4) q Electrical characteristics <Program/erase characteristics> <Retention characteristic> 4.0 4.0 o CHEI Program( V : 6 V, V :4 V) Retention Characteristics(150C) 3.5 G D 3.5 program state 3.0 3.0 CHEI Program( V : 6 V, V :3 V) 2.5 G D 2.5 (V) 2.363 V 2.0 2.0 2.160 V ( V) TH TH V 1.5 V 1.5 1.0 1.0 FN Erase ( V : 11 V) 0.5 Erase state 0.5 B 0.0 0 1 2 3 4 5 6 7 8 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 10 10 10 10 10 10 10 10 10 10 Time (s) Time (s) NanoForum'09 SNU SoEECS & ISRC Outline I. Introduction II. NAND Cell and Array Structure III. NOR Cell and Array Structure IV. AND Cell and Array Structure V. STAR NAND Flash Structure VI. Conclusions NanoForum'09 SNU SoEECS & ISRC Conventional Flash Memory Structures < NAND > < NOR > < AND > LSL LBL Active W/L F-Poly Schematic Top View NAND NOR AND program efficiency high Low high sensing speed low high high density high low low NanoForum'09 SNU SoEECS & ISRC Vertical AND Structure (1) q Memory cell device with vertical and double gate structures - vertical structure, S/D junctions connected by diffusion layer à High integration density. - double gate structure. à High device performance, high sensing speed. N N N P P P N N N P NanoForum'09 SNU SoEECS & ISRC Vertical AND Structure (2) q Fabrication procedure N N N N N N P P P P N N N N P P N N P N P N N N N N N N N N N N P P P P P P P P P P N N N N N N N N N N P P P P (a) (b) (c) (d) N N N N N N P P P P N N N N N P N P N P N P N N N N N N N N N N N N P P P P P P P P P P P P N N N N N N N N N N N N P P P P (h) (g) (f) (e) NanoForum'09 SNU SoEECS & ISRC Vertical AND Structure (3) q Program/erase characteristics <Program characteristics> <Erase characteristics> 7 7 V = 13 V 6 G VG = 15 V 6 VG = 17 V 5 5 4 4 V = 13 V G V = 15 V 3 G V = 17 V 3 G 2 Threshold Voltage [V] Threshold Voltage [V] 2 -5 -4 -3 -2 -1 0 10-7 10-6 10-5 10-4 10-3 10-2 10-1 10 10 10 10 10 10 Programming Time (sec) Erasing Time (sec) NanoForum'09 SNU SoEECS & ISRC Outline I. Introduction II. NAND Cell Structure III. NOR Cell and Array Structure IV. AND Cell and Array Structure V. STAR NAND Flash Structure VI. Conclusions NanoForum'09 SNU SoEECS & ISRC STAR NAND Flash Structure (1) WL direction q Stacked bit-lines gate à high density oxide q Cylindrical channel and gate ONO dielectrics gate-all-around cell Si structure cylindrical channel à high performance Si body oxide q Single-crystal Si channel à high performance, uniformity, reliability Si substrate NanoForum'09 SNU SoEECS & ISRC24 STAR NAND Flash Structure (2) q Fabrication procedure mask a > b nitride nitride nitride SiGe SiGe SiGe Si Si Si SiGe SiGe SiGe Si Si Si SiGe SiGe SiGe Si substrate Si substrate Si substrate SiGe SiGe nitride nitride nitride a > b SiGe Si Si Si SiGe Si Si Si SiGe Si substrate Si substrate Si substrate NanoForum'09 SNU SoEECS & ISRC STAR NAND Flash Structure (3) q Fabrication procedure (continued) WL direction gate gate SiGe ONO nitride oxide gate ONO dielectrics Si Si Si Si cylindrical channel Si Si Si body ONO oxide Si substrate Si substrate Si substrate NanoForum'09 SNU SoEECS & ISRC STAR NAND Flash Structure (4) q Components of stack and nanowire implementation <Selectively etched SiGe> <Rounded Si nanowire> NanoForum'09 SNU SoEECS & ISRC27 Conclusions (1) q Charge trap flash memory including SONOS structure is a promising candidate for the next generation high density flash memories. q For NAND application, arch SONOS flash memory is proposed for field concentration and suppression of back tunneling and is successfully demonstrated. q For NOR application, cone SONOS flash memory is proposed for field and current concentration, and the fabricated cell shows superb electrical characterics. NanoForum'09 SNU SoEECS & ISRC Conclusions (2) q For AND application, vertical AND structure is proposed for drastic reduction of cell size and the feasibility is demonstrated. q For further increase of density, STacked ARray (STAR) NAND array is proposed. NanoForum'09 SNU SoEECS & ISRC.
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