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A Secure Hfo2 Based Charge Trap Eeprom with Lifetime and Data Retention Time Modeling A SECURE HFO2 BASED CHARGE TRAP EEPROM WITH LIFETIME AND DATA RETENTION TIME MODELING By CHENG HAO Bachelor of Science in Electrical Engineering North Carolina State University Raleigh, NC 2011 Master of Science in Electrical Engineering Oklahoma State University Stillwater, OK 2016 Submitted to the Faculty of the Graduate College of the Oklahoma State University in partial fulfillment of the requirements for the Degree of DOCTOR OF PHILOSOPHY July, 2019 A SECURE HFO2 BASED CHARGE TRAP EEPROM WITH LIFETIME AND DATA RETENTION TIME MODELING Dissertation Approved: Dissertation Adviser Dr. Chris Hutchens Dissertation Adviser Committee Member Dr. Jerzy Krasinski Committee Member Dr. Daqing Piao Outside Committee Member Dr. Jindal Shah ii ACKNOWLEDGEMENTS I would like to sincerely thank my advisor Dr. Chris Hutchens for the guidance throughout my Ph.D. study. I certainly would not have this achievement without his effort. I also would like to thank Dr. Jerzy Krasinski, Dr. Daqing Piao and Dr. Jindal Shah to be my committee members. They have provided me valuable guidance and suggestions for my work. I would like to thank Air Force Research Laboratory (AFRL), Rome, NY for the funding of this project. I would like to thank my parents, my mother Mrs. Ru Jia, my father Mr. Genli Hao and other family members for being supportive toward my education. I would like to thank my girlfriend Ms. Hao Guo for being on my side throughout these years. I would like to dedicate this dissertation to all people that support me these years for this great achievement. I would like to thank my MSVLSI lab members Mr. Vishal Reddy Banala and Mr. Juan Salinas for their help and contributions throughout my study. iii Acknowledgements reflect the views of the author and are not endorsed by committee members or Oklahoma State University. Name: CHENG HAO Date of Degree: JULY, 2019 Title of Study: A SECURE HFO2 BASED CHARGE TRAP EEPROM WITH LIFETIME AND DATA RETENTION TIME MODELING Major Field: ELECTRICAL ENGINEERING Abstract: Trusted computing is currently the most promising security strategy for cyber physical systems. Trusted computing platform relies on securely stored encryption keys in the on-board memory. However, research and actual cases have shown the vulnerability of the on-board memory to physical cryptographic attacks. This work proposed an embedded secure EEPROM architecture employing charge trap transistor to improve the security of storage means in the trusted computing platform. The charge trap transistor is CMOS compatible with high dielectric constant material as gate oxide which can trap carriers. The process compatibility allows the secure information containing memory to be embedded with the CPU. This eliminates the eavesdropping and optical observation. This effort presents the secure EEPROM cell, its high voltage programming control structure and an interface architecture for command and data communication between the EEPROM and CPU. The interface architecture is an ASIC based design that exclusively for the secure EEPROM. The on-board programming capability enables adjustment of programming voltages and accommodates EEPROM threshold variation due to PVT to optimize lifetime. In addition to the functional circuitry, this work presents the first model of lifetime and data retention time tradeoff for this new type of EEPROM. This model builds the bridge between desired data retention time and lifetime while producing the corresponding programming time and voltage. iv TABLE OF CONTENTS Chapter Page I. INTRODUCTION ......................................................................................................1 II. TRUSTED PLATFORM MODULE SECURITY ISSUES .....................................3 2.1 Trusted Platform Module ...................................................................................4 2.2 Means of Memory Attacks .................................................................................8 2.2.1 Microprobing Attack .................................................................................8 2.2.2 Cold-boot Attack .....................................................................................10 2.2.3 Side Channel Attacks ..............................................................................11 2.3 Variety of Hardware Security Means ..............................................................13 2.4 Perspective of This Work.................................................................................14 III. HFO2 HK DIELECTRIC TRANSISTOR .............................................................16 3.1 High-k Dielectric Gate Stack ...........................................................................16 3.1.1 Why High-k ............................................................................................16 3.1.2 Choices of Material .................................................................................17 3.1.3 Gate Stack Structure ...............................................................................18 3.2 Defect Levels ...................................................................................................19 3.3 Carrier Transport ..............................................................................................21 3.4 Threshold Voltage Instability and Memory Applications ...............................24 3.4.1 Charge Trapping/Detrapping and Threshold Voltage Instability ...........24 3.4.2 Memory Applications .............................................................................27 3.5 Reliability Issues ..............................................................................................28 3.5.1 Bias Temperature Instability ...................................................................28 3.5.2 Stress Induced Leakage Current .............................................................29 3.5.3 Time Dependent Dielectric Breakdown ..................................................30 IV. PROPOSED EEPROM ARCHITECTURE ..........................................................33 4.1 Design Overview .............................................................................................33 4.2 CPU/EEPROM Interface .................................................................................34 4.2.1 Input Registers ........................................................................................34 4.2.2 CUI ..........................................................................................................36 4.2.3 Controller ................................................................................................38 4.3 Interface Operation ..........................................................................................40 4.3.1 Write .......................................................................................................40 v Chapter Page 4.3.2 Erase ........................................................................................................41 4.3.3 Read ........................................................................................................42 4.4 EEPROM Core.................................................................................................42 4.4.1 EEPROM Cell .........................................................................................42 4.4.2 EEPROM Macro Model .........................................................................48 V. PROGRAMMING VOLTAGE GENERATION....................................................51 5.1 LDO Specifications ..........................................................................................51 5.2 Design Flow .....................................................................................................54 5.3 Implementation ................................................................................................61 5.3.1 Bandgap Voltage Reference ..................................................................61 5.3.2 Gain Boosting ........................................................................................63 5.3.3 Boosted Telescopic OTA .......................................................................64 VI. EEPROM LIFETIME AND DATA RETENTION TIME TEADEOFF ..............66 6.1 High-k Dielectric Gate Reliability ...................................................................66 6.2 TDDB Models for SiO2 Gate Stack .................................................................67 6.2.1 E Model ...................................................................................................67 6.2.2 1/E Model................................................................................................69 6.2.3 Power Law Voltage Model .....................................................................70 6.2.4 √퐸 Model ................................................................................................70 6.3 Advanced TDDB Models for HfO2 Gate Stack ...............................................72 6.3.1 Progressive Breakdown ..........................................................................72 6.3.2 Generated Subordinate Carrier Injection Model .....................................75 6.3.3 A Percolation Model with Different Defect Generation Rates ...............76 6.3.4 An All-in-one TDDB Reliability Model .................................................77 6.4 Proposed Comprehensive Model .....................................................................78 6.4.1 Model Overview .....................................................................................78
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