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NAND Flash Scaling Challenges Charge-Trap NAND Flash Memory Souvik Mahapatra E E Dept, IIT Bombay, India CtibtiContributions: San dya CPC, Pawan Si ngh hS, Suyog Gup ta, KhitijAlKshitij Auluck , Piyush Dak, Sandeep Kasliwal, Udayan Ganguly, Dipankar Saha, Gautam Mukhopadhyay, Juzer Vasi Support: Applied Materials, Intel Corporation, SRC/GRC 1 Outline FG NAND Flash scaling challenges SiN based charge trap flash – material dependence P/E simulation of SiN Flash Metal nanodot Flash Scalability simulation of m-ND Flash 2 NAND Flash Background BL DSL CG CD 15nm ells WL FG 50nm No. of c TO 9nm Memory state Figure: Samsung L=35nm SL SSL •Electron transfer between substrate & FG define memory state (write & erase) •FG surrounded by TO & CD acts as electron storage well (non-volatility, need 10yrs), though leak out occurs over time (retention loss) •Repeated Write/Erase (10-100K needed) causes memory 3 wear out (cycling endurance) NAND Flash Scaling CG •More memory, faster access, reduced cost CD 15nm •Guideline (ITRS roadmap): L=35nm (2009) , FG 50nm 28nm (2010/11), 22nm (2013/14)… TO 9nm •SLC (1bit/cell) , MLC (2 or 3 bit s/ cell) f or hi gh er L=35nm density, higher reliability issues Scaling penalty: Solution: Discrete trap- (1) Loss of CG – FG coupling based charge storage (2) C ell t o cell cross t alk (3) Non-scaling of TO, FG and CG CD thickness CD, 12nm (4) Non-scaling of operating SiN, 6nm voltage TO, 6nm (5) Higher reliability concern 4 Planer CTF Devices & test chip demonstrated (Samsung) •Memory window close down with W/E cycling •Data keeps leaking out (worse than FG!) •Loss of memory operation 5 CTF reliability worse than FG, no product yet Retention Issue Lateral or Vertical charggge migration Trap depth of SiN is key to control charge migration Solution – to cut SiN above STI (Samsung, 2007) 6 NAND 3D Memory 3D CTF ppproposed as a way to move forward below 20nm node: BiCs (Toshiba), TCAT (Samsung) 7 Motivation CTF reliabilityyp improvement needs: Understandinggp impact of device p rocessing on material and electrical properties Proper device design (structure, composition) Detailed electrical characterization & modeling – feedback for intelligggent manufacturing 8 SANOS Device Structure Trap parameters: Gate Nt,elec, Φt,elec Nt,hole, Φt,hole 12 nm ))) Ec mmmmmm Φt,elec 15 nm Al2O3 20 nm Si+ N+ tancetancetance (n (n (n ssssss Φt,hole DiDiDi N+ Si+ 6 nm SixNy SixNy Ev SiO 3-6 nm TO Al O 2 Trap dist. 2 3 Channel (A.U.) Charge tunnel from substrate to SiN via TO, Al2O3 used for leakage blocking 9 P/E Transients 12 8 P/E at +18V/-18V P E R.I. Ref Total memory window 10 r 6 active In 8 4 N-rich 6 ow (V) d (V) Si-rich dd ex (R.I.) FB 2 4 V N0 N1 N2 N3 N4 Δ 2 0 N+ Si+ /E Win W11 W2 W3 W6 W8 PP 0 1951.95 -2 2.00 -2 2.05 -4 2.10 -8 -5 -2 1 -4 2.15 10 10 10 10 W11W2W3W6W8 Time (s) Splits High-k blocking dielectric: ¾ Better coupling to channel ¾ Larger memory windows P / E state (memory window) depend on SiN composition 10 ISPP and ISPE 7 6 N0 N0 N+ 5 N+ 6 N1 N1 4 5 N2 N2 N3 3 N3 ) 4 ) VV N4 2 N4 VV ( ( Si+ FB 3 Si+ FB 1 V 2 V 0 1 -1 0 -2 -1 -3 10 15 20 25 -4 Vg (V) 0 -5 -10 -15 -20 -25 N+ SiN Vg (V) ¾Higher electron trapping efficiency ¾Poor erase characteristics Si+ SiN ¾Low P saturation levels 11 ¾Higher erase efficiency Charge loss (Retention) N+ 0.8 0.5 5.5 E state loss P state loss 040.4 505.0 0.6 N1 Δ 4.5 Si+ V N2 0.3 FB (V) + + B (V) (V) FF N3 040.4 N Si V N+ FB -1.6 N4 -1.7 V 0.2 Δ -1.8 0.2 -1.9 0.1 -2.0 Si+ -2.1 2 3 4 0.0 0.0 10 10 10 1.95 2.00 2.05 2.10 2.15 Time (s) RIR.I. N+ SiN ¾ Deep electron traps - shallow hole traps Si+ SiN ¾ Shallow electron traps - deep hole traps P/E state retention dependent on SiN composition 12 Tunnel oxide thickness dependence 555.5 ) 5.0 VV ( FB 2.5 V 3/6/12 5/6/12 4/6/12 6/6/12 2.0 0.04 ) VFB= 2.5V VV ( 0.00 FB V -0.04 Δ 101 102 103 104 Time (s) Thinner TO Æ Increased electron tunnel out from SiN 13 Retention – T dependence V = 5.5V 0.0 FB 1043 38 N1:Ea = 1.88 eV 10 N2:Ea = 1.38 eV (V) -0.4 FB 33 N3:Ea = 1.01 eV V 10 ΔΔ 1028 -0.8 23 (s) 10r 0.0 t 1018 VFB = 2.5V 13 (V) 10 -0.4 FB 8 VV o o 10 Δ 25 C 125 C 150oC 180oC 103 -0.8 25 30 35 40 1 2 3 4 10 10 10 10 1/kT(e V-1) Time (s) Higher activation energy in N+ → Deeper electron traps 14 Retention – E state TO thickness & T effect 0.4 o o E state retention loss 25 C 125 C 150oC 180oC (V) BB 0.2 ¾ T independent F No thermal emission of V VFB = -2.0V holes Δ 000.0 0.4 3/6/12 4/6/12 5/6/12 6/6/12 ¾ TO independent for > 3nm )) (V No Trap to Band tunneling 0.2 of holes FB VFB = -2.0V V ΔΔ 0.0 101 102 103 104 Different charge loss mechanisms Time (s ) for electrons and holes 15 Endurance – SiN Composition 5 5 ) VV ( 4 FB 4 N1 ) w, V N2 oo VV 3 3 ( N1 N3 FB V 2 N2 2 N4 N3 Wind P 16V 5ms yy N+ 1 N4 E -15V 1ms 1 Memor 0 0 Si+ 0 1 2 3 4 100 101 102 103 104 10 10 10 10 10 P/E Cycles P/E Cycles Endurance degradation SiN composition dependent Si-rich devices cycle with negligible erase state degradation 16 Summary • Comparison of SiN Compositions Parameter N+ Si+ Electron trap depth Deep Shallow Hole trap depth Shallow Deep Hole trap density Very low High Split window Not Possible operation possible Endurance High Low degradation 17 P/E Simulation of SiN Flash • DlDevelop a SiltifSimulation framework capabl blfe of providi ng useful insight into the physics involved during Program /Erase (P/E) operations. • Accuratelyyp predicting P/E behavior of SANOS/SONOS memories • Simul ati on up t o l ong ti me i nst ant s, l arge bi ases • For different gate stack dimensions • For different Nitride Compositions 18 Simulation Methodology •Set P/E bias •Compute Poisson throughout gate stack •Assume TO and CD as pure tunnel barriers, compute tunneling currents in and out of SiN •Compute transport, continuity and SRH (trapping detrapping) in SiN •Com pute tr apped ch ar ges, update Poisson •Continue till end of P/E time 19 Simulation Flow 20 Key Models Incorporated Tsu-Esaki tunneling formulation Field depppendent capture cross section Poole Frenkel detrapping from traps TtbdtliTrap to band tunneling 21 P/E: Stack Energy Band Diagrams 22 SANOS sample stack properties Gate Stack Dep. Dimensions SiN Si H /N 2 6 3 Temp RI (nm) type flow ratio (°C) TO SiN CD N2 0. 005 650 2. 006 4 6 15 N2 0.005 650 2.006 6 612 N2 0. 005 650 2. 006 4 6 12 N0 0.01 800 1.987 4 6 12 N0 Æ More N rich SiN; N2 Æ More Si rich SiN Differen t s tac k dimens ions use d t o ch eck rob ust ness 23 ISPP Matching 7.5 Exp Lower Less than 1V change in 6.5 Field dep. σ (n = 3) Vfb Shift σ = const (n = 0) VT (or VFB) for every 1V 5.5 n increment in applied VG σ = σ0/(1+(E/Esat) ) 4.5 (ISPP slope <1V/V) ) VV 3.5 Vfb ( Vfb Employing the field Δ 2.5 ddtdependent σ enables Lower ISPP Slope accurate prediction of 1.5 ISPP 0.5 -0.5 5 10 15 20 Vg (V) 24 ISPP Matching 9.5 Exp: N2 (4/6/15nm) Good matching with 8.5 Exp: N2 (4/6/20nm) Exp: N0 (4/6/12nm) ISPP data for varying 757.5 3 σ = σ /(1+(E/E ) ) gate stack thickness 6.5 0 sat ) N2 and nitride VV 5.5 compositions 4.5 Vfb ( Vfb Δ 3.5 StSame parameter 2.5 N0 values used during P/E 1.5 transient matching (to 050.5 Symbol : Exp Line : Sim follow) -0.5 4 6 8 10 12 14 16 18 20 22 Normalized Vgg( (V) 25 P/E Matching 5.5 6 Symbol: Exp Line: Sim 5 4.5 4 3.5 3 (V) V) (( 2.5 Vfb Vfb 2 Vfb Vfb Δ Δ Vg : -17V - -12V 1.5 1 Vg : 12V-16V 0.5 0 Symbol: Exp Line: Sim -1 -0.5 -6 -5 -4 -3 -2 -1 0 -6 -5 -4 -3 -2 -1 0 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Time (s) Time (s) Progg(ram and Erase transients (N2-4/6/12 nm SANOS) 26 P/E Matching (Change in TO) 5.5 6 Symbol: Exp Line: Sim 4.5 5 4 3.5 ) V) VV 3 2.5 Vfb ( Vfb Vfb ( Vfb Δ 2 Δ 1.5 Vg : -18V - -13V 1 0.5 Vg : 12V-17V 0 Symbol: Exp Line: Sim -0.5 -6 -5 -4 -3 -2 -1 0 -1 10 10 10 10 10 10 10 -6 -5 -4 -3 -2 -1 0 10 10 10 10 10 10 10 Time (s) Time (s) Program and Erase transients (N2-6/6/12 nm SANOS) 27 P/E Matching (Change in CD) 6.5 7 Symbol: Exp 5.5 Line: Sim 6 5 4.5 4 ) ) VV VV 353.5 3 Vfb ( Vfb Vfb ( Vfb 2.5 Δ Δ 2 Vg : -18V - -13V 1.5 1 Vg : 13V-18V 0.5 0 Symbol: Exp Line: Sim -0.5 -1 -6 -5 -4 -3 -2 -1 0 -6 -5 -4 -3 -2 -1 0 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Time (s) Time (s) Program and Erase transients (N2-4/6/15 nm SANOS) 28 P/E Matching (Change in SiN) 7.5 7 Symbol: Exp 6 6.5 Line: Sim 5 5.5 4 4.5 (V) 3 fb (V) b 353.5 VV Vfb Δ Δ 2 2.5 Vg : -17V - -13V 1 1.5 Vg : 12V-17V N0-4/6/12nm 0 SblESymbol: Exp 0.5 Line: Sim -1 -0.5 -6 -5 -4 -3 -2 -1 0 -7 -6 -5 -4 -3 -2 -1 0 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Time (s) Time (()s) Progg(ram and Erase transients (N0-4/6/12 nm SANOS) 29 Extracted parameters (SiN dependence) Parameter N0 N2 Parameter N0 N2 Electron trap depth 1.8 1.63 Hole Trap Depth (eV) 1.73 1.95 (()eV) Electron trap density Hole Trap Density 3.3 3.9 1.6 2.6 (1019cm-3) (1019cm-3) Electron σ const.
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