NAND Flash Scaling Challenges

Souvik Mahapatra E E Dept, IIT Bombay, India

CtibtiContributions: San dya C CP, Pawan Si ngh hS, Suyog Gup ta, KhitijAlKshitij Auluck , Piyush Dak, Sandeep Kasliwal, Udayan Ganguly, Dipankar Saha, Gautam Mukhopadhyay, Juzer Vasi

Support: Applied Materials, Intel Corporation, SRC/GRC 1 Outline

FG NAND Flash scaling challenges

SiN based charge trap flash – material dependence

P/E simulation of SiN Flash

Metal nanodot Flash

Scalability simulation of m-ND Flash

2 NAND Flash Background

BL DSL CG

CD 15nm ells

WL FG 50nm No. of c TO 9nm Memory state Figure: Samsung L=35nm SL SSL

•Electron transfer between substrate & FG define memory state (write & erase) •FG surrounded by TO & CD acts as electron storage well (non-volatility, need 10yrs), though leak out occurs over time (retention loss) •Repeated Write/Erase (10-100K needed) causes memory 3 wear out (cycling endurance) NAND Flash Scaling

CG •More memory, faster access, reduced cost CD 15nm •Guideline (ITRS roadmap): L=35nm (2009) , FG 50nm 28nm (2010/11), 22nm (2013/14)… TO 9nm •SLC (1bit/cell) , MLC (2 or 3 bit s/ cell) f or hi gh er L=35nm density, higher reliability issues

Scaling penalty: Solution: Discrete trap- (1) Loss of CG – FG coupling based charge storage (2) C ell t o cell cross t alk (3) Non-scaling of TO, FG and CG CD thickness CD, 12nm (4) Non-scaling of operating SiN, 6nm voltage TO, 6nm (5) Higher reliability concern 4 Planer CTF

Devices & test chip demonstrated (Samsung)

•Memory window close down with W/E cycling •Data keeps leaking out (worse than FG!) •Loss of memory operation 5 CTF reliability worse than FG, no product yet Retention Issue

Lateral or Vertical charggge migration

Trap depth of SiN is key to control charge migration

Solution – to cut SiN above STI (Samsung, 2007) 6 NAND 3D Memory

3D CTF ppproposed as a way to move forward below 20nm node: BiCs (Toshiba), TCAT (Samsung)

7 Motivation

CTF reliabilityyp improvement needs:

Understandinggp impact of device p rocessing on material and electrical properties

Proper device design (structure, composition)

Detailed electrical characterization & modeling – feedback for intelligggent manufacturing

8 SANOS Device Structure

Trap parameters: Gate Nt,elec, Φt,elec Nt,hole, Φt,hole

12 nm ))) Ec mmmmmm Φt,elec 15 nm Al2O3 20 nm Si+ N+ tancetancetance (n (n (n

ssssss Φt,hole

DiDiDi N+ Si+ 6 nm SixNy SixNy Ev SiO 3-6 nm TO Al O 2 Trap dist. 2 3 Channel (A.U.)

Charge tunnel from substrate to SiN via TO,

Al2O3 used for leakage blocking 9 P/E Transients

12 8 P/E at +18V/-18V P E R.I. Ref Total memory window 10 r 6 In active 8 4 N-rich 6 ow (V) d (V)

Si-rich dd ex (R.I.) ex (R.I.)

FB 2 4

V N0 N1 N2 N3 N4 Δ 2 0 N+ Si+ /E Win

W11 W2 W3 W6 W8 PP 0 1951.95 -2 2.00

-2 2.05 -4 2.10 -8 -5 -2 1 -4 2.15 10 10 10 10 W11W2W3W6W8 Time (s) Splits High-k blocking dielectric: ¾ Better coupling to channel ¾ Larger memory windows P / E state (memory window) depend on SiN composition 10 ISPP and ISPE

7 6 N0 N0 N+ 5 N+ 6 N1 N1 4 5 N2 N2 N3 3 N3

) 4 )

VV N4 2 N4 VV (

( Si+ FB 3 Si+

FB 1 V 2 V 0 1 -1 0 -2 -1 -3 10 15 20 25 -4 Vg (V) 0 -5 -10 -15 -20 -25 N+ SiN Vg (V) ¾Higher electron trapping efficiency ¾Poor erase characteristics Si+ SiN

¾Low P saturation levels 11 ¾Higher erase efficiency Charge loss (Retention)

N+ 0.8 0.5 5.5 E state loss P state loss 040.4 505.0 0.6 N1 Δ 4.5 Si+ V

N2 0.3 FB (V) + + B (V) (V)

FF N3 040.4 N Si V N+ FB -1.6 N4 -1.7 V 0.2 Δ -1.8 0.2 -1.9 0.1 -2.0 Si+ -2.1 2 3 4 0.0 0.0 10 10 10 1.95 2.00 2.05 2.10 2.15 Time (s) RIR.I. N+ SiN ¾ Deep electron traps - shallow hole traps Si+ SiN ¾ Shallow electron traps - deep hole traps

P/E state retention dependent on SiN composition 12 Tunnel oxide thickness dependence

555.5

) 5.0 VV (

FB 2.5 V 3/6/12 5/6/12 4/6/12 6/6/12 2.0 0.04 ) VFB= 2.5V VV

( 0.00 FB

V -0.04 Δ 101 102 103 104 Time (s)

Thinner TO Æ Increased electron tunnel out from SiN 13 Retention – T dependence

V = 5.5V 0.0 FB 1043 38 N1:Ea = 1.88 eV 10 N2:Ea = 1.38 eV (V) -0.4

FB 33 N3:Ea = 1.01 eV

V 10 ΔΔ 1028 -0.8 23 (s)

10r

0.0 t 1018 VFB = 2.5V 13

(V) 10 -0.4 FB 8 VV o o 10 Δ 25 C 125 C 150oC 180oC 103 -0.8 25 30 35 40 1 2 3 4 10 10 10 10 1/kT(e V-1) Time (s)

Higher activation energy in N+ → Deeper electron traps 14 Retention – E state TO thickness & T effect

0.4 o o E state retention loss 25 C 125 C 150oC 180oC (V)

BB 0.2 ¾ T independent F

No thermal emission of V VFB = -2.0V holes Δ 000.0 0.4 3/6/12 4/6/12 5/6/12 6/6/12

¾ TO independent for > 3nm )) (V No Trap to Band tunneling 0.2

of holes FB VFB = -2.0V V ΔΔ 0.0 101 102 103 104 Different charge loss mechanisms Time (s ) for electrons and holes 15 Endurance – SiN Composition

5 ) VV (

4 FB 4 N1 ) w, V N2 oo VV 3 3 ( N1 N3 FB

V 2 N2 2 N4 N3 Wind P 16V 5ms yy N+ 1 N4 E -15V 1ms 1 Memor

0 0 Si+ 0 1 2 3 4 100 101 102 103 104 10 10 10 10 10 P/E Cycles P/E Cycles

Endurance degradation SiN composition dependent Si-rich devices cycle with negligible erase state degradation 16 Summary

• Comparison of SiN Compositions

Parameter N+ Si+

Electron trap depth Deep Shallow

Hole trap depth Shallow Deep Hole trap density Very low High Split window Not Possible operation possible Endurance High Low degradation

17 P/E Simulation of SiN Flash

• DlDevelop a Si Siltifmulation framework capabl blfe of providi ng useful insight into the physics involved during Program /Erase (P/E) operations.

• Accuratelyyp predicting P/E behavior of SANOS/SONOS memories

• Simul ati on up t o l ong ti me i nst ant s, l arge bi ases

• For different gate stack dimensions

• For different Nitride Compositions

18 Simulation Methodology

•Set P/E bias •Compute Poisson throughout gate stack •Assume TO and CD as pure tunnel barriers, compute tunneling currents in and out of SiN •Compute transport, continuity and SRH (trapping detrapping) in SiN •Com pute tr apped ch ar ges, update Poisson •Continue till end of P/E time

19 Simulation Flow

20 Key Models Incorporated

Tsu-Esaki tunneling formulation Field depppendent capture cross section Poole Frenkel detrapping from traps TtbdtliTrap to band tunneling

21 P/E: Stack Energy Band Diagrams

22 SANOS sample stack properties

Gate Stack Dep. Dimensions SiN Si H /N 2 6 3 Temp RI (nm) type flow ratio (°C) TO SiN CD

N2 0.005 650 2.006 4 6 15 N2 0.005 650 2.006 6 612 N2 0.005 650 2.006 4 6 12

N0 0.01 800 1.987 4 6 12

N0 Æ More N rich SiN; N2 Æ More Si rich SiN Differen t s tac k dimens ions use d t o ch eck rob ust ness 23 ISPP Matching

7.5 Exp Lower Less than 1V change in 6.5 Field dep. σ (n = 3) Vfb Shift σ = const (n = 0) VT (or VFB) for every 1V 5.5 n increment in applied VG σ = σ0/(1+(E/Esat) ) 4.5 (ISPP slope <1V/V) ) VV 3.5 Vfb ( Vfb

Employing the field Δ 2.5 ddtdependent σ enables Lower ISPP Slope accurate prediction of 1.5 ISPP 0.5

-0.5 5 10 15 20 Vg (V)

24 ISPP Matching

9.5 Exp: N2 (4/6/15nm)

Good matching with 8.5 Exp: N2 (4/6/20nm) Exp: N0 (4/6/12nm) ISPP data for varying 757.5 3 σ = σ /(1+(E/E ) ) gate stack thickness 6.5 0 sat

) N2

and nitride VV 5.5 compositions 4.5 Vfb ( Vfb

Δ 3.5

StSame parameter 2.5 N0 values used during P/E 1.5 transient matching (to 050.5 Symbol : Exp : Exp Line : Sim follow) -0.5 4 6 8 10 12 14 16 18 20 22 Normalizedgg( V (V) )

25 P/E Matching

5.5 6 Symbol: Exp Line: Sim Sim 5 4.5

4 3.5 3 (V) V) (( 2.5

Vfb Vfb 2 Vfb Vfb Δ

Δ Vg : -17V - -12V 1.5 1 Vg : 12V-16V

0.5 0 Symbol: Exp Line: Sim -1 -0.5 -6 -5 -4 -3 -2 -1 0 -6 -5 -4 -3 -2 -1 0 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Time (s) (s) Time (s)

Progg(ram and Erase transients (N2-4/6/12 nm SANOS)

26 P/E Matching (Change in TO)

5.5 6 Symbol: Exp Line: Sim Sim 4.5 5

4 3.5 ) V)

VV 3 2.5 Vfb ( Vfb Vfb ( Vfb

Δ 2 Δ 1.5 Vg : -18V - -13V 1

0.5 Vg : 12V-17V 0 Symbol: Exp Line: Sim -0.5 -6 -5 -4 -3 -2 -1 0 -1 10 10 10 10 10 10 10 -6 -5 -4 -3 -2 -1 0 10 10 10 10 10 10 10 Time (s) Time (s)

Program and Erase transients (N2-6/6/12 nm SANOS) 27 P/E Matching (Change in CD)

6.5 7 Symbol: Exp 5.5 Line: Sim 6

5 4.5 4 ) ) VV VV 353.5 3 Vfb ( Vfb Vfb ( Vfb 2.5 Δ Δ 2 Vg : -18V - -13V 1.5 1 Vg : 13V-18V 0.5 0 Symbol: Exp Line: Sim -0.5 -1 -6 -5 -4 -3 -2 -1 0 -6 -5 -4 -3 -2 -1 0 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Time (s) Time (s)

Program and Erase transients (N2-4/6/15 nm SANOS) 28 P/E Matching (Change in SiN)

7.5 7 Symbol: Exp 6 6.5 Line: Sim 5 5.5

4 4.5 (V) 3 fb (V) b 353.5 VV

Vfb

Δ 2 2.5 Vg : -17V - -13V

1 1.5 Vg : 12V- 17V N0-4/6/12nm 0 SblESymbol: Exp 0.5 Line: Sim -1 -0.5 -6 -5 -4 -3 -2 -1 0 -7 -6 -5 -4 -3 -2 -1 0 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Time (s) Time (()s)

Progg(ram and Erase transients (N0-4/6/12 nm SANOS)

29 Extracted parameters (SiN dependence)

Parameter N0 N2 Parameter N0 N2 Electron trap depth 1.8 1.63 Hole Trap Depth (eV) 1.73 1.95 (()eV)

Electron trap density Hole Trap Density 3.3 3.9 1.6 2.6 (1019cm-3) (1019cm-3)

Electron σ const. , σ- Hole σ const. , σ- 0 5.7 5.7 0 88 (10-12 cm2) (10-10 cm2)

Trap-band emission Saturation electric field 13 -1 44 5 6.25 6.25 freq. υ-tbt(10 s ) Esat (10 V/cm)

Values of carrier effective masses, band gaps and dielectric constants taken from published literature 30 Summary

• NdlfltifildddttNew models for electric field dependent capture cross section has been proposed which gives excellent agreement with experimental results

• The robustness of the simulator is verified across different stack thicknesses and different nitride compositions to accurately predict the P/E and ISPP transients

31 Metal Nanodot (m-ND) Flash: Motivation

• Floating Gate Cell Nanodot Cell – poly-Si storage gate – discrete nanodots as storage node Control Gate CtlDiltiControl Dielectric Floating Gate Nanodots eeeeeee Tunnel Dielectric e e e e e

Source Drain Source Drain Channel Channel Defect in Complete charge loss Tunnel Oxide Onlyyp part of stored charge is lost Charge storage in discrete nanodots increases immunity to tunnel oxide defects 32 m-ND Flash Process Flow

SL DL Wafer Clean Tunnel Oxide 40Ǻ Metal Deposition Anneal ILD deposition Metal -- Deposition Si Si Anneal

Control Oxide: 120Ǻ Al2O3 Post Deposition Anneal Singl e L ayer (SL) DlLDual Layer (DL) Metallization: 1000Ǻ Pt

33 Pt Nanodot formation

500oC 700oC 900oC

5Å

Initial Deposited Thickness

10Å

Anneal Temperature Optimization of deposition and annealing processes results in large density (~4x1012cm-2), small size (~3nm) and large area coverage (~30%) 34 Cross-Section TEM

ILD

TO TO

Discrete SL and DL nanodot formation clearly visible

35 SL Memory Window

8 +18V -> +20V 7 SL-S1 6 6 SL-S3 5 T = 10ms w (V) (V)

4 oo 4 FB

V 2 Virgin V FB 3 ry Wind

0 oo 2 -18V -> -20V -2 1 Mem -5 -4 -3 -2 -1 0 INT10 10 10 10 10 17 18 19 Time (s) Gate Voltage (V)

Large Memory window & significant over erase ((psplit window p ossibility)

36 Memory Window: SL vs. DL

10 6 SL (b) 12nm )) 8 DL 4 17nm (V 6 (V) FB

FB 2 Improvement in Improvement : V 4 V memory window nn 0 Ac hieve d: 38% 2 Expected: 42% 0 over SL -2 turatio ration aa uu -2 S -4 T =10ms

Sat -4 -6 Thick CD Split 17 18 19 20 21 22 16 17 18 19 20 21 22 Eq. Gate Voltage (V) (w.r.t SL) Eq. Gate Voltage (V) • 90% improvement in DL window over SL due to increased CD thickness and charge storage in 2nd layer • Memoryyp window improvement onl y with thick CD: 38% , expected (40%) 37 High Temperature Retention

9 8 040.4 8 E-state DL 0.2 7 6 gain

6 (V)

0.0 o

V 5 25 C 4 FB FB

V P-state o -0.2 Δ (V) 4 80 C loss ( V FB 3 o SL 2 -0.4 )

VV 150 C 2 -0.6 DL-S1 1 0 DL-S2 DL -0.8 DL-S3 0 -2 DL-S9 0 1 2 3 4 -101.0 o 10 10 10 10 10 25 C 80oC 150oC o Time (s) Retention Temperature ( C)

Insignificant retention loss Retention better than SiN memory due to deeper potential well for m-ND’s 38 SL vs. DL P/E Endurance

6 6 5 5 4

)) 4 DL-S1 3 Solid: SL-S1 (V 3 DL-S2 FB (V) 2 Open: SL-S3 V DL-S3 FB 2 VV 1 DL-S9 0 1 -1 0 0 1 2 3 4 10 10 10 10 10 100 101 102 103 104 # P/E Cycles # P/E Cycles

Better endurance for DL w.r.t SL No window closure till breakdown 39 P/E Endurance (DL-S9)

8 5 6 4 4 3 ) )

VV 6V VV 6V ( 2 ( 2 75000 FB FB V 1 V 0 0 -2 -1

0 1 2 3 4 10 10 10 10 10 100 101 102 103 104 105 # P/E Cycles # P/E Cycles • 104 cycl es wi th 6V an d 7V m em or y win dow , 2x1 03 cycl es with 8V memory window • Maximum endurance seen when P/E-states are within +6V/-2V 40 • No window closure till breakdown MLC Operation (DL-S9)

4 11 4 o 3 V = 6V 3 T = 80 C PASS 10 2 2 (V) 1 (V) 1 FB FB V 0 01 V 0

-1 -1 00 -2 -2

0 1 2 3 4 10-2 10-1 100 101 102 103 10 10 10 10 10 Disturb Time (s) Retention Time (s)

Excellent separation maintained between the P/E levels after read disturb and high-T retention stress

41 Summary

• Single and dual layer Pt metal Nanodot memory gate stacks demonstrated • Excellent memory window, cycling endurance (>10K w ith 6V w in dow ), pre- andtd post-cycling retention • MLC capabilities • No fundamental reliability show stopper for metal dots in gate stack • Need feasibility demonstration in scaled (sub 20nm node) cells

42 Simulation of m-ND Flash

• To demonstrate viability of m-ND cells in sub 20nm cells (impact of cell size , no. of dots , area coverage, fluctuations, missing dots, dot to dot leakage…..)

• Full 3D electrostatics and tunneling implementation

• SlSolve L apl ace f or pot enti til&lal & elect tifildiric field in gat e st ack

• Non-local tunneling implementation (Tsu -Esaki) for charging of dots (substrate to dot, dot to gate, dot to dot)

• Calculate charges in iterative manner

• PtdthPort dot charges i n equi ilvalent tdi device si mul ltdiated using Sentaurus Device for VT calculation 43 Potential, E-field, Tunnel current (2D cuts)

44 Charge Transients

45 Prediction….

Area coverage, Channel length, No. density, Missing dots…

46 Summary

• Full 3D electrostatics – tunneling framework to study m- ND Flash viability below 20nm node

• Immunity to fluctuations (good)

• Memory window reduction with L scaling (issue)

• Cells becomes edge critical (issue)