Nano-Scale Memory Devices: Space-Time-Energy Trade-offs
Ralph Cavin and Victor Zhirnov Semiconductor Research Corporation
1 Main Points
Many candidates for beyond-CMOS nano-electronics have been proposed for memory, but no clear successor has been identified. MthdlMethodology for sys tem-lllevel ana lilysis
How is maximum performance related to device physics?
2 Three integrated components of a Memory Device:
1) ‘Storage node’
ppyhysics of memor y o peration 2) ‘Sensor’ which reads the state
e.g. transistor 3) ‘Selector’ which allows a memory cell in an array to be addressed transistor diode
All three components impact scaling limits for all memory didevices
3 Space-Time-Energy Metrics
Essential parameters of the memory element are: cell size/density, retention time, access time/speed operating voltage/energy. None of known memory technologies, perform well across all of these parameters At the most basic level, for an arbitrary memory element, there is interdependence between operational voltage, the spppeed of operation and the retention time.
More generally, cell dimensions are also part of the trade-off, hence the Space-Time-Energy compromise
4 Space-Action Principle for Memory
EnergytimeVolume min
E t V min E t L min
E t Nat min
The Least Action principle is a fundamental principle in Physics
E t min (h) Plank’s constant h=6.62x10-34 Js 5 Three Major Memory State Variables
Electron Charge (‘moving electrons’)
e.g. DRAM, Flash
Electron Spin (‘moving spins’)
(STT-) MRAM
Massive particle(s) (‘moving atoms’) e.g. ReRAM, PCM, Nanomechanical, etc.
6 Charge-based Memories
DRAM/SRAM A e- B Floating Gate Memory SONOS
Control
Requirements: 1) Efficient charge injection during programming 2) Suppresse d bac k-flfhflow of charge it/din store/read mo des 3) Efficient erase 4) Min . charge/bit: q=e=1. 6x10-19 Q
7 Barrier-less Ohmic Transport: The most efficient injection, but…
Write I AB ~ V … difficult retention Store
Eb
Charge-based memory is a two-barrier system
Example: DRAM
8 Essential Physics The operation of charge-based memory devices is governed by these basic equations, which put fundamental constraints on device and circuit parameters. Heisenberg Relations Bol tzmann prob abili ty of thermal excitation xp E Et exp( b ) kBT
E 2 2m b I I exp (a E ) I I0 exp( ) 0 b kBT 9 What is the minimum barrier height for the charge -based memory?
Thermionic leakage q CV current (ideal case): Store 25fF×050.5V×=3.75 fCl
Eb Eb Jth Jth0 exp kT
Eb, eV Max. retention Standard DRAM 0.7 4 ms requirement: 64 ms 0.76 24 ms High-barrier are needed for 080.8 77 ms Non-volatile memory 1.4 1 month 1.57 12 years E Min. barrier bmin hihtfheight for NVM
Problem: In Si devices Ebmax CV Selector N el e 2 dC CV E E b,C Sensor 2 E CV b,tr t a I 25fF Storage Node 0 88pF Cint ~ 5 L 1cm Nel~10 a=10 nm -15 3 Vcap=6x10 cm -14 E~10 J tw~1 ns 11 DRAM summary a=10 nm 5 -14 Nel~10 E10E~10 J -15 3 Vcap=6x10 cm t~1 ns EtV~10-9 J-ns-nm3 DRAM inherent issues: Selector -Low barrier height-Volatility Sensor - Remote sensing – Large size of Storage node 12 Flash: Local Sensing of Memory State Storage Node Selector V Sensor 13 Charge injection problem in high- barrier systems High-barriers are needed for Non-volatile memory BUT: Barrier formed by an insulating material (large Eb) cannot be suppressed) – charge transport in the presence of barriers: Non-ohmic charge transport Hot-electron injection Tunneling 14 Floating gate memory: WRITE and STORE modes ‘0’ FET Control channel gate Floating gate q CV tw WRITE I I V q CV STORE tret leakage I I V 15 We need to create an asymmetry in charge transport through the gate dielectric to maximize the Iwrite/Iret ratio Floating gate cell: Write – triangle barrier Retention – trapezoidal barrier V 3 2 1 1 a Eb t ~ ~ expC tret ~ ~ expC2 a Eb 1 T TF N V DT The asyyymmetry in char ge trans port between WRITE and STORE modes is achieved through different shape of barrier (triangle vs. trapezoidal) 16 Retention Analysis: Minimum Barrier Height and Width: Ne ts ~10 y I s Eb Ith Ith0 exp kT Ebmin=1. 8 eV (400K) e2 2mE 2 2m eV I A b V exp a E tun 2 b h a 2 amin=6.9 nm 17 Floating Gate Cell Retention and WRITE characteristics Retention: direct tunneling Write: F-N tunneling: E VF-N>Eb Vstored VF-N VW a V 2 V 2E The retention time strongly W min F N b depends on thickness Si/SiO2: Eb=3.1 V, VWSiO2>6.2 V For lower WRITE voltage Eb should Ideal case be decreased: Ebmin=1.8 eV Vmin>4 V BiBarrier Eb VRV Re t a tRt Re t BiBarrier Eb VWRV WR a tWRt WR Si/SiO2 3.1 eV 2 V 4 nm 4.35 min Si/SiO2 3.1 eV 6.8 V 5.4 nm 1h Si/SiO2 3.1 eV 2V 5.4 nm 20 y Si/SiO2 3.1 eV 12 V 5.4 nm 30ms Min. barrier 1.8 eV 0.9 V 6.9 nm 11 y Min. barrier 1.5 eV 6 V 6.9 nm 40ms 18 Voltage-Time Dilemma For an arbitrary electron-charge based memory element, there is interdepppg,endence between operational voltage, the speed of operation and the retention time. Specifically, the nonvolatile electron-based memory, suffers from the “barrier” issue: High barriers needed for long retention do not allow fast charge injection It is difficult (impossible?) to match their speed and voltages to logic 19 Flash Scaling limits due to ‘Sensor’ Selector Selector Sensor Storage Node 20 Semiconductor Physics sets limits on barrier quality p W W n n Depletion width N A N D W 2 0Vbi N A N D a=2W N C N V W min 2 0 E g ~ 10 nm N C N V a<2W 19 -3 NC – effective density of states in the conduction band, for Si NC=2.8x10 cm 19 -3 NV - effective density of states in the valence band, for Si NV=1.4x10 cm Eg – the band gap, for Si Eg=1.12 eV 21 Flash in the limits of scaling -18 3 V=2x10 cm Electrostatics requires gate Storage Node oxide scaling to maintain FET c harge sens itiv ity ~ 1 0 nm Selector Sensor ~6nm a~Wmin Nel~10 ~20nm Flash FET Tox=const =5.4 nm – degradation of sensitivity and control 22 Flash Summary a=10 nm -15 Nel~10 E10E~10 J t~1 s=1000 ns V=2000 nm3 EtV~10-9 J-ns-nm3 23 Conclusion on ultimate charge- based memories All charge-based memories suffer from the “barrier” issue: High barriers needed for long retention do not allow fast charge injection It i s diffi cu lt (imposs ible ?) to ma tc h the ir spee d an d vo ltages to logic Voltage-Time Dilemma Non-charge-bdNVM?based NVMs? 24 Emerging Memory Devices The Choice of Information Carrier Desired: ‘Benchmark’ memory cell Driver: Cell Scaling Cell size, l <10 nm 8 Store time, ts >10 s ‐7 Write time, tw <10 s ‐7 Read time, tr <10 s Read Voltage, Vr ~1 V Min. sense amplifier requitirement ‐6 (R. Waser et al.) Read current, Ir ~10 A 6 2 Read current density, Jr >10 A/cm Driver: Sensing 26 Spin torque transfer MRAM Magnetic storage node (Moving spins): Energy Limit E KV b ftr f0 exp f0 exp kBT kBT 9 10 -1 (f0~10 -10 c ) 1 KV tstore exp f 0 kBT tstore>10 y the anisotropy constant of a material Eb = KV > 36kBT~1.25 eV volume D. Weller and A. Moser, “Thermal Effect Limits in Ultrahigh-Density Magnetic Recording”, IEEE Trans. Magn. 36 (1999) 4423 28 Magnetic storage node (Moving spins): Size Limit Eb = KV > 36kBT~1.25 eV the anisotropy 3 constant of a material K~0.1-1 J/cm volume V=L2T~2x10 -19 cm3 Thin film: T=2nm L~11nm 4 Nat~10 5 Nspin~10 29 FET selector is biggest part of STT-MRAM in the limits of scaling 6 x 2 nm =12 nm Storag V=1500 nm3 e Node 11 nm Selector J-G. Zhu, Proc. IEEE 96 (2008) 1786 30 STT-RAM summary 3 V=1500 nm tw~1 ns E~107 A/cm2 11nm2 1V 1 ns~10-14 J EtV~10-11 J-ns-nm3 31 Scaled ReRAM Moving atoms: ‘Atomic Relay’ Atomic-scale switch, which opens or closes an electrical circuit byyg the controlled reconfiguration of silver atoms within an atomic-scale junction. Such ‘atomic relays’ operate at room temperature and the only movable part of the switch are the contacting atoms, which open and close a nm-scale gap. Small ((1~1nm) nm) Fast (~1 ns) - projection Low voltagg(e (<1V ) Nature 433, 47-50 (6 January 2005) Quanti zed cond uctance atomic s witch K. Terabe, T. Hasegawa, T. Nakayama and M. Aono 33 Two-sided barrier a=100 nm Au Au 0=5.1 eV 0=5.1 eV Both electrodes influence the potential of the electron within the electrode separation. For small gaps, the near electrode electric fields will influ ence the energy barrier Interface-to-interface interaction 34 Two-side barrier a=100 nm Au Au 0=5.1 eV 0=5.1 eV 35 Two-side barrier a=50 nm Au Au 0=5.1 eV 0=5.1 eV 36 Two-side barrier a=20 nm Au Au 0=5.1 eV 0=5.1 eV 37 Two-side barrier a=10 nm Au Au 0=5.1 eV 0=5.1 eV 38 Two-side barrier a=5 nm Au Au 0=5.1 eV 0=5.1 eV 39 Two-side barrier a=2 nm Au Au 0=5.1 eV 0=5.1 eV 40 Two-side barrier a=2 nm V=0 41 Two-side barrier a=1 nm V=0 42 Two-side barrier a=0.5 nm V=0 43 Two-side barrier a=0.5 nm V=1 volt 44 Two-side barrier a=2 nm V=2 volt 45 Ultimate ReRAM: 1-atom gap 1 a ~ n 3 0.257nm Au A B V=0 Eb=0.64 eV dt=0.09 nm dt< 1 a ~ n 3 0.257nm Au ON/OFF~1.61 A B V=0.5 V Eb=0.38 eV dt=0.075 nm dt< 1 a ~ 2n 3 0.514nm Au ON/OFF~476 A B V=0.5 V Eb=2.63 eV dt=0.37 nm