Panagiotis Dimitrakis Editor Charge- Trapping Non-Volatile Memories Volume 2—Emerging Materials and Structures Charge-Trapping Non-Volatile Memories Panagiotis Dimitrakis Editor Charge-Trapping Non-Volatile Memories Volume 2—Emerging Materials and Structures 123 Editor Panagiotis Dimitrakis Department of Microelectronics Institute of Advanced Materials Athens Greece ISBN 978-3-319-48703-8 ISBN 978-3-319-48705-2 (eBook) DOI 10.1007/978-3-319-48705-2 Library of Congress Control Number: 2016956818 © Springer International Publishing AG 2017 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland Contents 1 Materials and Device Reliability in SONOS Memories............ 1 Krishnaswamy Ramkumar 2 Charge-Trap-Non-volatile Memory and Focus on Flexible Flash Memory Devices ..................................... 55 Konstantina Saranti and Shashi Paul 3 Hybrid Memories Based on Redox Molecules ................... 91 Nikolaos Glezos 4 Organic Floating Gate Memory Structures ..................... 123 S. Fakher, A. Sleiman, A. Ayesh, A. AL-Ghaferi, M.C. Petty, D. Zeze and Mohammed Mabrook 5 Nanoparticles-Based Flash-Like Nonvolatile Memories: Cluster Beam Synthesis of Metallic Nanoparticles and Challenges for the Overlying Control Oxide Layer........... 157 E. Verrelli and D. Tsoukalas Index ...................................................... 211 v Chapter 1 Materials and Device Reliability in SONOS Memories Krishnaswamy Ramkumar 1.1 Introduction Non-volatile memories for data and code storage have been growing rapidly in performance and capacity over last few decades. With the advent of the many widely used consumer electronic gadgets such as cell phones, laptop computers, tablets, and electronic games, the need for non-volatile memories has been ever increasing recently. While the need for larger and larger memory capacity is obvious, there has also been an increasing demand for more and more robust data retention performance over a widening range of temperature. This is because the non-volatile memories are now getting into gadgets used in industrial and auto- motive environment. This coupled with the need for low cost solutions is chal- lenging the memory technology. SONOS (Silicon–Oxide–Nitride–Oxide–Silicon) seems to offer the non-volatile memory solutions in an ever widening range of applications. The key features of the SONOS memory device and their dependence on material characteristics are discussed in the following sections. 1.2 History of SONOS Memory Devices SONOS memory device has been known for many decades. The initial work on SONOS devices was reported in the late 1960s. The MNS (Metal–Nitride–Silicon) structure was first proposed as an alternate to the MOS (Metal–Oxide–Silicon) K. Ramkumar (&) Cypress Semiconductor, 3833 North First Street, San Jose, USA e-mail: [email protected] © Springer International Publishing AG 2017 1 P. Dimitrakis (ed.), Charge-Trapping Non-Volatile Memories, DOI 10.1007/978-3-319-48705-2_1 2 K. Ramkumar structure for superior dielectric strength [1]. However, instabilities were found with this device due to the large density of interface states at the Nitride–Silicon inter- face. The MNOS (Metal–Nitride–Oxide–Silicon) was proposed as a solution to this instability on account of the stable interface between silicon dioxide and silicon [2]. The charge storage in the MNOS structure was first observed as a hysteresis in the threshold voltage as a function of the gate voltage as shown in Fig. 1.1 [3]. In these devices, the nitride layer was identified as the charge storage layer due to the traps present and the oxide layer was proposed for injecting electrons or holes by direct tunneling. These early MNOS devices were made using the Aluminum gate technology The MNOS concept was studied widely in the 1970s and applied to memory structures [4–9]. With the advent of polysilicon gate technology, the Aluminum was replaced by polysilicon and SNOS devices became available. In the 1980s, to prevent carrier injection from the gate electrode to the nitride, another oxide layer was introduced between the nitride layer and the polysilicon gate and the SONOS device was invented [10]. The SONOS transistor was thus conceived as a storage element with its structure being almost identical to that of a MOS tran- sistor with the gate dielectric being replaced by a ONO dielectric. This device has been studied extensively in the last three decades to understand the carrier transport, trapping and de-trapping mechanisms in the nitride layer. Several mechanisms have been proposed such as direct or modified Fowler–Nordiehm tunneling of carriers from the silicon to the nitride through the oxide and subsequent capture of these carriers by the deep traps in the nitride. The research on the SONOS device has continued with more sophisticated modeling of the transport and trapping mecha- nisms [11–13]. With the highlighting of the charge trapping mechanism in the SONOS device and its application in memories, the SONOS device also got referred to as a “Charge Trap Memory Device” or “CT” memory. Fig. 1.1 First observation of memory effect in MNOS device [3] 1 Materials and Device Reliability in SONOS Memories 3 1.3 Floating Gate and SONOS Memories SONOS-based memories were first introduced in the 1980s with a 16 Kbit EEPROM as one of the first products. The competition at that time was from Floating gate memories. The different types of Floating gate transistors used in memories are shown in Fig. 1.2. In all cases, a conducting but electrically floating polysilicon layer is used for charge storage. These devices are used even in present day Flash memories with device scaling being the main driver of the increase in memory density. Many enhancements such as Multi-levels and scaling have been introduced into the Floating gate technology to extend its capability. It is clear from the above figure that significant process changes are required to realize the floating gate memory device—a second polysilicon layer deposition and additional patterning steps. However, the retention performance of the Floating gate device is very robust on account of the relatively thick (60–80 Å) tunnel oxide being used. A SONOS memory device, on the other hand, greatly resembles a regular MOSFET and requires very few changes to the basic MOS process. The only significant process change is the formation of the ONO dielectric which forms the gate dielectric of the SONOS device. A typical SONOS FET is shown in Fig. 1.3. The SONOS memories could not compete well against the Floating gate memories, in the 1980s because the program/erase voltages required to get sig- nificant tunneling currents were very high (>20 V) on account of the difficulty in scaling down the thicknesses of the layers of the ONO stack. With availability of better film deposition and metrology equipment subsequently, the ONO stack CG CG CG Float Float 14VSG Float e- Float SL SG FG FG FG e- S e- D S D S D Fig. 1.2 Different floating gate device used for memories Fig. 1.3 Schematic cross section of a typical SONOS Salicide ONO FET Poly Source Well Drain D-N Well 4 K. Ramkumar thickness could be scaled down with robust process control and SONOS memories capable of program/erase at lower voltages were conceived. Additionally, extensive research on charge trap devices yielded novel methods of program and erase that allowed low voltage operation [14]. With this feature, SONOS memories became competitive with the floating gate memories and have carved a niche in the NVM market. The SONOS memory technology claims to be much less complex as compared to the Floating gate technology [15]. 1.4 SONOS Memory Devices As mentioned earlier, the simplest SONOS device closely resembles a normal CMOS FET (Fig. 1.4). The main difference is that the gate dielectric now is a ONO dielectric made up of a tunnel oxide, a nitride and a blocking oxide. The transistor can be NMOS or PMOS and can be either enhancement type or depletion type. Depletion type has the benefit of a buried channel which keeps the carriers in the channel away from the interface states in Tunnel oxide–Semiconductor interface. If the memory stack is described in more general terms, the three layers can be referred to as 1. The tunneling layer, used for injecting charge carriers into the trap layer and to prevent trapped charges in the trap layer from being lost to the substrate. 2. The charge trap layer which stores charge by trapping the mobile carriers in traps located in the band gap. 3. The blocking layer which keeps the trapped charge in the trap layer isolated from the gate. N+ N+ P-Well Deep N-Well Poly Blocking Oxide (HTO) Nitride Tunnel Oxide Silicon Fig.