Investigation on Tunneling-Based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation

applied sciences

Article Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation

Kitae Lee 1,2 , Sihyun Kim 1,2, Daewoong Kwon 3,* and Byung-Gook Park 1,2,*

1 Inter-University Semiconductor Research Center (ISRC), Seoul National University, Seoul 08826, Korea; [email protected] (K.L.); [email protected] (S.K.) 2 Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Korea 3 Department of Electrical Engineering, Inha University, Incheon 22212, Korea * Correspondence: [email protected] (D.K.); [email protected] (B.-G.P.); Tel.: +82-32-860-7414 (D.K.); +82-2-880-7282 (B.-G.P.) Received: 6 June 2020; Accepted: 17 July 2020; Published: 20 July 2020

Abstract: Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large VDD (> 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate ﬁeld eﬀect transistors (FE-TCMOS) is proposed and its performance evaluated through 2-D technology computer-aided design (TCAD) simulations. As a result, it is revealed that the larger subthreshold swing and the steeper subthreshold swing are achievable by polarization switching in the ferroelectric layer, compared to conventional MOSFETs with high-k gate oxide, and thus the FE-TCMOS can have the more stable (larger static noise margin) ternary inverter operations at the lower VDD.

Keywords: ferroelectric; band-to-band tunneling; ternary CMOS; low power devices; semiconductor devices

1. Introduction Tunneling-based ternary complementary metal-oxide-semiconductor (TCMOS) technology has been reported recently [1–3]. Instead of the binary systems of the existing complementary metal-oxide-semiconductor (CMOS) technology, the third output voltage (Vout) state is formed in the ternary systems, and it has been spotlighted in terms of scaling and energy-efficiency [4,5]. In the TCMOS, the off-current (IOFF) levels of NMOS (n-type MOS) and PMOS (p-type MOS), which are generated by band-to-band tunneling (BTBT), should be matched to form the third Vout state during inverter operations. In contrast to conventional ternary devices that utilize multithreshold voltage (Multi-Vt) transistors [6–12], the TCMOS can perform ternary operations using a pair of NMOS/PMOS with a single voltage (Vt); the fabrication process is also comparable to the conventional CMOS process, because it can be fabricated only by introducing one additional doping process. However, the TCMOS has the disadvantage of slow switching speed caused by low on-state current (ION). In general CMOS, the time required for Vout state transition is sub-nsec, while it takes ~µsec for the TCMOS to be switched [1]. In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS), consisting of ferroelectric-gate field effect transistor (FeFET), is proposed to improve switching speed and supply voltage (VDD) scaling since it is well-known that the FeFET boosts ION and steepens

Appl. Sci. 2020, 10, 4977; doi:10.3390/app10144977 www.mdpi.com/journal/applsci Appl. Sci. 2020, 10, 4977 2 of 7 subthreshold swing (SS), compared to conventional MOSFETs [13–17]. To verify the operations of the Appl. Sci. 2020, 10, x FOR PEER REVIEW 2 of 7 FE-TCMOS, technology computer-aided design (TCAD) simulations with the calibrated ferroelectric materialsubthreshold parameters swing are(SS) used, compared and the to ternary conventional operations MOSFETs are rigorously [13–17]. To compared verify the between operations TCMOS of the andFE- FE-TCMOS.TCMOS, technology computer-aided design (TCAD) simulations with the calibrated ferroelectric material parameters are used and the ternary operations are rigorously compared between TCMOS 2. Experiments and Simulation Methods and FE-TCMOS. To embody the ferroelectricity in FE-TCMOS (Figure1a,b), a metal-ferroelectric-metal (MFM) capacitor2. Experiments was first and fabricated Simulation using Methods hafnium zirconium oxide (HZO) as ferroelectric material, and polarization-electric field (P-E) characteristics were obtained. Then, the simulation parameters To embody the ferroelectricity in FE-TCMOS (Figure 1a,b), a metal-ferroelectric-metal (MFM) of the ferroelectric material were achieved by fitting the simulation data to the measurement P-E capacitor was first fabricated using hafnium zirconium oxide (HZO) as ferroelectric material, and data (Figure1c) using the Sentaurus 2-D TCAD simulations where Preisach model was used for the polarization-electric field (P-E) characteristics were obtained. Then, the simulation parameters of the calibration [18]. The equation for the model is as follows: ferroelectric material were achieved by fitting the simulation data to the measurement P-E data (Figure 1c) using the Sentaurus 2-D TCAD simulations where Preisach model was used for the Paux = c Ps tanh(w (E Ec)) + Po f f (1) calibration [18]. The equation for the model· · is as follows· ±: where E is electric field, Paux is auxiliary polarization, and 푃푎푢푥 = 푐 ⋅ 푃푠 ⋅ tanh(푤 ⋅ (퐸 ± 퐸푐)) + 푃표푓푓 (1)

1 P + P where E is electric field, Paux is auxiliaryw polarization= ln s, andr (2) 1 푃 +푃 푤 =2Fc ln P푠s 푟 P r (2) 2퐹푐 푃푠−−푃푟 푑 푃푎푢푥[퐸(푡)]−푃(푡) d 푃(푡) =Paux[E(t)] P(t ) (3) P푑푡(t) = 휏푝 − (3) dt τ p wherewhereP sPiss is saturation saturation polarization, polarization,P rPisr is remanent remanent polarization, polarization,E cEisc is coercive coercive field, field, and andτ pτpis is relaxation relaxation timetime for for polarization polarization in in ferroelectric ferroelectric material. material Figure. Figure1c 1 indicatesc indicates that that the the measured measured and and the the calibrated calibrated P-EP-E curves curves are are well-matched well-matched [15]. [15] Here,. Here, the relaxation the relaxation time τ timep is set τp to is 250 set ns. to These250 ns. ferroelectric These ferroelectric material parametersmaterial parameters are reflected a tore thereflected gate dielectric to the gate of FE-TCMOS dielectric forof theFE- simulations,TCMOS for whereasthe simulation high-ks dielectric, whereas (εhighb = 25)-k dielectric is applied ( insteadεb = 25) ofis the applied ferroelectric instead material of the ferroelectric for TCMOS simulations.material for TCMOSFigure1a simulations. shows the schematicFigure 1a diagram shows the of theschematic FE-TCMOS diagram implemented of the FE- inTCMOS the simulations. implemented A P-N in the junction simulation is formeds. A P by-N introducingjunction is formed an additional by introducing doped layer an additional between the doped source layer and between the drain the under source the and channel. the drai Whenn under a drainthe channel voltage. When (VD) is a applied,drain voltage the band-to-band (VD) is applied, tunneling the band (BTBT)-to-band is generatedtunneling at(BTBT) the drain-side is generated P-N at junctionthe drain of-side the layer,P-N junction and thus of thethe P-Nlayer junctions, and thus formed the P-N by junctions adding formed the doped by adding layer can the be doped modeled layer ascan a drain-side be modeled tunnel as a drain junction-side diode. tunnel Figure junction1b is diode. the circuit Figure schematic 1b is the diagramcircuit schematic of the FE-TCMOS, diagram of whichthe FE shows-TCMOS, that which the tunnel shows junction that the diode tunnel is connected junction diode to the is V outconnectednode as to contrast the Vout to node a conventional as contrast CMOS.to a conventional Specific simulation CMOS. Specific parameters simulation are listed parameters in Table1. are listed in Table 1.

(a) (b) (c) VDD 40

)

2 Simulated Curve 30 Experimental Curve cm 20 Ternary CMOS

 10

( 0

Vin Vout -10 -20 -30 -40

Polarization -3 -2 -1 0 1 2 3 V Electric Field (MV/cm) SS FigureFigure 1. 1.( a(a)) The The schematic schematic diagram diagram of of TCMOS TCMOS consisting consisting of of ferroelectric-gate ferroelectric-gate field field e ffeffectect transistors transistors (FE-TCMOS).(FE-TCMOS). The The ferroelectric ferroelectric layer layer is is inserted inserted between between gate gate and and oxide oxide interfacial interfacial layer. layer. ( b(b)) The The circuitcircuit schematic schematic diagram diagram of of FE-TCMOS. FE-TCMOS. Tunnel Tunnel junction junction diode diode is is located located under under the the drain-side drain-side channel.channel. (c )(c) Experimental Experimental polarization-electric polarization-electric field (P-E) field curve(P-E) and curve calibrated and calibrated P-E curve by P-E technology curve by computer-aidedtechnology computer design-aided (TCAD) design simulation. (TCAD) simulation.

Appl. Sci. 2020, 10, x FOR PEER REVIEW 3 of 7

Appl. Sci. 2020, 10, 4977 Table 1. Simulation Parameters. 3 of 7

Parameter Description Value LG TableG 1.ateSimulation Length Parameters. 1 μm NS Source Doping Concentration 1020 cm-3 (Arsenic) Parameter Description Value ND Drain Doping Concentration 1020 cm-3 (Arsenic) µ NLGB BodyGate Doping Length Concentration 11017m cm-3 (Boron) 20 3 NS Source Doping Concentration 10 cm− 19(Arsenic)-3 NT Tunneling Layer Doping Concentration 20 5×103 cm (Arsenic) ND Drain Doping Concentration 10 cm− (Arsenic) TTNL Tunneling Layer Thickness 17 3 20 nm NB Body Doping Concentration 10 cm− (Boron) TNOX TunnelingInterfacial Layer Doping layer Concentration Thickness 5 1019 cm 3 (Arsenic)1 nm T × − TTTNLFE TunnelingFerroelectric Layer Thickness Thickness 20 nm 10 nm TPOXs InterfacialSaturation layer ThicknessPolarization 1 nm18 μC/cm2 T Ferroelectric Thickness 10 nm FEr 2 P Remanent Polarization 30 μC/cm2 Ps Saturation Polarization 18 µC/cm Ec Coercive Field 0.752 MV/cm Pr Remanent Polarization 30 µC/cm p τEc RelaxationCoercive Time Field for Polarization 0.75 MV/cm250 ns ετbp PermittivityRelaxation Constant Time for of Polarization Ferroelectric Material 250 ns 25 εb Permittivity Constant of Ferroelectric Material 25 3. Results and Discussion 3. Results and Discussion 3.1. Tunneling-based ternary CMOS with Ferroelectric-Gate Field effect transistor 3.1. Tunneling-Based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Before identifying the operations of TCMOS, the electrical characteristics of TNMOS (tunneling- Before identifying the operations of TCMOS, the electrical characteristics of TNMOS based ternary NMOS) and TPMOS (tunneling-based ternary PMOS) were first verified (Figure 2). (tunneling-based ternary NMOS) and TPMOS (tunneling-based ternary PMOS) were first verified Compared to conventional N/PMOS for CMOS, TNMOS/TPMOS have the larger Vt (close to VDD) (Figure2). Compared to conventional N /PMOS for CMOS, TNMOS/TPMOS have the larger Vt and the constant IOFF regardless of gate voltage (VG). As aforementioned, the IOFF is generated by the (close to VDD) and the constant IOFF regardless of gate voltage (VG). As aforementioned, the IOFF is BTBT at the drain-side tunnel junction and hence the IOFF increases with the larger VD (Figure 3). For generated by the BTBT at the drain-side tunnel junction and hence the IOFF increases with the larger the stable TCMOS operations, the IOFF of TNMOS /TPMOS needs to be almost the same at VD = ~ half VD (Figure3). For the stable TCMOS operations, the I OFF of TNMOS /TPMOS needs to be almost the VDD because the third Vout state between Vout = 0 V and Vout = VDD is formed using VDD divided by the same at VD = ~half VDD because the third Vout state between Vout = 0 V and Vout = VDD is formed resistance difference (namely, the IOFF difference) between them [2], if the TNMOS /TPMOS are using VDD divided by the resistance difference (namely, the IOFF difference) between them [2], if the simplified as variable resistors with respect to VD. Thus, the doping concentration modulation for the TNMOS /TPMOS are simplified as variable resistors with respect to VD. Thus, the doping concentration tunneling layer is essential to adjust the IOFF in the TCMOS fabrication process. modulation for the tunneling layer is essential to adjust the IOFF in the TCMOS fabrication process.

10-2 |V | N/PMOS D ) TN/TPMOS 1.0 V A 0.5 V ( -4 10 0.05 V

-6

10-8

Drain Current

10-10 -1.0 -0.5 0.0 0.5 1.0 Gate Voltage (V) Figure 2. The transfer characteristics of conventional NMOS/PMOS and TNMOS/TPMOS. Due to the Figure 2. The transfer characteristics of conventional NMOS/PMOS and TNMOS/TPMOS. Due to IOFF generated from the tunnel junction, the IOFF increases with the larger drain voltage. Compared with the IOFF generated from the tunnel junction, the IOFF increases with the larger drain voltage. conventional NMOS/PMOS, TNMOS/TPMOS are designed to have larger voltage (V ). Compared with conventional NMOS/PMOS, TNMOS/TPMOS are designed to havet larger voltage

(Vt). The ferroelectric material (e.g., doped HfO2) can have the larger permittivity by a polarization switching than the general high-k dielectric material (e.g., HfO2). The slope of the P-E curve refers to the permittivity of the dielectric, and the slope of the P-E curve in the ferroelectric material is larger than that of the high-k dielectric. Therefore, when the high-k dielectric is replaced with the ferroelectric layer in the gate stack of a MOSFET, the larger ION and the steeper SS are achievable. Figure4a shows the comparison of the transfer characteristics between conventional TNMOS /TPMOS and FE-TNMOS (ferroelectric-gate ﬁeld eﬀect transistors-TNMOS)/TPMOS. As expected, the larger Appl. Sci. 2020, 10, x FOR PEER REVIEW 4 of 7

Doping Concentration (cm-3) (a) (b) VD = 0.05 V Appl. Sci. 2020, 10, 4977 Body Drain 2.001×1020 4 of 7 3.421×1017 5.850×1014 Tunneling Layer 7.503×1011 -1.462×1014 ION and the improved SS are observed in the FE-TNMOS/FE-TPMOS-8.549 (ferroelectric-gate×1016 field effect -5.000×1019 transistors-TPMOS) (Figure4a). Considering that the high V t is inevitable for TCMOS operations, it is expected that FE-TCMOS can be operated at the more scaled VDD. In other words, at a specific V , FE-TCMOS might have a faster operation speed and aBand larger to Band static Generation noise (cm-3s-1 margin) than DD (c) VD = 0.5 V (d) VD = 1.0 V 6.145×1026 conventionalAppl. Sci. TCMOS. 2020, 10, x FOR PEER REVIEW 4 of 7 7.584×1021 9.360×1016 9.388×1011 Doping-1.754 Concentration×1016 (cm-3) (a) (b) VD = 0.05 V Body Drain -1.4212.001××10102120 -1.151×102617 3.421×10 5.850×1014 Tunneling Layer 11 Figure 3. (a) The schematic diagram of tunneling layer and doping concentration7.503×10 in case of -1.462×1014 TNMOS. The band-to-band tunneling generation rate at tunnel junction- 8.549 with× 10 respect16 to drain voltage. The drain voltages are (b) 0.05, (c) 0.5, and (d) 1.0 V, respectively.-5.000 The×1019 band-to-band tunneling generation rate becomes larger with the higher drain voltage.

The ferroelectric material (e.g., doped HfO2) can have the larger permittivityBand to Band Generation by a polarization (cm-3s-1) (c) VD = 0.5 V (d) VD = 1.0 V switching than the general high-k dielectric material (e.g., HfO2). The slope6.145 of ×the1026 P-E curve refers to the permittivity of the dielectric, and the slope of the P-E curve in the ferroelectric7.584×1021 material is larger 9.360×1016 than that of the high-k dielectric. Therefore, when the high-k dielectric9.388 ×is10 11replaced with the ferroelectric layer in the gate stack of a MOSFET, the larger ION and the -steeper1.754×1016 SS are achievable. Figure 4a shows the comparison of the transfer characteristics-1.421 between×1021 conventional -1.151×1026 TNMOS/TPMOS and FE-TNMOS (ferroelectric-gate field effect transistors-TNMOS)/TPMOS. As expected, the larger ION and the improved SS are observed in the FE-TNMOS/FE-TPMOS Figure 3. (Figurea) The 3. schematic (a) The schematic diagram diagram of tunneling of tunneling layer andlayer doping and doping concentration concentration in incase case of of TNMOS. (ferroelectric-gate field effect transistors-TPMOS) (Figure 4a). Considering that the high Vt is The band-to-bandTNMOS. tunneling The band-to generation-band tunneling rate atgeneration tunnel junction rate at tunnel with respect junction to with drain respect voltage. to drain The drain inevitable for TCMOS operations, it is expected that FE-TCMOS can be operated at the more scaled voltage. The drain voltages are (b) 0.05, (c) 0.5, and (d) 1.0 V, respectively. The band-to-band voltagesV areDD. In (b other) 0.05, words, (c) 0.5, at anda specific (d) 1.0 VDD V,, FE respectively.-TCMOS might The have band-to-band a faster operation tunneling speed generationand a larger rate tunneling generation rate becomes larger with the higher drain voltage. becomesstatic larger noise with margin the higherthan conventional drain voltage. TCMOS.

The 10ferroelectric-3 material (e.g., doped HfO2) can 200have the larger permittivity by a polarization c - TNMOS/TPMOS c-TNMOS

switching) than-4 the general high-k dielectric material (e.g., HfO2). The slope of the P-E curve refers to 10 180 c-TPMOS A FE-TNMOS/TPMOS ( FE-TNMOS

) the permittivity of the dielectric, and the slope of the P-E curve in the ferroelectric material is larger 10-5 160 FE-TPMOS than that of the high-k dielectric. Therefore, when the high-k dielectric is replaced with the 10-6 dec 140 ferroelectric layer in the gate stack of a MOSFET, the larger ION and the steeper SS are achievable.

-7 120

10 mV/

Figure 4a shows the comparison of the transfer( characteristics between conventional -8 100 TNMOS/TPMOS10 and FE-TNMOS (ferroelectric-gate field effect transistors-TNMOS)/TPMOS. As

SS -9 80 expected,Drain Current 10 the larger ION and the improved SS are observed in the FE-TNMOS/FE-TPMOS (a) 60 (b) (ferroelectric-10 -gate field effect transistors-TPMOS) (Figure 4a). Considering that the high Vt is 10 -9 -8 -7 -6 -5 inevitable for-1.5 TCMOS-1.0 -0.5operations,0.0 0.5 it is1.0 expected1.5 that FE-TCMOS10 10 can be10 operated10 at the10 more scaled Gate Voltage (V) Drain Current (A/m) VDD. In other words, at a specific VDD, FE-TCMOS might have a faster operation speed and a larger Figurestatic 4. (noisea) The margin transfer than characteristics conventional TCMOS of conventional. TNMOS/TPMOS and FE-TNMOS/TPMOS.

The higher-3 I Figureand 4. (a) the The steeper transfer characteristics SS are shown of conventional in FE-TNMOS TNMOS/TPMOS./TPMOS and (b FE) The-TNMOS SS/TPMOS. of conventional 10 ON 200 The higher ION and c - TNMOS/TPMOS the steeper SS are shown in FE-TNMOS/TPMOSc-TNMOS. (b) The SS of conventional

TNMOS) /TPMOS-4 and FE-TNMOS/TPMOS with respect to drain current. In the entire drain current 10 TNMOS/TPMOS and FE-TNMOS/TPMOS with respect180 to drain current.c-TPMOS In the entire drain current A FE-TNMOS/TPMOS ( FE-TNMOS

) range, FE-TNMOS /TPMOS have a lower SS. 10-5 range, FE-TNMOS/TPMOS have a lower SS. 160 FE-TPMOS 3.2. Operation10 Characteristics-6 of FE-TCMOS dec 140

3.2. Operation-7 characteristics of FE-TCMOS 120 10 mV/

(

Prior to the evaluation of FE-TCMOS, the voltage transfer characteristics (VTC) of conventional -8 100 10 TCMOS and CMOS were first verified. Figure5a showsSS the VTC of TCMOS and CMOS where it can be -9 80 Drain Current 10 confirmed that TCMOS(a) is stably operated with VDD = 1 V60 as a ternary CMOS with the(b) third Vout state. 10-10 Then, FE-TCMOS-1.5 and-1.0 FE-CMOS-0.5 0.0 were0.5 1.0 embodied1.5 by reflecting10-9 10 the-8 calibrated10-7 10-6 ferroelectric10-5 material parameters to the gateGate stack. Voltage To evaluate (V) the electrical characteristicsDrain Current of FE-TCMOS (A/m) and FE-CMOS, a 7-stage inverter chain was configured in mixed-mode device and circuit simulations as shown in

Figure5b. TheFigure input 4. (a) pulse, The transfer which characteristics has the transition of conventional from TNMOS 0 V/TPMOS to V DD and(1 FE V)-TN withMOS/TPMOS. 1 ms rising time, was applied, andThe higher the average ION and the propagation steeper SS are shown delay in of FE V-TNMOS/TPMOSout was extracted. (b) The as SS the of conventional switching time from each inverter stage.TNMOS Figure/TPMOS5 andc demonstrates FE-TNMOS/TPMOS the switchingwith respect to time drain as current. a function In the entire of the drain number current of inverter stages. It is foundrange, that FE-TN theMOS FE-TCMOS/TPMOS have has a lower the SS. slower switching speed than the FE-CMOS. It has been reported that the tunneling-based TCMOS has the slower (µsec order) switching speed compared to that (psec3.2. Operation order) characteristics of the CMOS of FE [1-TCMOS], because the switching delay of an inverter is proportional to the driving current of n/p-type transistors. That is, TNMOS/TPMOS not only have the low ION Appl. Sci. 2020, 10, x FOR PEER REVIEW 5 of 7

Prior to the evaluation of FE-TCMOS, the voltage transfer characteristics (VTC) of conventional TCMOS and CMOS were first verified. Figure 5a shows the VTC of TCMOS and CMOS where it can be confirmed that TCMOS is stably operated with VDD = 1 V as a ternary CMOS with the third Vout state. Then, FE-TCMOS and FE-CMOS were embodied by reflecting the calibrated ferroelectric material parameters to the gate stack. To evaluate the electrical characteristics of FE-TCMOS and FE- CMOS, a 7-stage inverter chain was configured in mixed-mode device and circuit simulations as shown in Figure 5b. The input pulse, which has the transition from 0 V to VDD (1 V) with 1 ms rising time, was applied, and the average propagation delay of Vout was extracted as the switching time from each inverter stage. Figure 5c demonstrates the switching time as a function of the number of inverter stages. It is found that the FE-TCMOS has the slower switching speed than the FE-CMOS. It has been reported that the tunneling-based TCMOS has the slower (μsec order) switching speed compared to that (psec order) of the CMOS [1], because the switching delay of an inverter is proportional to the driving current of n/p-type transistors. That is, TNMOS/TPMOS not only have the low ION due to the high Vt, but 0 V to half VDD and VDD to half VDD transitions are formed by the IOFF. Considering the 250 ns ferroelectric relaxation time (namely, polarization switching time) obtained in the previous study [15], if the ferroelectric layer is introduced to the CMOS, the boosted ION and the steeper SS cannot be achieved since the switching speed of the CMOS inverter is much faster than the polarization switching. This means that a ferroelectric material having a faster switching speed (sub-psec polarization switching) than the CMOS switching is required to apply the ferroelectric layer to conventional CMOS. In contrast, the operating speed of the tunneling-based TCMOS is slower than the polarization switching of the ferroelectric material. Therefore, the Appl.ferroelectric Sci. 2020, 10 layer, 4977 can effectively play a role as a current booster in the TCMOS. 5 of 7 Subsequently, the switching speed is compared between FE-TCMOS and TCMOS with respect to the number of inverter stages. Figure 6a shows that the switching delay difference between them due to the high V , but 0 V to half V and V to half V transitions are formed by the I . is negligible, becauset the switching speedDD is determinedDD by theDD IOFF and both devices have almostOFF the Considering the 250 ns ferroelectric relaxation time (namely, polarization switching time) obtained in same IOFF. The static noise margin (SNM) of FE-TCMOS was investigated from the butterfly curves the previous study [15], if the ferroelectric layer is introduced to the CMOS, the boosted I and the with various VDDs (0.5 V, 0.7 V, and 1.0 V), and the SNMs were compared with those ONof TCMOS. steeper SS cannot be achieved since the switching speed of the CMOS inverter is much faster than Figure 6b indicates that the FE-TCMOS has the sufficient SNM even at low VDD. Additionally, Figure the6c shows polarization the SNM switching. comparison This between means that FE a-TCMOS ferroelectric and TCMOS. material The having improvement a faster switching of the SNM speed is (sub-psec polarization switching) than the CMOS switching is required to apply the ferroelectric layer extracted as the increase of the SNM in percentage with respect to VDD. It is observed that the FE- to conventional CMOS. In contrast, the operating speed of the tunneling-based TCMOS is slower than TCMOS has the larger SNM and the SNM becomes improved further at the lower VDD, implying that the polarization switching of the ferroelectric material. Therefore, the ferroelectric layer can eﬀectively the FE-TCMOS is more advantageous as VDD decreases. These results can be understood better by the play a role as a current booster in the TCMOS. steeper SS and the larger ION of FE-TNMOS/TPMOS than by conventional TNMOS/TPMOS.

(a) (b) (c)

1.0 -1 10 FE-CMOS 7 Stage 10-2 FE-TCMOS 10-3

) -4

V 10

( -5 10

0.5 out 10-6

V -7 Vin T Vout V0 V1 V6 V7 10 Ferroelectric switching delay 10-8 TCMOS -9 CMOS 10 0.0 Time (sec) Switching 10-10 0.0 0.5 1.0 1 2 3 4 5 6 7 Vin (V) Number of Stage Figure 5. (a) The voltage transfer curves of conventional complementary metal-oxide-semiconductor (CMOS)Figure and 5. ternary(a) The complementary voltage transfer metal-oxide-semiconductor curves of conventional (TCMOS). complementary The third metal Vout -stateoxide is- formedsemiconductor in TCMOS (CMOS by voltage) and dividing ternary dependingcomplementary on IOFF metaldiff-erenceoxide-semiconductor between TPMOS (TCMOS and TNMOS.). The (b)third The circuitVout state schematic is formed diagram in TCMOS of 7-stage by voltage inverter dividing chain. ( cdepending) The switching on IOFF time difference of FE-CMOS between and FE-TCMOSTPMOS and with TNMOS. respect (b) to theThe number circuit schematic of inverter diagram stages. Theof 7- switchingstage inverter time chain. of FE-CMOS (c) The switching is pico-sec order,time whereas of FE-CMOS FE-TCMOS and FE is- micro-secTCMOS with order. respect The dashed to the linenumber represents of inverter ferroelectric stages. switchingThe switching delay, whichtime is of larger FE-CMOS than the is switching pico-sec order, time of whereas FE-CMOS. FE-TCMOS is micro-sec order. The dashed line represents ferroelectric switching delay, which is larger than the switching time of FE-CMOS. Subsequently, the switching speed is compared between FE-TCMOS and TCMOS with respect to the number of inverter stages. Figure6a shows that the switching delay di fference between them is negligible, because the switching speed is determined by the IOFF and both devices have almost the same IOFF. The static noise margin (SNM) of FE-TCMOS was investigated from the butterfly curves with various VDDs (0.5 V, 0.7 V, and 1.0 V), and the SNMs were compared with those of TCMOS. Figure6b indicates that the FE-TCMOS has the su fficient SNM even at low VDD. Additionally, Figure6c shows the SNM comparison between FE-TCMOS and TCMOS. The improvement of the SNM is extracted as the increase of the SNM in percentage with respect to VDD. It is observed that the FE-TCMOS has the larger SNM and the SNM becomes improved further at the lower VDD, implying that the FE-TCMOS is more advantageous as VDD decreases. These results can be understood better by the Appl. Sci. 2020, 10, x FOR PEER REVIEW 6 of 7 steeper SS and the larger ION of FE-TNMOS/TPMOS than by conventional TNMOS/TPMOS.

(a) (b) (c) 1.0 5 VDD -1 1.0 V 10 TCMOS Noise Margin FE-TCMOS 234 mV 0.7 V 4 0.5 V 10-2

)

V 3

(

-3

10 0.5

out 2 10-4 V 1 10-5

Switching Time (sec) Switching 0.0 0 1 2 3 4 5 6 7 0.0 0.5 1.0 1.0 0.7 0.5 Number of Stage V (V) IncreaseNM Percentage (%) in V (V) DD FigureFigure 6. ( 6.a )(a) The The switching switching time time comparison comparison between between TCMOS TCMOS and FE-TCMOS. and FE-TCMOS. The switching The switching speed diﬀspeederence difference between between them is them negligible. is negligible (b) The. (b butterﬂy) The butterfly curves curves of FE-TCMOS of FE-TCMOS with respectwith respect to VDD to . (c)V TheDD. ( comparisonc) The comparison of static of noise static margin noise margin between between FE-TCMOS FE-TCMOS and TCMOS. and TCMOS. The improvement The improvement of SNM inof FE-TCMOS SNM in FE is-TCMOS extracted is as extracted the increase as the in increase percentage, in percentage compared, tocompared TCMOS. to TCMOS.

4. Conclusions In this study, we investigated the ternary CMOS with the ferroelectric layer as a gate oxide. By utilizing the higher capacitance of the ferroelectric layer instead of the conventional high-k dielectric, the larger ION and the steeper SS were obtained, compared to conventional MOSFETs with high-k gate oxide, which leads to the more stable (larger SNM) ternary inverter operations at the lower VDD. It has the advantage of being completely compatible with existing processes [19]; moreover, through the switching speed comparison between TCMOS and CMOS, it is confirmed that the ferroelectric polarization switching is faster than the tunneling-based ternary inverter switching and thus the ferroelectric layer can play a role as a current booster in TCMOS.

Author Contributions: Conceptualization, K.L.; methodology, K.L.; validation, K.L.; formal analysis, K.L.; investigation, K.L.; resources, K.L and D.K.; writing—original draft preparation, K.L.; writing—review and editing, K.L., S.K., D.K., and B.-G.P; visualization, K.L.; supervision, D.K. and B.-G.P.

Funding: This research received no external funding.

Acknowledgments: This work was supported in part by The Brain Korea 21 Plus Project in 2020, in part by the Future Semiconductor Device Technology Development Program (10067739) funded by Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor Research Consortium (KSRC), and in part by Synopsys Inc.

Conflicts of Interest: The authors declare no conflict of interest.

References

4. Conclusions In this study, we investigated the ternary CMOS with the ferroelectric layer as a gate oxide. By utilizing the higher capacitance of the ferroelectric layer instead of the conventional high-k dielectric, the larger ION and the steeper SS were obtained, compared to conventional MOSFETs with high-k gate oxide, which leads to the more stable (larger SNM) ternary inverter operations at the lower VDD. It has the advantage of being completely compatible with existing processes [19]; moreover, through the switching speed comparison between TCMOS and CMOS, it is conﬁrmed that the ferroelectric polarization switching is faster than the tunneling-based ternary inverter switching and thus the ferroelectric layer can play a role as a current booster in TCMOS.

Author Contributions: Conceptualization, K.L.; methodology, K.L.; validation, K.L.; formal analysis, K.L.; investigation, K.L.; resources, K.L. and D.K.; writing—original draft preparation, K.L.; writing—review and editing, K.L., S.K., D.K. and B.-G.P.; visualization, K.L.; supervision, D.K. and B.-G.P. All authors have read and agreed to the published version of the manuscript. Funding: This research received no external funding. Acknowledgments: This work was supported in part by The Brain Korea 21 Plus Project in 2020, in part by the Future Semiconductor Device Technology Development Program (10067739) funded by Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor Research Consortium (KSRC), and in part by Synopsys Inc. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References

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