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Power device: Basics

Ichiro Omura Kyushu Institute of Japan

SinceIEEE EDS1909 Webinar Dec. 2, 2015

Ichiro Omura Kyushu Inst. Tech. Outline • Introduction – History – Power circuit • Power semiconductor devices – Power MOSFET / Super-junction MOSFET – IGBT – – Lateral devices • Future possibility • Related technology

Ichiro Omura Kyushu Inst. Tech. 1965 - "Moore's Law" Engine to drive ICT Gordon E. Moore

CMOS Manufacturing cost per cost Manufacturing component Number of components per

Integrated circuit patent in 1959

Robert Noyce To digital cost free => ICT for everybody Ichiro Omura Kyushu Inst. Tech. AC power distribution system

transm.web.fc2.com www.cz-toshiba.com

AC to AC Constant No active control function

Ichiro Omura Kyushu Inst. Tech. 100 years of power device development (High ) 1940 1960 1980 2000

Rotary converter arc /GTO IGBT (AC-DC) (AC-DC) (AC-DC/DC-AC) (AC-DC/DC-AC, MOS gate)

Electric Electronics R&D R&D Neutron doped FZ Carrier Injection Enhancement (Vacum Tubes) control Edge termination technology mm Chip Parallel operation Semiconductor Cosmic ray SEU Technology Thin wafer technology

Advanced LSI Tech. 0.1mm (CMOS, DRAM) Photos: Nippon inst. tech, Museum Nikkei 10-100um Tokyu Museum IGBT JR Kyushu Insulated Gate Nagahama Railway Museum Bipolar <1-10um Ichiro Omura Kyushu Inst. Tech. PWM: Pulse Width Modulation wave

PWM

Modulated signal to Power Semiconductor (ON/OFF) IGBT

AC Motor

PDS: Power Drive System 1. PWM signal control power switch (ON / OFF) 2. Motor current follows the modulation wave Ichiro Omura Kyushu Inst. Tech. Hybrid electric propulsion system Half-bridge ~500V Inverter for motor Inverter for generator

Battery

~200V IGBT Power Motor R Generator Total chip area for IGBT C S and power diode is more ICE 2 than 40 cm of silicon C wafer for Toyota Prius[*]. R to Wheels Z. Shen and I. Omura. Proceeding of the IEEE, Vol. 95 No. 4, 2007.(Figure) Ring gear *A. Kawahashi et al., Proc. of ISPSD 2004, pp. 23-29, 2004. Carrier/Planetary gear

Ichiro Omura Kyushu Inst. Tech. Sun gear Power Semiconductor Devices

Ichiro Omura Kyushu Inst. Tech. Power Semiconductor Devices Vertical device High LTT Opt- turn-on Bipolar gate MOS-gate

LTT 1GW IGBT GCT/GTO IGBT 1kW

GTO GCT Power

System Power MOSFET

Power MOS IGBT: Insulated Gate Bipolar Transistor GTO: Gate Turn-off Thyristor Low GCT: Gate Commutated Turn-off Thyristor LTT: Triggered Thyrisotor ( coupled)

Photos: • MOS gate devices cover wide-power range. Infineon • Toshiba Bipolar gate devices cover very high power applications(>10MW). ABB Ichiro Omura Kyushu Inst. Tech. TMEIC Types of power semiconductors(Switch)

Power MOSFET IGBT N-source N-source Source Gate Gate Emitter N P-base P-well P P MOS control MOS control + N- N-drift N-base N- + Unipolar Bipolar

P-emitter N-sub N+ P Collector Drain Thyristors (GTO,GCT) N-emitter Gate N P-base P IGBT: Insulated Gate Bipolar Transistor GTO: Gate Turn-off Thyristor Current control GCT: Gate Commutated Turn-off Thyristor N-base + Bipolar N-

P-emitter P 1. MOS-gate (voltage) control or bipolar gate (current) control 2. Unipolar conduction or bipolar conduction in high resistive (N-) Ichiro Omura Kyushu Inst. Tech. Remark: Vertical Device Structure

Cross section of active area Top view

Active area

Voltage Edge termination area Cell

Ichiro Omura Kyushu Inst. Tech. Power MOSFET

High LTT Opt- turn-on Bipolar gate MOS-gate

LTT 1GW IGBT GCT/GTO IGBT 1kW

GTO GCT Power System Power MOSFET Power MOS Low

Photos: Infineon Toshiba ABB Ichiro Omura Kyushu Inst. Tech. TMEIC Power MOSFET

N-source Source Gate

P-well Source Gate Current N-drift Drain

DC to DC Converter CPU=Load N-sub High Side MOSFET

Drain Imput Voltate CPU-chip

Sync. Rect. MOSFET De-coupling Output Capacitor Conduction carrier…… or Switching control ……. MOS-gate Switching Freq. ………. High Ichiro Omura Kyushu Inst. Tech. Function of N-drift layer n+ G S Function of N-drift layer: 1. Voltage blocking (higher ) n-drift 2. Current conduction (lower resistivity) p

Voltage Blocking Conduction D Source Source electron Ey Ey

Ldrift Charge neutrality

Ed Drain Drain Econd (VB) μ Blocking εstate (Poisson eq.) Conduction state (current eq.) dE E V qN = − y = ε ⋅ d J = q N E = qμ N cond D n n D cond n D L dy Ldrift drift

Ichiro Omura Kyushu Inst. Tech. μ n: Drift layer , length and drift layer resistance Ey Ichiro Omura Kyushu Inst. Tech. 5 1 ) X10 V/cm = × crit 3.0 VB Ecrit Ldrift E Ldrift 2 2.5 = ε ⋅ Ecrit qN D 2.0 y Ldrift Ecrit 1.5

Ecrit: critical E-field strength p 1.0 n-

2 Ecrit = ε ⋅ Ecrit 5.0 Drift layer doping N D 2qVB 0.0 1012 1013 1014 1015 Critical for Silicon ( N-drift Donor Concentration (/cm3) = 2VB Drift layer length Ldrift Ω Ecrit 1000m

Ω = μ Vcond 100m J n q n ND RON Ldrift 10mΩ

2 4V 1mΩ Drift layer resistance R = B [Ωcm2] drift μ ε 3 n Ecrit 0.1mΩ 10V 100V 1kV 10kV Low Voltage MOSFET (Vertical)

Source Gate Fig from Lecture Slide by N-source W. Saito, Toshiba P-well N-drift layer 1000 Si-limit 100 1997 ) 2

cm 2002

Ω 10 2007 2012 1

RonA (m Drain

0.1 10 100 1000 Breakdown voltage (V)

1. Cell size reduction for channel density 2. Trench gate for channel density and JFET resistance removal 3. Charge compensate (Vertical Field Plate) technology for drift resistance reduction.

Ichiro Omura Kyushu Inst. Tech. Super Junction MOSFET Fig from Lecture Slide by W. Saito, Toshiba DMOSFET 1000 Si-limit 100 1997 ) 2

cm 2002

Ω 10 2007 2012 1 SJ-MOSFET RonA (m

0.1 10 100 1000

) 25 Breakdown voltage (V) 2

cm g in Ω 20 p o d n

A(m m P/N column drift layer 15 lu on co r e Easy to deplete for high impurity concentration h 10 ig Low Ron + High Breakdown Voltage H 5

VB=700V

On-resistance R On-resistance 0 0 5 10 15 20 25 30 Charge compensate (Super Junction) technology P/N column pitch (μm) for drift resistance reduction.

Ichiro Omura Kyushu Inst. Tech. Column doping(ND) and Breakdown Voltage(VB)

1. Horizontal field for P/N column depletion Ex ε dE 2E = x = ε ⋅ hol Ehol qND dx Wcolumn

Source Ey Ex

VB Vertical field Ey W Wcolumn column Evert 3. A half area of drift layer contribute Drain = ⋅ VB Evert Ldrift current conduction 2.Vertical field for voltage blocking 1 between drain and source J = qμ N E n 2 n D cond Electric field in SuperJunction structure  high drift layer donor doping 1. Horizontal electric field for depletion of PN junction in narrow columns 2. Vertical electric field for sustainIchiro Omura blocking Kyushu Inst. voltage Tech. across drift layer Drift layer doping, length and drift layer resistance E 2Ehol ⇐ crit hol = ε ⋅ Ehol E Ecrit qND 2 2 Wcolumn E = ⋅ ⇐ crit |E|

= 1 = 1 μ Vcond J n q n ND Econd q n ND VB 2 2 Ldrift ⋅ Drift layer resistance 2VB Wcolomn W R = column Evert [Ωcm2] drift μ ε 2 n Ecrit Drain VB

Assumption: N-column and P-columnIchiro are Omura same Kyushu width Inst. Tech. IGBT Insulated Gate Bipolar Transistor High LTT Opt- turn-on Bipolar gate MOS-gate

LTT 1GW IGBT GCT/GTO IGBT 1kW

GTO GCT Power

System Power MOSFET

Power MOS Low

Photos: Infineon Toshiba ABB Ichiro Omura Kyushu Inst. Tech. TMEIC IGBT Shen, Omura, “Power Semiconductor Devices for Hybrid, Electric, and Fuel Cell ” Proc. Of the IEEE, Issue 4, 2007 Emitter 500 High Temp. Thin wafer NPT ) 2 Gate 300 Carrier enhancement effect

Non latch-up IGBT Protection 200 Collector Thermal management

Noise control Thin wafer PT 100 Trench gate Ic IPM NPT-IGBT Rated (A/cm 50 1985 1990 1995 2000 2005 2010 2015 Year 0.8V Vce 1. Bipolar Transistor + MOSFET (before IE-effect) 2. High current capability 3. ~0.8V collector-emitter threshold voltage for conduction 4. Medium switching speed (15kHz for , 100kHz for ICT

current supply and FPDIchiro driver Omura )Kyushu Inst. Tech. Operation mechanism of IGBT Conduction modulation in N-base

Ionized impurity (donor) positive negative = 2 pn ni d ε ⋅ E φ ≅ φ E ≅ 0 = q(N − n) ≅ 0 p n Unipolar dx D Electron E ≅ 0 Hole d ε ⋅ E ≅ = q(N + p − n) ≅ 0 E 0 dx D Conduction q φ ≅ ( −φ ) modulation E 0 = 2 kT p n pn ni e N << p,n << ≅ D ni p n PN-junction built-in N-source Gate Emitter potential IGBT P-base P Conduction modulation Ic 1. Both hole and electron contribute to current MOSFET N-base N N-base conduction 2. High stored carrier density in N-base (>1016cm-3) P-emitter P 3. Built-in voltage with the stored carrier 0.8V Vce Collector Ichiro Omura Kyushu Inst. Tech. Punch-through IGBT (PT-IGBT) Emitter Electric field at Stored Carrier N-source blocking state during on-state P-base

Epitaxial layer Gate with carrier N-base lifetime control

N-buffer P-emitter High minority carrier Low resistance (hole) injection efficiency P-type Substrate

1. Epi grown N-buffer (field stop) and short / lightly doped N-base 2. High minority (hole) carrier Collector injection from P-emitter 3. Low-conduction loss and large switching loss 4. Carrier lifetime control (high electron etc.) required Ichiro Omura Kyushu Inst. Tech. Non-Punch-through IGBT (NPT-IGBT) Electric Field at Stored Carrier Emitter blocking state N-source during on-state P-base

Gate

Neutron N-base transmutation doped wafer

Low minority carrier (hole) injection efficiency Shallow P-emitter Collector 1. NTD wafer without N-buffer 2. Low minority (hole) carrier injection from P-emitter Neutron transmutation doping 3. Higher-conduction loss and M. Tanenbaum and A. D. Mills J. Electrochem. Soc., vol. 108, pp.171 1961 lower switching loss J. Cornu and R. Sittig IEEE Trans. Electron Devices, vol. ED-22, pp.108 1975 4. No carrier lifetime control IAEA-TECDOC-1681, Neutron Transmutation Doping of Silicon at Research Reactors, required 2012 Ichiro Omura Kyushu Inst. Tech. Thin wafer IGBT technology Emitter Electric field at Stored Carrier N-source blocking state during on-state P-base

Gate NTD wafer etc. N-base

N-buffer Shallow P-emitter Collector PT NPT Thin-wafer-PT N-base length Short Long Short =FS-IGBT

P-emitter hole High Low Low injection Carrier lifetime Short Long Long in N-base Thin Wafer Technology -Reduction of turn-off tail current with short N-base -Reduction of conduction loss with short N-base Low Hole Injection P-emitter with long carrier lifetime -Reduction of turn-off tail current with low hole injection -Better thermal coefficient without carrier lifetime control Ichiro Omura Kyushu Inst. Tech. Problem in High Voltage IGBT Device Design Gate Emitter Stored Carrier during on-state

N-source P-base Electron current Hole current High conduction resistance for high voltage IGBT

N-base Carrier storage

Pemitter N-buffer

Collector

Ichiro Omura Kyushu Inst. Tech. Electron Injection Enhancement Effect

Gate Emitter Stored Carrier during on-state

N-source Electron P-base current

Hole current Carrier storage N-base

Kitagawa et al. “A 4500 V injection enhanced insulated gate bipolar transistor (IEGT) operating in a mode similar to a thyristor,” IEDM’93, 1993. Omura et al. “Carrier injection enhancement effect of high voltage MOS Pemitter devices-device and design concept,” ISPSD 97, pp. 217-220, 1997. N-buffer Omura, “High Voltage MOS Device Design: Injection Enhancement and Negative Gate Capacitance, (ETH thesis 2000), Series in Vol. 150, Hartung-Gorre Verlag, 2005. Collector Trench gate technology with special structure enhances majority carrier (electron) injection in N-base  Low conductionIchiro Omuraloss under Kyushu Inst.high Tech. current density Summary of IGBT Technology •Trench Gate –Conduction loss reduction with electron injection enhancement

–Channel resistance, JFET resistance reduction Gate

•Low Injection P-emitter + Long Carrier Lifetime N-base – Turn-off loss reduction with low hole storage in N-base – Better thermal coefficient without carrier lifetime control P-emitter •Thin Wafer Technology – Both conduction and turn-off loss reduction with with short N-base Ichiro Omura Kyushu Inst. Tech. Conduction and Breakdown Voltage Voltage blocking Conduction (flat carrier distribution is assumed) E-field Gate Emitter E-field

Ey Ey Floating P n p Charge neutrality

Hole Electron N-base current current

Pemitter N-buffer Collector ≅ = p n nstored

V V PN-junction built-in N-base length B ≥ ≥ B 2 Ln−base potential Ecrit Ecrit kT nstroed V − = 2 ln Stored Carrier built in q ni density nstored IGBT 1 ~ 2V Ic N-base conduction R = μ B MOSFET N −base + μ ⋅ ⋅ resistance q( n p ) nstored Ecrit Ichiro Omura Kyushu Inst. Tech. 0.8V Vce DMOSFET SJ-MOSFET IGBT . Gate Emitter

Floating P

Hole Electron Device Structure N-base current current Pemitter N-buffer

Collector

E 2 n Drift Layer Doping = ε ⋅ crit 2Ecrit stored N D N = ε ⋅ (Stored carrier density) D 16 -3 2qVB qWcolumn (>10 cm )

2VB = 2 VB 1 ~ 2VB Drift Layer Length Ldrif = = Ldrif Ln−base (N-base length) Ecrit Ecrit Ecrit Drift Layer Resistance 2 ⋅ 1 ~ 2V 4VB 2VB Wcolomn = B (N-base conduction R = R = RN −base μ drift μ ε 3 drift μ ε 2 q( + μ )⋅n ⋅ E resistance) n Ecrit n Ecrit n p stored crit

PN-junction = kT nstored none none Vbuilt−in 2 ln built-in potential q ni

600V class device 80-100 mΩcm2 <10 mΩcm2 ~1.5V at 200A/cm2

Assumption: N-column and P- (flat carrier stored carrier column are same width distribution is assumed

Omura et. al, International Workshop on PhysicsIchiro ofOmura Semiconductor Kyushu Inst. Devices, Tech. 2007. IWPSD 2007, pp. 781 – 786, 2007 DMOSFET SJ-MOSFET IGBT .

Gate Emitter

Floating P

Hole Electron Device Structure N-base current current

Pemitter N-buffer

Collector

RN −base ID ≅ ID V-I RON Rdrift Ic ≅ characteristics RON Rdrift Vbuilt−in VDS VDS Vce

Switching charge (turn-off charge)

Charge in main-junction PN-column depletion capacitance charge Stored carrier sweep out

Omura et. al, International Workshop on PhysicsIchiro ofOmura Semiconductor Kyushu Inst. Devices, Tech. 2007. IWPSD 2007, pp. 781 – 786, 2007 Types of Power Semiconductors

High LTT Opt- turn-on Bipolar gate MOS-gate

LTT 1GW IGBT GCT/GTO IGBT 1kW

GTO GCT Power

System Power MOSFET

Power MOS Low

Photos: Infineon Toshiba ABB Ichiro Omura Kyushu Inst. Tech. TMEIC Light Triggered Thyristor(LTT) P-emitter Photos: http://dbnst.nii.ac.jp/ N-emitter P-base Cathode Anode N-base

Stored carrier concentration under current conduction Impurity concentration

1.4GW system by Toshiba

1. PNPN structure 2. Light triggered turn-on 3. Cannot turn-off by gate Reverse 4. One wafer per one device Forward Conduction blocking blocking 5. Pressure contact package 6. Highest power per single semiconductor Trigger pulse

Ichiro Omura Kyushu Inst. Tech. GCT: Gate Commutated Turn-off Thyristor

Gate drive current 1. PNPN structure 2. One wafer per one device 3. > 100um cell size 4. Pressure contact package 5. Very low stray integrated for couple of kA gate current 6. Highest power per single semiconductor turn-off device

ABB GTO(GCT)

ABB 5.5kV, 5kA HPT IGCT ABB Integrated gate circuit

Ichiro Omura Kyushu Inst. Tech. Lateral Devices Control and Power = Power IC

Motor Driver

Emitter Collector Oxide

~1kV BOX Substrate

Toshiba Gate Source Drain Audio Speaker Driver P n+n-drift n+

<100V

Trypath datasheet

Ichiro Omura Kyushu Inst. Tech. RESURF principle for breakdown voltage design

Breakdown at vertical PN-junction Low dose N-drift Figure J. A. Appels High dose N-drift Source Drain et al. IEDM1979, pp. 238- 241, 1979 Source Drain Gate N+ N+ Gate N-drift Ey N+ N+ P N-drift N+ P- P P-

GND Breakdown voltage Electric Breakdown Breakdown GND field Ex Electric near N+ near P field Ex

Medium dose N-drift N-drift Dose Source Drain

Gate Ey N-drift 2 P N+ N-drift dose (atm/cm ) is the key parameter P- for breakdown voltage design (~1e12/cm2)

GND Electric field Ex Ichiro Omura Kyushu Inst. Tech. Lateral “Super Junction” MOSFET

X2 amount of Source Drain conduction carriers Gate Oxide Gate Oxide P-buried P-buried P-buried N P-substrate N

P-substrate D. Disney et al. A new 600V lateral PMOS device with a buried conduction layer, pp.41-44, ISPSD’ 03 SOI IGBT N Emitter base Ey Oxide

BOX Substrate

GND Ichiro Omura Kyushu Inst. Tech. Future Power ICs

Power IC VBK in ISPSD papers Future HV Power IC will be …

Digital Rich Power IC

DIP IPM H Transmissions ig High power motor h 10000 P drives o High power w / e P r SOI single chip inverter Industrial Drives P M I o EV/HEV s d IP u T M le s 1000 ra w Appliances d n I it ) s n h ) e HEV IPM v fe s c V i r u e out c l Kilowatt

( e m at r Industrial IPM V am P s / o o , o o l r in d i 100 w n P ed c V e o ( r P w I C p C B e o s r w On board

Max S Voltage o iP e Power IC n r P Vicor VIChip C 10 B CPU Power Supply P (POL) o Mobile Power Supply w e r Single chip power supply S o 1 C 0.1 1 10 100 1000 Current(A) Omura, ECPE workshop Jan. 2012 Max(Iin, Iout) Ichiro Omura Kyushu Inst. Tech. Omura, CIPS 2010 Future Possibility

Ichiro Omura Kyushu Inst. Tech. Advanced power devices Road map

Wide band-gap semiconductor Platform (SiC::2010 ~、GaN::2015 ~ FET/ BJT/PiN/Field Diamond::2025~) emitter Hybrid pair platform of Si-switching SiC device and SiC diode (2013~2035) SiC IGBT/PiN MOS/SIT/SBD Silicon platform (~2030) GaN HEMT/MOS/SBD GaAs-FET Si-IGBT Power SiC-SBD, SiC-PiN IntegratedPower Si-MOS(SJ) Integrated Circuit area SiC-SBD Circuit area Silicon IGBT, Thyristor/PiN Silicon CMOS, MOSFET (SJ)/SBD, PiN Blocking voltage [v] 1 10 100 1k 10k H. Ohashi et al. “Role of Simulation Technology for the Progress in Power Devices and Their Applications,” IEEE Ichiro Omura Kyushu Inst. Tech. T-ED, Vol. 60, issue 2, 2013. Future possibility

• 1) Si-power devices still have much room for development toward ultimate and IGBTs. • 2) The combination of Si-switching devices and SiC freewheeling will be a significant step not only for strengthening the SiC market but also for Si- device development. • 3) Si-IGBT will be replaced by SiC MOSFET in the voltage range of more than 1000 V in some applications, and SiC-IGBT has the potential to be used for applications of more than 10 kV. (Si-IGBT for volume market, SiC for high end market) • 4) GaN power devices will replace some of Si-power ICs and will be used for faster switching applications. • 5) The unique properties of diamond have potential for new power devices particularly in high-voltage applications. • 6) The ultimate CMOS has the potential to be used for power integrated devices in ICT applications. H Ohashi, I Omura - IEEE transactions on electron devices, 2013 Ichiro Omura Kyushu Inst. Tech. Related Technology

Ichiro Omura Kyushu Inst. Tech. Examples of High Power IGBT Package

42 Chips

125mm 15mm

Ichiro Omura Kyushu Inst. Tech. Shen, Omura, “Power Semiconductor Devices for Hybrid, Electric, and Fuel Cell Vehicles” Proc. Of the IEEE, Issue 4, 2007 Wafer technology(Silicon) Productivity 300mm, CZ, MCZ Large Market, Short time to market 1200V IGBT 1200V PiN diode Low voltage commodity Material (wafer) engineering will share the major part of total power device design,Low fabrication voltage high and spec PE application High voltage power MOS 6500V PiN diode

6500V IGBT Thyrisotrs Special Power Devices Quality Functionality Smaller Market, Long term Integration, Game change Long carrier lifetime Epi, SOI, SJ-structure etc Ichiro Omura Kyushu Inst. Tech. 150-200mm FZ (Pre-structured wafer) and micro electronics forming Cyber-Physical System Generating High speed Actuating Service Lighting Cloud Heating Cooling Energy Digital SNS Networking E-Storage network network IoT, Industrie 4.0 Power- Micro- electronics Power Software, electronics Clustering Circuit, Sensing, Protocol Legacy Micro- Legacy Power- Control Electronics Electronics LSI, Power Integrating Adv. CMOS Semi. Integration Hardware  Electron devices are the key technology for future energy networking  New phase of electronics has started with close link between power and micro electronics for future sustainable society I. Omura, SIIQ report, Oct. 2012, in Japanese Ichiro Omura Kyushu Inst. Tech. See also

Z. John Shen, Ichiro Omura Article Power Semiconductor Devices for Hybrid, Electric, and Fuel Cell Vehicles Proceedings of the IEEE 05/2007; 95(4-95):778 - 789.

H. Ohashi and I. Omura “Role of Simulation Technology for the Progress in Power Devices and Their Applications,” IEEE T-ED, Vol. 60, issue 2, 2013.

Ichiro Omura Kyushu Inst. Tech.