Power semiconductor device: Basics Ichiro Omura Kyushu Institute of Technology Japan SinceIEEE EDS1909 Webinar Dec. 2, 2015 Ichiro Omura Kyushu Inst. Tech. Outline • Introduction – History – Power electronics circuit • Power semiconductor devices – Power MOSFET / Super-junction MOSFET – IGBT – Thyristors – Lateral devices • Future possibility • Related technology Ichiro Omura Kyushu Inst. Tech. 1965 - "Moore's Law" Silicon Engine to drive ICT Gordon E. Moore CMOS Manufacturing cost per cost Manufacturing component Number of components per integrated circuit Integrated circuit patent in 1959 Robert Noyce To digital cost free => ICT for everybody Ichiro Omura Kyushu Inst. Tech. AC power distribution system transm.web.fc2.com www.cz-toshiba.com AC to AC Constant frequency No active control function Ichiro Omura Kyushu Inst. Tech. 100 years of power device development (High voltage) 1940 1960 1980 2000 Rotary converter Mercury arc rectifier Thyristor/GTO IGBT (AC-DC) (AC-DC) (AC-DC/DC-AC) (AC-DC/DC-AC, MOS gate) Electric Machine Electronics R&D R&D Neutron doped FZ wafer Carrier Injection Enhancement (Vacum Tubes) Carrier lifetime control Edge termination technology mm Chip Parallel operation Semiconductor Cosmic ray SEU Technology Thin wafer technology Advanced LSI Tech. 0.1mm (CMOS, DRAM) Photos: Nippon inst. tech, Museum Nikkei 10-100um Tokyu Museum IGBT JR Kyushu Insulated Gate Nagahama Railway Museum Bipolar Transistor Toshiba <1-10um Ichiro Omura Kyushu Inst. Tech. PWM: Pulse Width Modulation Modulation wave Carrier wave PWM Modulated signal to Power Semiconductor switch (ON/OFF) IGBT AC Motor PDS: Power Drive System 1. PWM signal control power semiconductors switch (ON / OFF) 2. Motor current follows the modulation wave Ichiro Omura Kyushu Inst. Tech. Hybrid electric vehicle propulsion system Half-bridge boost converter ~500V Inverter for motor Inverter for generator Battery ~200V IGBT Power Diode Motor R Generator Total chip area for IGBT C S and power diode is more ICE 2 than 40 cm of silicon C wafer for Toyota Prius[*]. R to Wheels Z. Shen and I. Omura. Proceeding of the IEEE, Vol. 95 No. 4, 2007.(Figure) Ring gear *A. Kawahashi et al., Proc. of ISPSD 2004, pp. 23-29, 2004. Carrier/Planetary gear Ichiro Omura Kyushu Inst. Tech. Sun gear Power Semiconductor Devices Ichiro Omura Kyushu Inst. Tech. Power Semiconductor Devices Vertical device High LTT Opt- turn-on Bipolar gate MOS-gate LTT 1GW IGBT GCT/GTO IGBT 1kW GTO GCT Power System Power MOSFET Power MOS IGBT: Insulated Gate Bipolar Transistor GTO: Gate Turn-off Thyristor Low GCT: Gate Commutated Turn-off Thyristor LTT: Light Triggered Thyrisotor (optical fiber coupled) Photos: • MOS gate devices cover wide-power range. Infineon • Toshiba Bipolar gate devices cover very high power applications(>10MW). ABB Ichiro Omura Kyushu Inst. Tech. TMEIC Types of power semiconductors(Switch) Power MOSFET IGBT N-source N-source Source Gate Gate Emitter N P-base P-well P P MOS control MOS control + N- N-drift N-base N- + Unipolar Bipolar P-emitter N-sub N+ P Collector Drain Thyristors (GTO,GCT) Cathode N-emitter Gate N P-base P IGBT: Insulated Gate Bipolar Transistor GTO: Gate Turn-off Thyristor Current control GCT: Gate Commutated Turn-off Thyristor N-base + Bipolar N- P-emitter P Anode 1. MOS-gate (voltage) control or bipolar gate (current) control 2. Unipolar conduction or bipolar conduction in high resistive layer(N-) Ichiro Omura Kyushu Inst. Tech. Remark: Vertical Device Structure Cross section of active area Top view Active area Electric Current Voltage Edge termination area Cell Ichiro Omura Kyushu Inst. Tech. Power MOSFET High LTT Opt- turn-on Bipolar gate MOS-gate LTT 1GW IGBT GCT/GTO IGBT 1kW GTO GCT Power System Power MOSFET Power MOS Low Photos: Infineon Toshiba ABB Ichiro Omura Kyushu Inst. Tech. TMEIC Power MOSFET N-source Source Gate P-well Source Gate Current N-drift Drain DC to DC Converter CPU=Load N-sub High Side MOSFET Drain Inductor Imput Voltate CPU-chip Sync. Rect. MOSFET De-coupling Capacitor Output Capacitor Conduction carrier…… Electron or hole Switching control ……. MOS-gate Switching Freq. ………. High Ichiro Omura Kyushu Inst. Tech. Function of N-drift layer n+ G S Function of N-drift layer: 1. Voltage blocking (higher breakdown voltage) n-drift 2. Current conduction (lower resistivity) p Voltage Blocking Conduction D Source Source electron donor Ey Ey Ldrift Charge neutrality Ed Drain Drain Econd (VB) Blocking state (Poisson eq.) Conduction state (current eq.) dE E V qN = −ε y = ε ⋅ d J = qμ N E = qμ N cond D n n D cond n D L dy Ldrift drift Ichiro Omura Kyushu Inst. Tech. μ n: electron mobility Drift layer doping, length and drift layer resistance Ey Ichiro Omura Kyushu Inst. Tech. 5 1 ) X10 V/cm = × crit 3.0 VB Ecrit Ldrift E Ldrift 2 2.5 = ε ⋅ Ecrit qN D 2.0 y Ldrift Ecrit 1.5 Ecrit: critical E-field strength ｐ 1.0 ｎ- 2 Ecrit = ε ⋅ Ecrit 5.0 Drift layer doping N D 2qVB 0.0 1012 1013 1014 1015 Critical Electric Field for Silicon ( N-drift Donor Concentration (/cm3) = 2VB Drift layer length Ldrift Ω Ecrit 1000m Ω = μ Vcond 100m J n q n ND RON Ldrift 10mΩ 2 4V 1mΩ Drift layer resistance R = B [Ωcm2] drift μ ε 3 n Ecrit 0.1mΩ 10V 100V 1kV 10kV Low Voltage MOSFET (Vertical) Source Gate Fig from Lecture Slide by N-source W. Saito, Toshiba P-well N-drift layer 1000 Si-limit 100 1997 ） 2 cm 2002 Ω 10 2007 2012 1 RonA (m Drain 0.1 10 100 1000 Breakdown voltage (V) 1. Cell size reduction for channel density 2. Trench gate for channel density and JFET resistance removal 3. Charge compensate (Vertical Field Plate) technology for drift resistance reduction. Ichiro Omura Kyushu Inst. Tech. Super Junction MOSFET Fig from Lecture Slide by W. Saito, Toshiba DMOSFET 1000 Si-limit 100 1997 ） 2 cm 2002 Ω 10 2007 2012 1 SJ-MOSFET RonA (m 0.1 10 100 1000 ) 25 Breakdown voltage (V) 2 cm g in Ω 20 p o d n A(m m P/N column drift layer 15 lu on co r e Easy to deplete for high impurity concentration h 10 ig Low Ron + High Breakdown Voltage H 5 VB=700V On-resistance R On-resistance 0 0 5 10 15 20 25 30 Charge compensate (Super Junction) technology P/N column pitch (μm) for drift resistance reduction. Ichiro Omura Kyushu Inst. Tech. Column doping(ND) and Breakdown Voltage(VB) 1. Horizontal field for P/N column depletion Ex dE 2E = ε x = ε ⋅ hol Ehol qND dx Wcolumn Source Ey Ex VB Vertical field Ey W Wcolumn column Evert 3. A half area of drift layer contribute Drain = ⋅ VB Evert Ldrift current conduction 2.Vertical field for voltage blocking 1 between drain and source J = qμ N E n 2 n D cond Electric field in SuperJunction structure high drift layer donor doping 1. Horizontal electric field for depletion of PN junction in narrow columns 2. Vertical electric field for sustainIchiro Omura blocking Kyushu Inst. voltage Tech. across drift layer Drift layer doping, length and drift layer resistance E 2Ehol ⇐ crit hol = ε ⋅ Ehol E Ecrit qND 2 2 Wcolumn E = ⋅ ⇐ crit |E|<Ecrit VB Evert Ldrift Evert Ecrit 2 2 Evert 2E Drift N-column = ε ⋅ crit Ex N D Horizontal field doping qWcolumn Ehol 2 V Drift layer length = B Ldrif Ecrit source Ey = 1 μ = 1 μ Vcond J n q n ND Econd q n ND VB 2 2 Ldrift ⋅ Drift layer resistance 2VB Wcolomn W R = column Evert [Ωcm2] drift μ ε 2 n Ecrit Drain VB Assumption: N-column and P-columnIchiro are Omura same Kyushu width Inst. Tech. IGBT Insulated Gate Bipolar Transistor High LTT Opt- turn-on Bipolar gate MOS-gate LTT 1GW IGBT GCT/GTO IGBT 1kW GTO GCT Power System Power MOSFET Power MOS Low Photos: Infineon Toshiba ABB Ichiro Omura Kyushu Inst. Tech. TMEIC IGBT Shen, Omura, “Power Semiconductor Devices for Hybrid, Electric, and Fuel Cell Vehicles” Proc. Of the IEEE, Issue 4, 2007 Emitter 500 High Temp. Thin wafer NPT ) 2 Gate 300 Carrier enhancement effect Non latch-up IGBT Protection 200 Collector Thermal management Noise control Thin wafer PT 100 Trench gate Ic IPM NPT-IGBT Rated Current Density(A/cm 50 1985 1990 1995 2000 2005 2010 2015 Year 0.8V Vce 1. Bipolar Transistor + MOSFET (before IE-effect) 2. High current capability 3. ~0.8V collector-emitter threshold voltage for conduction 4. Medium switching speed (15kHz for motor drive, 100kHz for ICT current supply and FPDIchiro driver Omura )Kyushu Inst. Tech. Operation mechanism of IGBT Conduction modulation in N-base Ionized impurity (donor) positive negative = 2 pn ni d ε ⋅ E φ ≅ φ E ≅ 0 = q(N − n) ≅ 0 p n Unipolar dx D Electron E ≅ 0 Hole d ε ⋅ E ≅ = q(N + p − n) ≅ 0 E 0 dx D Conduction q ≅ (φ −φ ) modulation E 0 = 2 kT p n pn ni e N << p,n << ≅ D ni p n PN-junction built-in N-source Gate Emitter potential IGBT P-base P Conduction modulation Ic 1. Both hole and electron contribute to current MOSFET N-base N N-base conduction 2. High stored carrier density in N-base (>1016cm-3) P-emitter P 3. Built-in voltage with the stored carrier 0.8V Vce Collector Ichiro Omura Kyushu Inst. Tech. Punch-through IGBT (PT-IGBT) Emitter Electric field at Stored Carrier N-source blocking state during on-state P-base Epitaxial layer Gate with carrier N-base lifetime control N-buffer P-emitter High minority carrier Low resistance (hole) injection efficiency P-type Substrate 1.