High Power Bipolar Junction Transistors in Silicon Carbide

Home , Breakdown voltage, Donor (semiconductors), Gain (electronics), Semiconductor device

KTH Information and Commcon Technology

Hyung-Seok Lee

Licentiate Thesis

Laboratory of Solid State Devices (SSD), Department of Microelectronics and Information Technology (IMIT), Royal Institute of Technology (KTH)

Stockholm, Sweden

High Power Bipolar Junction Transistors in Silicon Carbide

A dissertation submitted to the Royal Institute of Technology, Stockholm, Sweden, in partial fulfillment of the requirements for the degree of Teknologie Licentiat.

Hyung-Seok Lee : High Power Bipolar Junction Transistors in Silicon Carbide ISRN KTH/EKT/FR-2005/6-SE, KTH Royal Institute of Technology, Department of Microelectronics and Information Technology (IMIT), Laboratory of Solid State Devices (SSD), Stockholm 2005.

Abstract

As a power device material, SiC has gained remarkable attention to its high thermal conductivity and high breakdown electric field. SiC bipolar junction transistors (BJTs) are interesting for applications as power switch for 600 V-1200 V applications. The SiC BJT has potential for very low specific on-resistances and this together with high temperature operation makes it very suitable for applications with high power densities. One disadvantage of the BJT compared with MOSFETs and Insulated Gate Bipolar Transistors (IGBTs) is that the BJT requires a more complex drive circuit with higher power capability. For the SiC BJT to become competitive with field effect transistors, it is important to achieve high current gains to reduce the power required by the drive circuit. Although much progress in SiC BJTs has been made, SiC BJTs still have low common emitter current gain typically in the range 10-50. In this work, a record high current gain exceeding 60 has been demonstrated for a SiC BJT with a breakdown voltage of 1100 V. This result is attributed to an optimized device design, a stable device process and state-of-the-art epitaxial base and emitter layers.

A new technique to fabricate the extrinsic base using epitaxial regrowth of the extrinsic base layer was proposed. This technique allows fabrication of the highly doped region of the extrinsic base a few hundred nanometers from the intrinsic region. An important factor that made removal of the regrowth difficult was that epitaxial growth of very highly doped layers has a faster lateral than vertical growth rate and the thickness of the p+ layer therefore has a maximum close to the base-emitter side- wall. A remaining p+ regrowth spacer at the edge of the base-emitter junction is proposed to explain the low current gain. Under high power operation, the SiC BJTs were strongly influenced by self-heating, which significantly limits the performance of device. The DC I-V characteristics of 4H-SiC BJTs have also been studied in the temperature range 25 °C to 300 °C. The DC current gain at 300 °C decreased 56 % compared to its value at 25 °C. Self- heating effects were quantified by extracting the junction temperature from DC measurements. To form good ohmic contacts to both n-type and p-type SiC using the same metal is one important challenge for simplifying SiC Bipolar Junction Transistor (BJT) fabrication. Ohmic contact formation in the SiC BJT process was investigated using sputter deposition of titanium tungsten to both n-type and p-type followed by annealing at 950 oC. The contacts were characterized with linear transmission line method (LTLM) structures. The n+ emitter structure and the p+ base structure contact resistivity after 30 min annealing was 1.4 x 10-4 Ωcm2 and 3.7 x 10-4 Ωcm2, respectively. Results from high-resolution transmission electron microscopy (HRTEM), suggest that diffusion of Si and C atoms into the TiW layer and a reaction at the interface forming (Ti,W)C1-x are key factors for formation of ohmic contacts.

Keywords: Silicon Carbide (SiC), Power device, Bipolar Junction Transistor, TiW, Ohmic contact, Current gain β

Table of Contents

List of appended papers...... iii Summary of Appended Papers ...... v Acknowledgements...... vi List of Symbols & Acronyms...... vii 1. Introduction ...... 1 2. Background...... 3 2.1 Crystal structures and polytypes ...... 3 2.2 Electrical properties ...... 4 2.2.1 Wide bandgap...... 4 2.2.2 High breakdown electric field ...... 5 2.2.3 High thermal conductivity ...... 7 2.3 Electrical Models of SiC...... 7 2.3.1 Mobility Model ...... 7 2.3.2 Intrinsic carrier concentration and Energy band gap...... 8 2.3.3 Incomplete Ionization ...... 9 2.3.4 Recombination...... 9 2.3.5 Bandgap narrowing...... 10 2.4 The basic principle of BJT operation...... 10 2.4.1 Current gain ...... 11 2.4.2 Breakdown voltage ...... 12 3. Fabrication of SiC Bipolar Transistors...... 13 3.1 Review of design and processing issues for SiC BJTs ...... 13 3.2 Bulk and epitaxial growth...... 15 3.3 Etching of SiC...... 16 3.4 Ion implantation...... 18 3.5 Oxidation and oxide deposition ...... 20 3.6 Metallization ...... 21 3.7 Layout and fabrication process for SiC BJTs ...... 22 4. Characterization and Results...... 27 4.1 SiC Power BJT Results...... 27 4.1.1 BJTs with an epitaxially regrown extrinsic base layer...... 27 4.1.2 Continuous growth run of epitaxial layers BJTs...... 29 4.1.3 Wafer map of SiC BJTs...... 30 4.2 Material characterization ...... 33 4.2.1 X-ray diffraction (XRD)...... 33 4.2.2 Transmission Electron Microscope (TEM) ...... 35 4.2.3 Secondary Ion Mass Spectrometry (SIMS)...... 37 4.3 Electrical characterization...... 37 4.3.1 Extraction of junction temperature...... 37 4.3.2 Linear transmission line model (LTLM)...... 39

5. Summary and Future work...... 41 Bibliography...... 43 Appended Papers……………………………………………………………...45

List of appended papers

I. Electrical Characteristics of 4H-SiC BJTs at Elevated Temperatures H-S. Lee, M. Domeij, E. Danielsson, C-M. Zetterling and M. Östling Materials Science Forum vol. 483-485, pp. 897-900, 2005

II. Geometrical effects in high current gain 1100 V 4H-SiC BJTs M. Domeij, H-S. Lee, C-M. Zetterling, M. Östling, A. Schöner IEEE Electron Device Letters, vol. 26, n 10, pp. 743-745, 2005

III. Investigation of TiW contacts to 4H-SiC Bipolar Junction Devices H-S. Lee, M. Domeij, C-M. Zetterling, M. Östling To be published in Materials Science Forum

IV. A 4H-SiC BJT with an Epitaxially Regrown Extrinsic Base Layer E. Danielsson, M. Domeij, H-S. Lee, C-M. Zetterling, M. Östling, A. Schöner and C. Hallin Materials Science Forum vol. 483-485, pp. 905-908, 2005

Related work not included in the thesis

1. Simulation study of 4H-SiC Junction-gated MOSFETs from 300 K to 773 K H-S. Lee, S-M. Koo, C-M. Zetterling, E. Danielsson, M. Domeij, and M. Östling Materials Science Forum vol. 457-460, pp. 1437-1440, 2004

2. Current Gain of 4H-SiC Bipolar Transistors Including the Effect of Interface States M. Domeij, E. Danielsson, H-S. Lee, C-M. Zetterling and M. Östling Materials Science Forum vol. 483-485, pp. 889-892, 2005

3. SiC power bipolar junction transistors-Modeling and improvement of the current gain M. Domeij, H-S. Lee, C-M. Zetterling, M. Östling, A. Schöner Proceedings of the 11th European conference on Power electronics and applications (EPE), Dresden, Germany 11th-14th September 2005

4. SiC JMOSFETs for High-Temperature Stable Circuit Operation S.-M. Koo, C.-M. Zetterling, H.-S. Lee, and M. Östling Materials Science Forum vol. 457-460 pp. 1445-1450, 2004

5. Combination of JFET and MOSFET devices in 4H-SiC for high-temperature stable circuit operation S-M. Koo, C-M. Zetterling. H-S. Lee and M. Östling Electronics Letters, vol. 39, n 12, pp. 933-935, 2003

iii

6. Challenges for high temperature silicon carbide electronics electronics S.-M. Koo, E. Danielsson, .W. Liu, S-K. Lee. M. Domeij,.H-S. Lee, M. Östling, Mater. Res. Soc. Symposium Proceedings vol. 764, pp. 15-25, 2003

Summary of Appended Papers

Paper I. This paper presents high temperature characteristics of SiC BJTs. Electrical DC measurements with 4H-SiC BJTs were compared with pulsed measurements. Self-heating effects were quantified by extracting the junction temperature from DC measurements. The DC measurements and writing the paper were done by the author in cooperation with the co- authors.

Paper II. The highest current gain of SiC BJTs that have been reported till now was presented. A significant influence of surface recombination on the current gain has been examined with different emitter finger widths. The critical distance between implantation and emitter edge was analyzed by measurements. The author performed all device processing and contributed with electrical measurements and characterization.

Paper III. In this paper, the ohmic contact formation in SiC BJTs with TiW contacts has been studied. We found that diffusion of Si and C atoms into the TiW layer and a reaction at the interface forming titanium tungsten carbides are key factors for formation of ohmic contacts. The author performed all processing steps and writing and characterization.

Paper IV. SiC BJTs were fabricated using epitaxial regrowth to form a highly doped extrinsic base layer for a good base ohmic contact. A remaining regrowth spacer at the edge of the base-emitter junction was proposed to explain a low current gain. The author contributed with device processing and DC measurement.

Acknowledgements

First of all, I would especially like to thank my supervisors, Prof. Carl-Mikael Zetterling, Prof. Mikael Östling, and Dr. Martin Domeij. They have given me an opportunity to pursue this research and they have guided me during my studies. My principle supervisor Carl- Mikael has taught me valuable lessons in doing research. His talent, excellent intuition power, and broad interests have encouraging and motivated me. I am deeply grateful to Mikael, head of the department and dean of the school of ICT, for providing invaluable support and continuous guidance with his energetic intellectual energy. Martin has provided many wonderful discussions and fruitful advice both scientifically and personally. He also has given me several chances to visit conferences and to meet specialists of this research area. Without their help, this Thesis would not have been what it is now.

I am very grateful to Dr. Erik Danielsson for teaching me processing in the clean-room and computer simulation. Special thanks goes also to my Korea University senior Dr. Sang-Mo Koo. He helped me to accommodate to the new surroundings in Sweden and also shared his research experience in a kind manner. I sincerely wish for you to get a good position in Korea. I am grateful to Prof. Byung-Moo Moon in Korea University for his great advice and consideration. I would like to Zandra Lundbeg for her warm kindness and for helping out.

I am grateful to Timo Söderquist for helping me clean-room equipments and a korean greeting whenever he meets me with his smile. I would also like to thank Dr. Gunnar Malm for kind answers about research as well as social issues in Sweden. I am grateful to Dr. Per- Erik Hellström for processing advice. Thanks goes also to Christian Ridder for his detailed help in managing of the stepper photolithography. Special thanks goes to all my colleagues: Erdal, Sanna, Uwe, Johan, Ann-Chatrin, Christian, Yongbin, Stefan, Dongping, Sten, Wei, Patrik, Martin, Shili, Julius, Zhibin, Zhen.

I would like to thank all the members of the Korean students and researchers association (KOSAS) in Sweden. I am especially grateful to Dr. Sang-Ho Yun at MSP for his great support and advice. His attitude as a scientist always kept me going. Thanks is also given to Jang-Young Kim and Joo-Hyung Kim at KMF.

I sincerely wish to thank all members of my family for their encouragement and support. Especially, I wish to express my deepest gratitude to my parents who always have believed in me and for their love and support. Finally, I want to thank my wife Soo-Youn and my daughter Yoon-Seo, to whom this Thesis is dedicated.

Stockholm, November 2005

Hyung-Seok Lee

List of Symbols & Acronyms

BVCEO Common emitter breakdown voltage BVCBO Common base breakdown voltage DB Base minority carrier diffusion coefficients DE Emitter minority carrier diffusion coefficients E Electric field EC Critical electric field

Eg Bandgap gc Donor level degeneracy factor gv Acceptor level degeneracy factor IB Base current IC Collector current IE Emitter current LT Transfer length

NB Base doping concentration NC Effective conduction band density of state Nd Donor concentration + Nd Ionized donor concentration

NE Emitter doping concentration

NV Effective valence band density of state n Electron concentration ni Intrinsic carrier concentration p Hole concentration Pdiss Dissipated power q Electron charage RSRH Shockley-Read-Hall recombination rate RAuger Auger recombination rate RC Contact resistance RT Total resistance RTh Thermal impedance Tamb Ambient temperature Tj Junction temperature VB Breakdown voltage VCE Collector-emitter voltage WE Emitter region width WB Base region width α Common-base current gain αT Base transfort factor β Common-emitter current gain γ Emitter injection efficiency ρ Resistivity ρc Specific contact resistance ρs Sheet resistance τ Lifetime τn Electron lifetime τn Hole lifetime Al Aluminium

vii

AFM Atomic force Microscopy B Boron BJT Bipolar Junction Transistor CVD Chemical Vapor Deposition C Carbon EDS Energy Dispersive X-Ray Spectrometry FET Field Effect Transistor HRXRD High-Resolution X-Ray Diffraction ICP Inductively coupled Plasma IGBT Insulated Gate Bipolar Transistor I-V Current-Voltage measurement JBS Junction Barrier Schottky JTE Junction Termination Extension LPE Liquid Phase Epitaxy MBE Molecular Beam Epitaxy MOS Metal Oxide Semiconductor MOSFET Metal Oxide Semiconductor Field Effect Transistor PECVD Plasma Enhanced Chemical Vapor Deposition RF Radio Frequency RIE Reactive Ion Etching RTA Rapid Thermal Annealing SAED Selected Area Electron Diffraction Si Silicon SiC Silicon Carbide SIMS Secondary Ion Mass Spectrometry TEM Transmission Electron Microscopy TiW Titanium Tungsten TLM Transmission Line Model XRD X-Ray Diffraction

viii

Chapter 1

Introduction

Information Technology (IT) has brought about a remarkable change of modern society. We can meet the benefits of this revolution in everyday life. The words, such as cyberspace, wireless, mobile phone, digital camera, and hybrid-car are not strange any more. The development of semiconductor devices has become a major force in this revolution which has led to remarkable change of society.

During the last two decades, silicon (Si) has been the dominant material in semiconductor device technology, due to well controlled and mature process technology. Si is still dominating the field of power devices. Silicon Insulated Gate Bipolar transistors (IGBTs) and power MOSFETs are widely used and dominate the market for power switches. However, the power transistors for 600 V and above based on Si have either a relatively high specific on- resistance, as the MOSFET, or significant switching power losses as the IGBT, both resulting in high power dissipation. In addition, the maximum allowed operating temperature of Si power devices is typically 150-175 °C, so the design margins to avoid overheating are relatively small. In recent years, the need of a new material for power devices have been stressed because of the limitation of Si material properties and the increasing power densities of power electronic systems. Silicon carbide (SiC) has gained remarkable attention as the most mature of the wide band gap materials with the potential of replacing Si in power devices due to its electrical and physical properties. SiC has the advantage of high thermal conductivity, high breakdown electric field, and saturated carrier velocity compared to other semiconductor materials, which makes it an ideal material for power devices [1]. In addition, SiC can today be fabricated with high material quality compared to other wide bandgap materials and 4 inch wafers were recently introduced on the market. Remarkable progress has been made in SiC power devices in recent years. Many high power SiC devices, such as diodes, transistors and thyristors, have been demonstrated and SiC Schottky diodes for 600 V and 1200 V are now commercially available [2].

High power switching is one of the important applications, which can use advantages of SiC. The SiC Bipolar Junction Transistor (BJT) is a promising high power switching device due to

1 H.-S. LEE Chapter 1. Introduction

its low specific on-resistance [3-5]. Although SiC BJTs are also very favorable at high temperatures (over 150 ºC), at which MOSFETs suffer from poor oxide reliability, the low current gain is one of the main challenging issues for SiC BJTs. The improvement of the current gain of SiC BJTs is complex since it depends on several parameters such as the thicknesses and doping levels of the base and emitter layers, the material quality and the surface passivation.

The topic of this thesis is the fabrication and electrical characterization of 4H-SiC BJTs, designed to be used as power switches. The aim of this thesis is to improve the current gain and breakdown voltage and to optimize the processing for SiC power BJTs. This thesis consists of 5 chapters including this introduction. Chapter 2 presents the material and electrical properties of SiC and makes a comparison with other materials. Chapter 3 describes process technology development for SiC. The different fabricated devices and electrical characterization including the important characteristics of power BJTs are discussed in chapter 4. Finally, a short summary and a future outlook is given in chapter 5.

Chapter 2

Background

SiC is a semiconductor material exhibiting some important superior characteristics compared with Si or other semiconductors. The wide band gap, the high critical field, the high thermal conductivity are main advantages, which make it an excellent material for high power, high temperature, and high frequency device applications. In this chapter, the basic material properties and advantages of SiC are described.

2.1 Crystal structures and polytypes

SiC consists of Si and C atoms, which are both group IV element materials. Each Si atom shares electrons with four C atoms, which means that each atom is bonded covalently to four neighbors, and vice versa. The basic structural unit is shown in Fig. 2.1. The approximate bond length between Si and C atoms is 1.89 Å and the length between Si-Si or C-C atoms is 3.08 Å.

1.89 Å

3.08 Å

Fig. 2.1. The basic structural unit in SiC [7].

3 H.-S. LEE Chapter 2. Background

C A

C A C

B B B

A A A

3C 4H 6H Fig. 2.2. Some common crystal polytypes, 3C, 4H and 6H polytype stacks [7].

SiC has a characteristic, which is known as a polytypism. It means that the material can possess more than one crystal structure. Each crystal structure is called a polytype. The different polytypes are defined by the stacking sequence and referred by Ramsdell notation [6]. For instance, 2H, 4H, and 6H is hexagonal structure and has an AB, ABAC, ABCACB stacking sequence, respectively. Similarly, 3C is cubic with ABC stacking sequence. The different stacking sequences for 3C, 4H, and 6H in SiC are illustrated in Fig. 2.2.

2.2 Electrical properties

Material Properties

SiC has a high critical field of about 2·106 V/cm, a high thermal conductivity of 3-4 W/cmK, and a high saturated carrier velocity of 2·107 cm/s. Thanks to these properties, SiC devices have a large potential for high power, high temperature, and high frequency applications. The physical properties of SiC and other semiconductor materials are compared in Table 2.1 [1,7,8-9].

2.2.1 Wide bandgap

If the electrons in the valence band are excited with an external energy equal to the bandgap, they can move to the conduction band. At a given temperature, the thermal energy creates an intrinsic equilibrium electron-hole pair (EHP) concentration that depends exponentially on the bandgap. At the intrinsic temperature, the EHP concentration becomes equal to the doping

4 High Power Bipolar Junction Transistors in Silicon Carbide

Table 2.1 Electrical properties of SiC and other semiconductors

Property Si GaAs GaN 3C-SiC 6H-SiC 4H-SiC Bandgap, E g 1.12 1.43 3.4 2.4 3.0 3.2 (eV at 300K) Critical field, E c 2.5x105 3x105 3x106 2x106 2.5x106 2.2x106 (V/cm) Thermal conductivity, λ 1.5 0.5 1.3 3-4 3-4 3-4 (W/cmK at 300K) Saturated electron drift 1x107 1x107 2.5x107 2.5x107 2x107 2x107 velocity,vsat (cm/s) Electron mobility, µn 1350 8500 1000 1000 500 950 (cm2/V⋅s) Hole mobility, µ p 480 400 30 40 80 120 (cm2/V⋅s) Dielectric 11.9 13.0 9.5 9.7 10 10 constant, εr

concentration and this normally prevents adequate device operation. The intrinsic temperature depends on doping concentration and for Si a common temperature is around 150 oC. As a wide bandgap material, SiC has three times higher bandgap energy than that of Si. Due to the wide bandgap, the intrinsic temperature of SiC can reach 1000 oC thus making SiC very suitable for high temperature applications. To benefit from the high temperature capability of SiC, developments in package technology are, however, needed.

2.2.2 High breakdown electric field

Normally, wide bandgap materials have a high breakdown electric field because the wide bandgap leads to a high impact ionization energy. SiC has a high critical field of about 2 MV/cm in a high voltage device. This value is about 10 times higher than that of Si. The breakdown voltage of a p-n diode is given by the following relationship:

E W V = C (2-1) B 2

5 H.-S. LEE Chapter 2. Background

-1 10

-2 10

-3 10

-4 10

Width of the drift (cm) region Si GaAs

-5 6H-SiC 10 4H-SiC 1 2 3 4 10 10 10 10 Breakdown Voltage(V) Fig. 2.3. The width of the drift region for Si, GaAs, 6H-SiC, and 4H-SiC at different breakdown voltages.

Where VB is breakdown voltage, Ec and W are the critical field and the width of the drift region respectively. From equation 2-1, for SiC a significantly higher breakdown voltage can be achieved with the same drift region as for Si. Similarly, a thinner drift region can be realized in SiC for the same breakdown voltage (Fig. 2.3).

Much higher doping levels ND of the drift region can be used in SiC due to its high electric breakdown field (Eq. 2-2) [10].

2 2εVB εEC ND = 2 = (2-2) qW 2qVB

The specific on-resistance Ron-sp of the drift region is calculated by equation 2-3:

2 W 4VB R on−sp = = 3 (2-3) qµ n ND εµnEC

The minimum specific on-resistance is plotted in Fig. 2.4 for different breakdown voltages. The theoretical on-resistance of a SiC high voltage device can be around 1000 times lower than that of Si. The lower on-resistance leads to lower on-state power losses because it affects the forward voltage drop.

6 High Power Bipolar Junction Transistors in Silicon Carbide

1 10

) 0 2 10

Si -1 10 GaAS

6H-SiC -2 10 Specific On-Resistance(ohmcm 4H-SiC

-3 10 2 3 4 10 10 10 Breakdown Voltage(V)

Fig. 2.4. The minimum specific on resistance of the drift region for Si, GaAs, 6H-SiC, and 4H-SiC as function of breakdown voltage.

2.2.3 High thermal conductivity

The 2-3 times higher thermal conductivity of SiC compared to Si is an important figure of merit for high power applications. The generated heat gives a rise in temperature that degrades the device performance and the heating must be limited to avoid device failure. The high thermal conductivity increases the heat transport out from the device. This means that a smaller and less expensive thermal cooling system is needed. The thermal cooling system is an important part that affects the cost, size, and weight in power electronic systems.

2.3 Electrical Models of SiC

2.3.1 Mobility Model

The Arora model [11] is commonly used for describing the carrier mobility of SiC. The mobility is more anisotropic for 6H-SiC than it is for 4H-SiC. The low electric field mobility is dependent on the doping level and temperature and is given by

αn,p αn,p ⎛ T ⎞ µn,p,max ⎛ T ⎞ µn,p = µn,p,min ⎜ ⎟ + ⎜ ⎟ ⎝ 300 ⎠ ⎛ N + N ⎞ ⎝ 300 ⎠ (2-4) 1 + ⎜ D A ⎟ ⎜ ⎟ ⎝ N n,p,ref ⎠

7 H.-S. LEE Chapter 2. Background

1000 150 300 K 300 K 900 400 K 400 K 500 K 500 K 800 600 K 600 K 700 K 700 K 700 800 K 800 K /Vs) 100 2 /Vs) 600 2

500

400 50 300 (cm Mobility Hole

Electron Mobility (cm

200

100 0 0 15 16 17 18 19 20 15 16 17 18 19 20 10 10 10 10 10 10 10 10 10 10 10 10 Doping concentration(cm-3) Doping concentration(cm-3)

(a) (b) Fig. 2.5. The low field mobility model of 4H-SiC as a function of doping concentration (a) electron mobility (b) hole mobility

The high-field velocity is given by the Caughey-Thomas model [12]. At high electric fields, the carrier drift velocity (vD) saturates due to an increase of the optical phonon scattering and reaches the saturation velocity (vsat). The high-field mobility can be expressed as

0 µ n,p µ n,p (E) = 1 0 β β (2-5) ⎡ ⎛ µ E ⎞ ⎤ ⎢1+ ⎜ n,p ⎟ ⎥ ⎜ ⎟ ⎢ vsat ⎥ ⎣ ⎝ ⎠ ⎦

2.3.2 Intrinsic carrier concentration and Energy band gap

In an intrinsic semiconductor, the electron density is exactly equal to the hole density. From the mass-action law, we can write this intrinsic-carrier density as

− (E − E ) − E n2 = N N exp[ c v ] = N N exp[ g ] (2-6) i c v kT c v kT where Eg is the band gap energy and Nc and Nv are the effective density of states in the conduction and valence band, respectively. For a given semiconductor material at a constant temperature, the value of ni is constant, and independent of the Fermi energy.

8 High Power Bipolar Junction Transistors in Silicon Carbide

2.3.3 Incomplete Ionization

The donor and acceptor energy levels in SiC are deeper than the thermal energy at room temperature, so the dopants in SiC are not fully ionized even above room temperature [13-15].

N N + = D (2-7) D E − E 1+ g exp( C D ) c kT

N N + = A (2-8) A E − E 1+ g exp( A V ) v kT where EFn and EFp are the quasi-fermi levels, ED and EA is the donor and acceptor energy level, respectively. Due to the lack of specific information for SiC, the donor level degeneracy factor gc and acceptor level degeneracy factor gv are usually assumed to have the same values as in Si. For nitrogen donor levels in 4H-SiC, a dopant ionization energy EC-ED = 42 meV and gc=2 can be used. The p-type doping can be achieved with Al acceptors with ionization energy EA-EV = 191 meV and gv =4 [8].

2.3.4 Recombination

Carrier recombination is modeled using the well known Shockley-Read-Hall (SRH) equation.

The Shockley-Read-Hall (SRH) recombination rate RSRH can be defined [16-17] as

np − n2 RSRH = i (2-9) Etrap −Etrap kT kT τ p (n + nie ) +τ n ( p + nie )

Where τn and τp are the electron and hole lifetimes, respectively. These lifetimes depend on temperature, defect concentrations. dopant type and doping concentration. Common SRH carrier lifetimes are in the range of 0.1 – 2 µs in 4H-SiC epitaxial layers [18] but can be significantly reduced in ion implanted material.

Auger recombination is a process in which an electron and a hole recombine in a band-to- band transition, with the resulting energy given off to another electron or hole. The Auger recombination rate is given by

R Auger = (C n + C p)(np − n2 ) (2-10) n p ie

-31 -6 -1 -31 -6 -1 where Cn is 5·10 [cm s ] and Cp is 2·10 [cm s ] [19-20].

9 H.-S. LEE Chapter 2. Background

2.3.5 Bandgap narrowing

The high concentration of free carriers in a semiconductor can cause a significant reduction of the bandgap. At high doping levels, carrier-carrier interaction, carrier-impurity interaction and overlap of the electron wave functions are not negligible. These band gap narrowing effects are taken into account by band edge displacements that can be described [21] as

N + 1 N + 1 ∆E = A ( D )3 + B ( D ) 2 (2-11) c nc 1018 nc 1018 N + 1 N + 1 ∆E = A ( D ) 4 + B ( D ) 2 (2-12) v nv 1018 nc 1018

Table. 2.2. The parameter for bandedge displacement for different polytype of SiC [21].

n-type Anc Bnc Anv Bnv 4H-SiC -1.5 ×10-2 -2.93 ×10-3 1.9 ×10-2 8.74 ×10-3 6H-SiC -1.12 ×10-2 -1.01 ×10-3 2.11 ×10-2 1.73 ×10-3

Bandgap narrowing has an important effect in bipolar transistors by increasing the minority carrier concentration in the emitter, thus reducing the emitter efficiency.

2.4 The basic principle of BJT operation

The bipolar junction transistor (BJT) was invented by John Bardeen, Walter Brattain, and William Shockley at Bell Laboratories in 1947. Even though the importance of BJT has been challenged by the metal oxide semiconductor (MOS) based field effect transistor (FET), the BJT has still important applications that combine high power and high speed. A BJT consists of two joined back-to-back p-n junctions. The typical geometry of BJT with carrier flux components in forward-active mode is shown in Fig. 2.6. The BJT is a three- terminal electronic device. As the figure shows, the three regions of the BJT are called emitter, base and collector. The two junctions are referred to as the emitter-base and the base- collector junction respectively. The npn BJT is more widely used than the pnp BJT, because the electron mobility is higher than hole mobility. The basic principle of operation of the BJT is the control of the collector current by the base- emitter voltage. In the forward-active mode, the base-emitter junction if forward biased and the base-collector is reverse biased. The electrons injected from the emitter constitute the current InE. Most injected electrons, which are the minority carrier in base, will reach the collector (InC). Some electrons will recombine with majority carrier holes in base (IRB). The majority carrier holes injected from base give rise to IpE. Some electrons and holes will also recombine in the space charge region of the forward biased emitter-base junction (IR). Finally, the reverse-saturation current of the base-collector junction is designated as IC0.

10 High Power Bipolar Junction Transistors in Silicon Carbide

Emitter Base Collector

InE Electron flow I nC IC IE IR I RB Hole flow I + C0 N IpE P N

Fig. 2.6. Current components in an npn bipolar transistor operating under forward-active mode.

2.4.1 Current gain

The emitter, base, and collector current can be expressed as

IE = I pE + I nE + I R (2-16)

IB = I pE + IRB + IR − IC0 (2-17)

IC = InE − I RB + IC0 (2-18)

Now we assume that IR can be neglected as is the case if the material quality of the base- emitter junction is high. Then the emitter injection efficiency γ, which is the injected electron current from the emitter divided with the total emitter current, is defined by

I N D W γ = nE ≅ (1+ B ⋅ E ⋅ B )−1 (2-19) IE NE DB WE -3 where NB, NE = base and emitter doping concentration (cm ), 2 DB, DE = base and emitter minority carrier diffusion coefficients (cm /sec),

WB, WE = base and emitter region widths (cm)

Equation 2-19 holds if WE is much smaller than the hole diffusion length LpE in the emitter. If the opposite is true, then WE should be replaced by LpE. Two important parameters in the characterization of the bipolar transistors are the common- base current gain α and common-emitter current gain β.

11 H.-S. LEE Chapter 2. Background

The common-base current gain α is written as

InC InC InE α = = ⋅ = αT ⋅γ (2-20) I E InE I E the base transport factor αΤ is the ratio of the electron current reaching the collector region and the electron current injected from the emitter.

The common-emitter current gain β is defined as the ratio of the collector and base currents

I α β = C = (2-21) I B 1−α

2.4.2 Breakdown voltage

There are two mechanisms that can limit the breakdown voltage of bipolar transistors. As the reverse bias of the base-collector junction is increased, the base-collector depletion region can extend through the base region and reach the base-emitter depletion region. This phenomenon is called punch-through and it limits the open-base breakdown voltage if the total dose of the base doping is too low. The second breakdown mechanism is the avalanche breakdown process. As the reverse bias voltage of the base-collector junction increases with the emitter left open, the collector current starts to increase rapidly as the maximum electric field reaches the critical field. This is similar with the breakdown process of a P-N junction diode. If the collector-emitter junction is biased with the base open circuit, then the base-collector junction will also be reverse biased. The avalanche multiplication at the base-collector junction will now be multiplied by the transistor gain thus increasing the avalanche current. Normally, the common emitter breakdown voltage BVCEO and common base breakdown voltage BVCBO can be described in a relationship that depends on the current gain. The value of BVCEO is smaller than BVCBO.

BVCBO BVCEO = 1 (2-22) (β ) n where n is an empirical constant. Generally, n is between 3 and 6 in silicon [22]. However, n is different in SiC. The n value was reported to range between between 3 and 13 in 4H-SiC [23].

Chapter 3

Fabrication of SiC Bipolar Transistors

One of the main advantages in SiC device technology is the compatibility with Si processing technology compared with other wide bandgap materials. However, there are some differences from Si process technology because of the chemical inertness and the thermal stability of SiC. First of all, wet chemical etching is almost impossible in SiC at room temperature. Instead, plasma etching is available for definition of mesa-etched structures in SiC. The diffusivity of impurities in SiC are orders of magnitude lower than in Si and diffused doping profiles are therefore normally not considered for SiC devices. Generally, ion implantation and epitaxial growth are needed to get proper doping concentrations. Finally, much higher temperatures are needed for thermal oxidation, for annealing of metal ohmic contacts, and for activation of implanted impurities. This chapter will describe process technology for SiC. In this work, all processing steps have been performed with 4H-SiC. However, the process technology described in this chapter is valid also for other polytypes of SiC, such as 3C- and 6H-SiC although the process parameters will be differ.

3.1 Review of design and processing issues for SiC BJTs

The typical cross-section view of a SiC power NPN Bipolar Junction Transistor (BJT) is shown in Fig 3.1. Generally, two approaches have been used to fabricate npn SiC-BJTs because of the extremely low diffusion of dopants in SiC. One is epitaxial growth of the emitter with a p+ impanted base contact region in the base layer with some separation from the emitter edge (Fig. 3.1 (a)). The other is an n+ implanted emitter region and emitter contact on a base layer after etch removal of the p+ base epitaxial growth (Fig. 3 b). The n+ epitaxially grown structures are preferred nowadays because the implanted emitter suffers from

13 H.-S. LEE Chapter 3. Fabrication of SiC Bipolar Transistors

Emitter contact Epitaxial grown emitter Base contact Implanted emitter

N+ emitter Base contact P+base Emitter contact

P-base P+ implantation P-base N+ implantation

N-collector N-collector

+ + Collector contact N doped Collector contact N doped

(a) (b)

Fig. 3.1. A schematic cross-section of (a) an epitaxial grown emitter and (b) an implanted emitter

Table 3.1 Review of SiC BJTs that have been demonstrated.

Emitter Base Collector Breakdown Current ( Doping [cm-3] ( Doping [cm-3] ( Doping [cm-3] Voltage Ref. Group gain β / Thickness [µm] ) / Thickness [µm] ) / Thickness [µm] ) BNCEO [kV] Purdue 1 ×1019 / 1 2 ×1017 / 1 8 ×1014 / 50 15 3.2 [24] Colorado 1 × 1019 / 0.2 2 × 1018 / 0.1 2 × 1016 / 3 17.4 - [25] Cree */ 0.75 2.5 ×1017 / 1 2.5 ×1015 / 20 20 1.8 [4] RPI Implanted emitter 2 × 1017 / 1 4 × 1015 / 12 9 1.1 [26] Cree / 0.75 2 × 1017 / 1 4.4 × 1015 / 15 11 1.3 [27] Purdue 1 × 1019 / 1 1 × 1017 / 1 2.4 × 1015 / 20 55 0.5 [28] Rutgers */ 0.7 3 ×1017 / 0.8 6 ×1015 / 12 32 0.7 [29] Rutgers 1 × 1020 / 1 8.5 × 1017 / 1.4 7 × 1014 / 50 7 9.2 [30] RPI 1 × 1019 / 0.8 2.3 × 1017 / 1 1 × 1015 / 45 9 4 [31] KTH 9 ×1019 / 0.4 1017 -1018/ 0.4 5 ×1015 / 15 6 1 [Paper IV] KTH 9 × 1019 / 0.3 4 × 1018 / 0.3 8 × 1015 / 10 5 - [Paper I] Cree */ 1.5 2 × 1017 / 1 4.8 × 1015 / 15 40 1 [3] Rutgers 1.3 ×1019 / 0.8 2.9 ×1017 / 1 5.5 ×1015 / 15 5 1.6 [5] KTH 5 × 1019 / 0.6 3 × 1017 / 0.7 4 × 1015 / 15 64 1.1 [Paper III] * not mentioned

incomplete activation of dopants and defects from implantation damage even after high temperature annealing. To avoid the implantation damage, in the emitter and in the base- emitter junction region, the epitaxial emitter structure as shown in Fig. 3.1 a has been used in this work.

A previously fabricated BJTs by Cree showed a common emitter current gain of 20, and a breakdown voltage 1.8 kV in 4H-SiC [25]. A high current gain of 55 with relatively low breakdown voltage of 500 V attributed to Al spiking into the base region after metal contact annealing [28]. Recently, a 1 kV, 30 A 4H-SiC was demonstrated with a common emitter current gain of 40 [3]. However, an improved current gain is still needed in order to compete with Si devices (MOSFETs and IGBTs) in most applications. A review of experimentally obtained SiC BJTs results is given in table 3.1.

14 High Power Bipolar Junction transistors in Silicon Carbide

For high voltage BJT structures, the collector doping has to be low enough forming a thick drift region of 10-15 µm for a 1200 V SiC device. Also, the base should be designed with a sufficiently high doping dose to avoid punch-through at the maximum required blocking voltage. On the other hand, the doping concentration in the emitter normally must be large compared to the base doping for high emitter injection efficiency, resulting in a high current gain. However, as the emitter doping concentration increases, doping induced band-gap narrowing is effectively increased, and above some doping level the emitter injection efficiency starts to decrease. In addition, as the emitter is highly doped, the diffusion length of minority carrier in emitter is decreased due to increasing Auger recombination. Bandgap narrowing and Auger recombination reduce the emitter injection efficiency and thus the current gain. The high-level injection in the base that occurs at high current densities results also in a reduction of the emitter injection efficiency.

Optimization of the current gain is quite complex since the current gain depends on parameters such as the material quality and the surface passivation besides the thicknesses and doping levels of the base and emitter layers mentioned earlier. Improved epitaxial growth conditions can increase the current gain, by resulting in higher carrier lifetimes. Effects from surface recombination on the current gain of SiC BJTs must also be taken into account. Improved passivation is needed to reduce the surface recombination at the etched side-wall of the base-emitter junction.

3.2 Bulk and epitaxial growth

The first SiC material growth was initiated by Acheson. But with the Acheson process the single crystalline material quality was low. Lely later presented a method for single crystal growth in 1955. The Lely method had a limitation in size (< 1 cm2), and could only be used for 6H-SiC, even though high material quality could be obtained. This method was refined by Tairov and Tsvetkov in 1978 [32]. This is now known as the modified Lely method. In earlier days the modified Lely method was used whereas today sublimation growth of SiC is preferred because it can produce large diameter single crystalline SiC. Today, commercial production volumes of 4H- and 6H-SiC are available in diameters up to 75 mm from some companies such as Cree [2], Intrinsic [33], Caracal [34] and 100 mm wafers have already been demonstrated [2, 33-34].

Epitaxial growth is an essential process required for device fabrication in SiC due to the relatively low purity of SiC substrates. Generally, epitaxial layers of SiC are utilized as active regions of devices. The chemical vapor deposition (CVD) technique has been recognized as the common epitaxial growth method for various device applications of SiC. It is accomplished by high purity Si- and C- precursor gases with hydrogen carrier gas in a reaction chamber, which is heated up to the growth temperatures in the range of 1500 oC to 1850 oC. The horizontal hot-wall CVD reactor gives important benefits of long-term stability and growth of thick layers. Especially, long continuous growth time (> 30 hr) can make high quality epitaxial layers without appreciable degradation of the SiC surface. These properties can make it useful for high power device fabrication. There are other epitaxial growth techniques, such as liquid-phase epitaxy (LPE), sublimation epitaxy technique is similar with

15 H.-S. LEE Chapter 3. Fabrication of SiC Bipolar Transistors

modified Lely growing method except for a lower processing temperature. The advantage of this technique is a very high growth rate (> 400 µm/hr). The starting material for the BJT process in this work was 2 inch 4H-SiC substrates purchased from Cree Research Inc.. The lowly doped (1015~1017) epitaxial layer and the highly doped (~1019) epitaxial layer was grown in CVD reactors by Acreo AB and Linköping University respectively.

3.3 Etching of SiC

As mentioned earlier, the strong chemical bond between Si and C makes SiC it difficult to etch. Normally, wet chemical etching of SiC has to be done at high temperature (> 350 oC), but wet chemical etching of SiC has problems because it is relatively isotropic and this prevents etching of steep trenches. Therefore, plasma etching of SiC is preferred (see Table 3- 2). Reactive ion etching (RIE) as a plasma etching technique has been used for SiC etching.

Table 3.2 A summary of etching methods for SiC

Polytype of Technique parameters Etch rate (Ǻ/min) Ref. SIC Wet chemical Molten KOH 4H 26000 [35]

RIE CF4/O2 3C 600-2600 [36]

SF6/O2 6H 3000 [37]

CF4/O2 6H 2200 [38]

NF3/O2 6H 493 [39]

NF3 4H, 6H 1500 [39] ICP Cl2/Ar 4H 2300 [40] SF6/O2/Ar 4H 5000 [41] SF6 4H 3000 [42] ECR CF4/O2 4H, 6H 700 [43]

However, the main problem of conventional RIE for SiC etching is residual surface damage due to the high dc self-bias, which leads to a rougher surface. Recently, high density plasma equipments, such as inductively coupled plasma (ICP) etching or electron cyclotron resonance (ECR) etching have emerged as alternatives to RIE.

In ICP etching, the plasma is generated at lower pressure by supplying rf power to the inductive coil which is mounted on the outside of the quartz (see Fig. 3.2). A separate rf power source is connected to the wafer platen, to allow control of ion energy and flux. As a result, high density and low energy ions give better selectivity and less surface damage than RIE.

16 High Power Bipolar Junction transistors in Silicon Carbide

Fig. 3.2. A schematic drawing showing a chamber of a STS ICP equipment [44].

150

140 130 120 110 100 90

80 70 60

SiC Etch Rate (nm/min) 40 30 20 4 6 8 101214161820222426283032 ICP Energy (W)

Fig. 3.3. Etch rate as a function of platen power in a STS ICP reactor.

17 H.-S. LEE Chapter 3. Fabrication of SiC Bipolar Transistors

) 1,50 2

1,45

1,40

1,35

1,30

1,25

1,20

Etch Selectivity of SiC (SiC/SiO 1,15

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 ICP Energy (W)

Fig. 3.4. the SiC/SiO2 etch selectivity as function of platen power.

In this work, a fluorine-based (SF6/Ar) ICP reactor was used to etch SiC. The typical parameters were SF6 flow rate of 21 sccm, Ar flow rate 9 sccm and 5.0 mTorr base pressure and a deposited silicon dioxide mask was used. The etch rate and the SiC etch selectivity (SiC/SiO2) was around 135 nm/min and 1.47 with 30 W of platen power, respectively (see Fig. 3.3, Fig 3.4).

3.4 Ion implantation

For SiC processing, ion implantation is the only available technique for selective area doping due to the extremely low diffusion coefficients of dopants in SiC. Ion implantation of SiC bipolar transistors has been used for junction formation of P-N diodes [45], highly doped Ohmic contact regions [46-48], and device isolation and junction terminations [49-52]. For n- type doping, nitrogen (N) and phosphorus (P) are used as typical dopants. Acceptor doping by ion implantation is often used to obtain low contact resistance to p-type regions in pn diodes, BJTs and JFETs. Aluminium (Al) and boron (B) are used for p-type dopants. To minimize lattice damage, ion implantation in SiC is frequently performed at a high temperature in the range of 300 to 800 oC. Acceptor ions are implanted with concentration between 1017 and 1021 cm-3. Annealing at high temperatures in the range of 1500-1700 °C is essential after ion implantation to obtain activation of the implanted dopants and re-crystallisation of the SiC material

There are three important aspects of post-implantation annealing:

(i) To activate implanted dopants (ii) To reduce implantation induced lattice damage (iii) To preserve the surface morphology and to avoid dopant outdiffusion

18 High Power Bipolar Junction transistors in Silicon Carbide

Therefore, different annealing conditions such as temperature, ambient gas, and time etc. must be evaluated. Two kinds of high temperature annealing methods, such as furnace and lamp annealing, have been used. Furnace with high purity inert gas ambient such as argon is widely used for the post implantation annealing step at typical temperatures between 1600 and 1700 oC for 10-30 min. A low sheet resistance of 20 KΩ/ for an Al implantation dose of 1.2·1015 cm-2 has been achieved but the surface roughness was 18 nm for annealing temperature 1700 oC for 30 min [53]. Another method for high temperature annealing after ion implantation is flash lamp annealing which achieves higher temperatures within shorter time than furnace annealing thus causing less surface roughness. A flash lamp annealing at 1770 oC for 5 min showed a good surface roughness of less than 1 nm while achieving 70 KΩ/ for an Al implantation dose of 1·1015 cm-2 [53]. These two annealing method have both a trade-off between surface roughness and a sheet resistance, i.e. a longer annealing. Recently encapsulating techniques such as AlN and graphite were introduced to protect the SiC surface during post implantation annealing. As a result, AlN and graphite encapsulating resulted in good surface morphologies and prevented step bunching effects [54].

In this work, implantations with a silicon dioxide or photoresist mask have been used to form the junction termination edge (JTE) and the p+ base doping required for the ohmic contact. Before ion implantation, a proper depth profile was determined with TRIM [55] simulation (see Fig.3.5). Ion implantation of 300 keV Al was used to form the junction termination extension (JTE). Different doses were used in the four quarters of the wafer for high base doping. After post-implantation annealing, secondary ion mass spectrometry (SIMS) was performed to measure the impurity depth profile.

Fig. 3.5. The depth profile generated by TRIM simulation using silicon oxide mask.

19 H.-S. LEE Chapter 3. Fabrication of SiC Bipolar Transistors

3.5 Oxidation and oxide deposition

SiC is the only wide bandgap material which has silicon dioxide (SiO2) as a native oxide. This SiO2 is useful for MOSFETs and also in the bipolar transistor process:

1) thermally grown SiO2 can be used for sacrificial oxide to remove contaminations and surface damage 2) deposited SiO2 provides good masking during the plasma etching and ion implantation 3) thermally grown SiO2 can be used as passivation of the etched pn junctions and protect the surfaces from contaminants.

There are two possible chemical reactions for dry thermal oxidation. 3 SiC + O ↔ SiO + CO (3-1) 2 2 2

SiC + O2 ↔ SiO2 + C (3-2)

Thermal oxidation of SiC is considerably more complicated than it is for Si. Most of the carbon is removed from oxide as CO or CO2 gas. But some carbon is still remaining at the SiC/SiO2 interface, and this can affect the electrical properties [56]. The thermal oxidation rate is significantly lower than for Si. The thermal oxidation thickness was around 50 nm on n-type 4H-SiC when it was performed at 1250 oC during 1 hour. Figure 3.6 shows oxide thickness for dry oxidation of 4H-SiC [57]. In this work, thermal oxidation has been used to form passivation of the etched terminations of the base-emitter and the base-collector junctions.

Another way to form the SiO2 is plasma enhanced chemical vapor deposition (PECVD). This method has useful advantages such as thick oxide deposition without SiC consumption and a carbon free SiO2 layer is obtained. The general process recipe is a mixture of N2O and SiH4 gases in Ar atmosphere. The deposition rate was around 50 nm/min. A thick oxide layer was used as a mask for ion implantation and SiC plasma etching as well as to make an overlayer after metallization with PECVD in this work.

(a) (b) Fig. 3.6. The Oxide thickness as a function of time and temperature for dry oxidation of 4H- SiC: (a) on C-terminated face (b) on Si-terminated face [57].

Fig. 3.6. The Oxide thickness as a function of time and temperature for dry oxidation of 4H- SiC: (a) on C-terminated face (b) on Si-terminated face [57].

20 High Power Bipolar Junction transistors in Silicon Carbide

3.6 Metallization

Ohmic contact formation in device processing is especially important, because a voltage drop induced by a poor contact will increase the power loss and decrease the device performance. -5 2 Normally, the SiC specific contact resistance ρc is in the range of ~10 Ωcm n-type [58-63] and ~10-4 Ωcm2 in p-type SiC regions [46, 48, 64-66]. The p-type SiC specific contact resistance is typically higher than that of n-type SiC, due to a higher Schottky barrier. For BJTs poor ohmic contact present an additional voltage drop in the forward biased operation. For example, the specific on-resistance of drift region in paper III can be calculated as 2.5 ·10- 3 Ωcm2 from equation 2-3. If the contact resisivity is not significantly less than this value, the additional voltage drop is essential in this BJTs. To obtain good ohmic contacts is strongly dependent on some factors: surface preparation, high surface doping concentration, choice of metal and annealing temperature. Surface preparation before metal deposition is important to remove residual of oxide and photoresist that can negatively affect the ohmic contact behaviour. Additionally surface roughness after etching, ion-implantation and annealing can degrade the ohmic contacts. Recently, to reduce the surface roughness, AlN or graphite encapsulant has been adopted during high temperature annealing after ion implantation [54, 67]. A significant reduction of ρc can be obtained by a high doping concentration at the surface for both n-type and p-type SiC, by enabling a tunnelling current through the thin barrier. The high doping concentration that is needed to form a good ohmic contact is in the range of 1019 cm-3 and above. The choice of the best metal for ohmic contacts to SiC is still an important topic and a challenge for many SiC research groups. Many candidate metals for ohmic contacts have been reported, and a summary of those is given in Table 3.3. Post deposition annealing is required to form an ohmic contact. Often, high temperature (> 900 oC) annealing is used but the required annealing temperature is highly dependent on the metal. Table 3.3 Literature Review of ohmic contact on SiC in the literature.

Contact ρ Annealing Polytype C Doping (cm-3) Ref. Type metal (Ωcm2) condition n TiC 4H 4×10-5 1.3×1019 950 oC [58] 1000 ~ 1050 Ni/Cr/W 4H 10-4~10-6 1017~1018 [59] oC 1.0×10-4 Ni-Cr 4H 4.8×1017 1100 oC [60] ~1.6×10-5 Ni 4H 6×10-6 1×1019 1050 oC [61] -5 18 o CoSi2 6H 3×10 7×10 900 C [62] TiW 4H 2~6×10-5 1.3×1019 950 oC [63] TiW 4H 1.4×10-4 5×1019 950 oC [Paper III] Si/Pt ~10-3 30 ~ 400 oC p 4H 1×1019 [64] Al/Ti ~10-4 1100 oC Al 4H 6.1×10-5 6×1020 950 oC [65] Ti/Al 4H 10-6 3×1020 1000 oC [48] Ni 4H 7×10-3 2×1020 1000 oC [48] TiC 4H 1.0×10-4 2×1019 850 oC [46] TiW 4H 1.2×10-4 1.3×1019 950 oC [66] TiW 4H 3.7×10-4 7×1019 950 oC [Paper III]

21 H.-S. LEE Chapter 3. Fabrication of SiC Bipolar Transistors

Ni-based and Al-based contacts are widely used for n-type and p-type regions, respectively. However, these contacts have some problems. For example, annealing at high temperatures above 1000 oC is required to form an ohmic contact if Ni is used. This can lead to poor surface morphology and affect the device characteristics as well as the contact resistance. The low melting temperature of aluminum makes it difficult to apply it in a high temperature device. In addition, Al sometimes causes spiking problems in which the reaction layer penetrates deeper than the highly doped region during the annealing. This spiking problem can influence the breakdown voltage in a BJT by causing punch through [28] and therefore it is important to use a metal which does not cause spiking. Additionally, a multifunctional metal which can be used for both n-type and p-type regions is wanted because it can reduce the process complexity especially for BJTs. The titanium-tungsten (TiW) alloy is one of the promising alternatives that can satisfy these requirements. TiW has also the advantage of a lower required annealing temperature (around 900-950 oC) than that of Ni and TiW has excellent long-term reliability [66].

In this work, TiW was sputter deposited on the base and emitter layers to obtain ohmic contacts. A RF sputter was used for TiW deposition from a source with weight ratio of 30:70 (Ti:W) at a sample temperature of 60-120 oC. Furnace annealing of the contacts was performed at 900 - 950 oC in argon atmosphere. The electrical characterization of TiW ohmic contact is described in detail in chapter 4.

3.7 Layout and fabrication process for SiC BJTs

All photolithographic steps were performed using either a Canon 4:1 aligner or a DSW 8500 g-line 5:1 stepper. The DSW stepper lithography with a Si 4 inch carrier wafer was used to obtain a sufficiently high optical resolution and alignment accuracy (better than 1 µm) in the improved BJT process. As positive photoresist, the Shipley 1813 and Shipley 1818 were mainly used, while AZ5214 resist was used for image reversal. The BJTs fabricated in this work (Paper I-IV) were made with 6-8 mask steps depending on the design. The entire layout used with the Canon aligner is shown. Different emitter widths from 20 µm to 50 µm were designed for one-finger transistors, while two- and four-finger transistors were fabricated with 40 µm emitter width. A top view and cross- sectional view of a four-finger transistor are shown in Fig. 3.8. A new design of BJTs was fabricated using a DSW stepper. This layout has a set of different transistor designs with different emitter widths from 5 to 30 µm. The multi-finger transistors have been designed with three different emitter widths of 5, 10 and 20 µm respectively. The layout of different transistor designs and the top optical and cross-sectional views of the multi-finger transistor is shown in Fig. 3.9 and Fig. 3.10, respectively. The major process step of SiC BJTs are also illustrated with Fig. 3.11. A summary of design parameters for all batches are presented in table 3.4. The 1st batch design used a high base concentration to achieve a high breakdown field and prevent the punch through effect between emitter and base. Also, the implantation for base ohmic contact could be skipped due to the relatively high doping concentration in base. However, the high doping in the base layer resulted in a low common emitter current gain likely to depend on a low mobility and a short carrier lifetime in the base, even though the thickness was thin.

22 High Power Bipolar Junction transistors in Silicon Carbide

(a)

(b)

Fig. 3.7. The layout of (a) the different transistor structures (b) the full mask layout

Emitter Base

Drift collector

Buffer Substrate

(a) (b)

Fig. 3.8. (a) Cross-sectional view of a bipolar junction transistor and (b) a SEM image of a four-finger transistor.

23 H.-S. LEE Chapter 3. Fabrication of SiC Bipolar Transistors

(b)

(c)

(a)

Fig. 3.9. The layout of (a) the entire mask layout (b) the different emitter width transistors of 5,10,20,30 µm (c) the 20 µm emitter width transistor.

10µm

Emitter contact 2 µm 19 -3 200 nm ND =5 • 10 cm 18 -3 Emitter 400 nm ND =7 • 10 cm 4 µm Base contact 17 -3 700 nm NA= 3•10 cm

15 -3 N ≈7•1019 cm-3 Base 15 µm ND =4• 10 cm A

N+ substrate Collector contact

(a) (b)

Fig. 3.10. (a) Top view of 20 µm emitter width transistor with 300×300 µm active area (b) Cross-sectional view of the active region of the same transistor.

24 High Power Bipolar Junction transistors in Silicon Carbide

Emitter Oxide/Resist

Base Emitter Base

Substrate Substrate

(a) (b)

Mask Oxide/Resist

Emitter

Base

Substrate

Emitter Base Base Substrate

Substrate

(e) (f)

Fig. 3.11. The main steps of the SiC BJTs process (a) three epitaxial layers as a starting material (b) oxide deposition with a PECVD process (c) stepper photolithography with a Si 4 inch carrier wafer obtaining high optical resolution (d) Oxide dry etching (e) the mesa structure definition by ICP etch with an oxide mask (f) A fabricated transistor after the metallization steps.

25 H.-S. LEE Chapter 3. Fabrication of SiC Bipolar Transistors

Table 3.4 A summary of design parameters for the different batches.

Design parameter BJTs, 1st Batch BJTs, 2nd Batch BJTs, 3rd Batch Emitter 5·1019 Doping (cm-3) 9·1019 9·1019 1.1·1019 (Two step emitter layer) Thickness (µm) 0.3 0.3 0.6 Base Doping (cm-3) 4·1018 1017-1019(graded) 3·1017 Thickness (µm) 0.3 0.4 0.5 Extrinsic layer - 4·1020 - Collector Doping (cm-3) 8·1015 5·1015 4·1015 Thickness (µm) 10 15 15 Highest Current 5 15 64 gain β Breakdown Voltage * 1000 1100 (V) Layout 20,30,40, and 50 5,10,20 and 30 5,10,20 and 30 Emitter widths (µm) (1 finger) ( 1finger) ( 1finger) Device area 300 µm ×300 µm, 300 µm ×300 µm, 200 µm ×300 µm, (including contact 600 µm ×600 µm, 600 µm ×600 µm, 400 µm ×300 µm pad) 1200 µm ×1450 µm 1200 µm ×1450 µm Entire mask Fig. 3.7. Fig. 3.9. Fig. 3.9. Paper I IV II - not used, * not measured.

One special design issue of the 2nd batch was the using of an extrinsic base layer that was fabricated using epitaxial regrowth. This regrowth is an interesting alternative to base contact implantation. The use of regrowth allows a shorter distance between the emitter edge and the extrinsic base than when using a base contact implant which creates more lifetime-reducing defects. It was, however, found that the regrown region was difficult to remove from the emitter edge by etching since the epitaxial growth on the emitter side-wall was significantly faster than on the flat surfaces. A graded intrinsic base was also used in the 2nd batch to create a built-in electric field to enhance the base transport factor and the current gain. The modest gain of 15 that was obtained in the second batch depends on several factors with a remaining epitaxial regrowth regions at the emitter-edge and an interrupted epitaxial growth of the base and emitter layers. In the 3rd batch, a continuous growth of the base-emitter junction was used to reduce the defect concentrations at base-emitter interface. Another design characteristic of this batch was that the emitter was grown as a two-layer structure. This is effective to improve the emitter injection efficiency by using a moderately high doping at the junction, while maintaining a good ohmic contact using a higher doping in the surface region. Also, Al base contact implantation was adapted in this batch and the base thickness was a little increased compared to before two batches for improvement of breakdown voltage and consideration of the implanted highly doped layer of base.

26 High Power Bipolar Junction Transistors in Silicon Carbide

Chapter 4

Characterization and Results This chapter describes the characterization of the fabricated SiC BJTs and the measurement methods which were used in this work. Results from material characterization by XRD, TEM, and SIMS measurements are summarized. Electrical characteristics, such as transistor I-V measurements, the extraction method for contact resistance using TLM structures and extraction of the junction temperature of BJTs are presented.

4.1 SiC Power BJT Results

4.1.1 BJTs with an epitaxially regrown extrinsic base layer

A highly doped extrinsic base is necessary for several reasons. Firstly, a high doping lowers the base contact resistivity, which is crucial for the on-resistance. Secondly, the resistivity of p-type SiC is quite high, as a result of the low hole mobility and incomplete dopant ionization, and this causes an increased potential at the location of the base contact at high currents. Since the base contact is located above the collector region, this can induce a locally forward biased base-collector junction that brings the transistor into saturation thus reducing the current gain. Additionally, the on-state collector-emitter voltage is increased and the effect becomes more severe if the current gain is low. A high base resistance has also a negative effect by decreasing the switching speed of the transistor. To avoid these effects, a low resistive extrinsic region has to be placed very close to the intrinsic region. Finally, a low ohmic contact resistivity can be achieved with a highly doped epitaxially grown base layer due to high doping concentration and smooth surface preparation. In this work (Paper IV), the collector, base and a thin n+ emitter were all epitaxially grown as shown in Fg. 4.1(a),. Emitter and base fingers were defined by oxide masked dry etching of SiC in an inductively coupled plasma (ICP) system. Ion implantation of 300 keV Al was used to form a 100 µm wide junction termination extension (JTE) with four different implantation doses of 7·1012 cm-2, 1·1013 cm-2 and 1.5·1013 cm-2 in three different quarters of the wafer,

27 H.-S. LEE Chapter 4. Characterization and Results

Different Slope

Base contact Emitter contact SiO2 Spacer P+ regrowth 4*1020cm-3 + 19 -3 N emitter, ND=9*10 cm P-base, graded 1017–1018 cm-3, 400 nm

15 -3 N-collector, ND=5*10 cm , 15 µm

(a) (b)

Fig. 4.1. (a) Cross-section of the device structure obtained from process simulation ISE-DIOS (b) AFM image of the BJT top surface before passivation and metallization

10 200 Emitter current vs. 8 collector-emitter voltage 150

6 100 7e12 1e13 4 1.5e13 no Al 50 2

(microamps) current Emitter Common emitter current gain 0 0 0 200 400 600 800 1000 1200 0.01 0.1 V (V) Collector current (A) CE (a) (b) Fig. 4.2. (a) Measured common emitter current gain as function of collector current at 13 -2 VCE=30V (b) highest breakdown voltage 1000 V at JTE implantation 300 keV, 1*10 cm . with a remaining reference quarter without implantation. Epitaxial regrowth of a highly Al- doped (4·1020 cm-3 ) layer was performed to enable a low resistive ohmic contact to the base of 2.4·10-4 Ωcm2 and a low base series resistance. The regrowth was then removed from a lithographically defined area around the emitter by dry etching. A thermal oxide was grown for passivation and TiW was sputtered as contact metal to base, emitter and collector.

Unfortunately, the regrowth epilayer was not perfectly removed from the etched sidewall of the base-emitter junction because the epitaxial growth of very highly doped layers has a faster lateral than vertical growth rate and resulting in a thicker p+ layer at the side-walls. The remaining p+ regrowth at the side-wall of the emitter is schematically illustrated as the spacer in Fig. 4.1(a). It can be seen that the slope of the spacer region varies with orientation in Fig. 4.1(b).

28 High Power Bipolar Junction Transistors in Silicon Carbide

Measurements during the process before the epitaxial regrowth (probing directly on SiC) showed a current gain of 15 even at 150 °C. However, the common emitter current gain was reduced to 6 after epitaxial regrowth and etching as shown in Fig. 4.2 (a). The current gain reduction is presumably caused by a local reduction of the emitter efficiency where the highly doped p+ region is remaining at the emitter edge. A breakdown voltage of 1000 V was obtained for devices with Al implanted JTE (see Fig. 4.2 (b)). Although some BJTs had a high breakdown voltage, many BJTs had a high reverse leakage current likely caused by a remaining p+ regrowth layer outside the base-collector junction. The problem with the remaining regrowth spacer region can be solved by adding a mask step and dry etching for definition of a new base-emitter side-wall to the left of the spacer in Fig. 4.1.

4.1.2 Continuous growth run of epitaxial layers BJTs

The schematic cross-sectional view of the new fabricated 4H-SiC BJTs with varying geometrical dimensions is shown in Fig. 4.3 (Paper II). A wafer with low-resistive n-type substrate and a 15 µm 4·1015 cm-3 nitrogen doped epitaxial collector layer was purchased from Cree Research Inc. The base and emitter layers were grown epitaxially in a continuous growth run by Acreo AB. This continuous growth of the base-emitter junction is believed to be important for achieving a high current gain, since an interrupted epitaxial growth can increase the defect concentration and thus the recombination current at the base-emitter interface. A 500 nm thick base layer was grown with an Al concentration of 2.4·1017 cm-3. The emitter was grown as a two-layer structure with nitrogen doping; 400 nm with 1.1·1019 cm-3 followed by 200 nm with 6·1019 cm-3 on top. Emitter fingers and a surrounding base-collector junction were formed by inductively coupled plasma (ICP) etching using an oxide mask. Photolithography with resolution and mask alignment accuracy well below 1 µm was enabled by using a stepper with the 2 inch SiC wafer mounted on a 4 inch Si carrier wafer. A two- energy implantation of aluminum (2.0·1014 cm-2 with 30 keV and 4.9·1014 cm-2 with 65 keV) was also used to enable ohmic contact formation to the base. High temperature annealing was performed at 1600 ºC during 10 minutes in Ar ambient to activate the Al dopants and reduce the defect concentration. Dry thermal oxidation at 1100 ºC during five hours was carried out to passivate the etched terminations of base-emitter and base-collector junctions. Contact windows were etched and TiW (30 % Ti and 70 % W) was sputtered to provide contacts to the emitter, base and collector regions. The contacts were annealed at 950 ºC during 30 minutes in Ar ambient to improve the contact resistivity.

WE/2

Emitter contact 19 -3 200 n m ND =6• 10 cm 19 -3 W 400 n m ND =1.1 • 10 cm p+ Base contact 17 -3 500 n m NA = 2.4•10 cm 15 -3 N ≈6•1019 cm-3 15 µ m ND =4• 10 cm A

N+ substrate Collector contact

Fig. 4.3. Schematic cross-section of the fabricated 4H-SiC BJT.WE is the emitter finger width and WP+ is the distance between emitter edge and base implantation.

29 H.-S. LEE Chapter 4. Characterization and Results

100 80

W =30 µm V =35 V 70 E CE W =20 µm 80 V =1100 V E BR 60 W =10 µm E 50 60

40 40 30

20 (microamps) Current 20

10 gain current emitter Common 0 0 0 200 400 600 800 1000 1200 0.001 0.01 0.1 Collector current (A) Collector-emitter voltage (V)

(a) (b) Fig. 4.4. (a) Measured common emitter current gain (β) vs. collector current (IC) for BJTs with different emitter finger widths (WE) during a base-emitter voltage sweep at a constant collector-emitter voltage VCE=35 V (b) Measured open-base blocking characteristics

A high current gain exceeding 60 is observed for the BJT with WE=30 µm at IC=60 mA and β decreases at higher IC under the influence of self-heating.

Fig. 4.4 (a) also displays measured current gain β vs. collector current IC at VCE=35 V for BJTs with three different emitter finger widths WE of 10, 20 and 30 µm. All three BJTs have an emitter finger length of 500 µm and the distance between the base-emitter junction and the base contact implant is 5 µm to avoid influence of ion implantation induced damage on the current gain decreases with decreasing WE.

The BJT has an open-base breakdown voltage of BVCE0=1100 V (Fig. 4.4 (b)). A significant variation of the breakdown voltage was found over the wafer with breakdown voltages varying between 500 V and 1100 V. The highest breakdown voltages were consistently measured for BJTs located closer to the wafer edge. A reasonable explanation for this behavior is that the BJTs are limited by punch-through breakdown and that the base doping is higher closer to the edge of the wafer as has been reported for epitaxially grown layers [68].

4.1.3 Wafer map of SiC BJTs

The wafer measurement mapping provides spatial information of defective chips as a processing yield as well as a trend of device design with measurement analysis. In this work (paper II), the different emitter finger widths WE of 10 and 20 µm with different base implantation distance Wp+ in the range of 1-4 µm were used in order to investigate

30 High Power Bipolar Junction Transistors in Silicon Carbide

(WE, Wp+) β (20 µm , 2 µm) @ (20 µm , 3 µm)

IC (mA) 35.1 56.6 56.6 55.3 56.7 57.1 @ @ @ @ @ @ 100 92.7 91.5 80.2 94.8 92.1

49.8 53.8 54.4 55.3 54.1 52.3 54.5 54.8 55.8 50.4 @ 93 @ @ @ @ @ 100 @ 100 @ @ @ 100 99.9 89.4 99.9 99.9 99.9 99.9

52 50.2 50.1 X 51.3 43.6 50.1 53.5 54 48.8 @ @ @ @ 100 @ @ 100 @ 100 @ @ 100 99.9 99.9 93.6 99.9 99.9

30 X X X X 32.9 33.9 28.1 44 41 @11.5 @10.4 @ 9.4 @6,5 @51 @90.2

39.8 X X 45.1 45.4 46.4 @ 24 Not @24.1 @41.5 @81.9

working

(20 µm ,4 µm) (10 µm , 1 µm)

56.6 59.9 60.4 30.2 29.1 19 @ @ 100 @ @ @ @97 99.9 77.2 98.7 98.6

51.3 54.6 57.1 58.5 57.1 31.2 32.3 32.5 30.3 57.1 @ 78 @ @ @ @ @ @ @ @ @ 99.2 97.8 99.7 99.9 98.9 98.9 98.9 98.7 99.9

53.8 17.5 52.5 54.3 56.4 54.6 31 26.3 15.1 54.6 @ @ @ @ @ @ @ @ @ @ 91.4 96.5 99.9 99.9 99.3 99.9 98.8 82.1 95.7 99.9

29@ 28.9 22.8 41.7 51.5 @8.48 @ 5.1 @2,4 @21.6 @100

42.2 46.6 55.4 @18.3 @28.8 @100 Not performed

(10 µm ,2 µm) (10 µm , 3 µm)

34.9 44.6 44.2 34.9 47.4 48 @ @ @99.7 @ @ @99.9 99.4 99.8 99.4 99.9

39.8 41.4 43 43.2 41.5 42.1 43 45 45.5 44 @ @ @ @ @ @ @ @ @ @ 99.5 99.6 99.7 99.7 99.6 99.6 99.7 99.8 99.8 99.7

41.2 39 39 39.5 37.2 41.3 42.6 44.1 41.3 33.6 @ @ @ @ @ @ @ @ @ @ 99 99.6 99.4 99.4 99.5 99.3 99.6 99.7 99.7 99.6

Fig. 4.5. Wafer mapping of the common emitter current gain for different emitter finger widths (WE) and different ion-implantation distances (Wp+).

31 H.-S. LEE Chapter 4. Characterization and Results

geometrical effects on the current gain. Figure 4.5 shows wafer mapping displaying the average value of the current gain β at collector current IC of emitter finger length and different implantation distance. The current gain decreased with decreasing emitter width for the same implantation distance. This behavior, commonly referred to as the emitter size effect is caused by surface recombination that becomes more pronounced as the emitter area to periphery ratio decreases.

The influence of the implantation distance WP+ of the current gain is displayed in Fig. 4.6. Normally, the high implantation dose creates defects and causes a reduction of current gain if the implantation distance is too small. Figure 4.6. suggests that a minimum implantation distance of 2-3 µm between base implant and emitter edge is required to avoid defects in emitter region and a significant reduction of current gain.

Gain Current Highest Common emitter 35 2um 3um 4um 20 µm emitter width, implantation distance (a)

25 Common emitter Highest Current Gain 1um 2um 3um

10 µm emitter width, implantation distance (b) Fig. 4.6. Measured common emitter current gain vs distance between emitter edge and the base contact implantation for SiC BJTs with (a) 20 µm emitter width and (b) 10 µm emitter width.

32 High Power Bipolar Junction Transistors in Silicon Carbide

4.2 Material characterization

4.2.1 X-ray diffraction (XRD)

As a nondestructive method for the structure analysis, the X-ray diffraction is used for identification of phase contents and crystal orientation of the material. The X-ray diffraction can be understood by interference of waves scattered at successive planes. This interference is described by Bragg's law nλ = 2d sinθ , where θ is the diffraction angle, d is the lattice plane distance and λ is the wavelength.

To see the formation of compound phases between SiC and the metal contact, θ-2θ scans were performed before and after annealing in this work (Paper III). In this works, the XRD measurements were carried out with a Siemens D5000 equipment using a Cu-Kα source. A TiW layer was deposited by Ar magnetron sputter from a composite TiW target (ratio 30:70) with 3kW power to form a metal contact to both the emitter and the base. In order to identify the material composition in the border region between TiW and SiC, XRD θ-2θ scans were performed before and after annealing. Figure 4.7 shows the XRD spectra of as-deposited TiW on SiC. The samples were furnace annealed at 950 oC in Ar atmosphere for 30 min. As shown in Fig. 4.8, the TiW layer was consumed by chemical reaction as shown by the vanishing TiW peak after high temperature annealing. A new peak corresponding to titanium tungsten carbide was found instead after annealing. A sample for which the contact process had failed leading to a rectifying contact behavior was also used for comparison (Fig.4.9). In the previous process run (Paper II) that gave rectifying contacts, dry etching of oxide was used for opening the contact window, while a lift-off technique lead to the good contact. The differences in surface preparation before sputter deposition of TiW is a likely explanation for the large differences in contact properties. The sample with ohmic contacts shows a more pronounced formation of titanium tungsten carbide than the rectifying sample. The successful formation of an ohmic contact with TiW is believed to be due to diffusion of Si and C atoms into the TiW layer and a reaction at the interface forming titanium tungsten carbide.

33 H.-S. LEE Chapter 4. Characterization and Results

SiC(008) TiW(110) SiC(004)

Intensity (AU)

20 40 60 80 100 2θ

Fig. 4.7. X-ray diffraction spectrum of a 110 nm thick TiW on 4H-SiC before annealing.

(111)

)C 1-x SiC(004) W x (Ti

Intensity (AU)

30 35 40 45

2θ Fig. 4.9. X-ray diffraction spectrum of a 110 nm thick TiW on 4H-SiC after annealing at 950 ºC for 30 minutes in Ar ambient.

34 High Power Bipolar Junction Transistors in Silicon Carbide

SiC(004)

Intensity (A.U)

(111)

1-x

SiC (Ti,W)C

30 35 40 45 2θ Fig. 4.9. X-ray diffraction spectrum of a 110 nm thick TiW on 4H-SiC after annealing at 950 ºC for 30 minutes in Ar ambient for the non-ohmic rectifying contact.

4.2.2 Transmission Electron Microscope (TEM)

High-resolution transmission electron microscopy (HRTEM) is a powerful technique for investigating the dynamics of the reaction and the changes in material composition after contact annealing. The cross-sectional TEM image in Fig. 4.10 shows no large scale reaction between SiC and the TiW layer. However, some amorphous regions were found, containing carbon and silicon according to Energy Dispersive X-Ray Spectrometry (EDS). This means that Si and C atoms diffuse from SiC into the TiW layer. Titanium tungsten carbide regions were found by selected area electron diffraction (SAED). Titanium tungsten carbide regions were also found in the rectifying contact sample (Fig. 4.11). However, the ohmic contact samples show larger titanium tungsten carbide regions from selected area electron diffraction. This is consistent with the observation by XRD analysis.

35 H.-S. LEE Chapter 4. Characterization and Results

TiW (Ti,W)C1-x TiW

(Ti,W)C1-x (Ti,W)C1-x

A A

SiC

(a) (b) Fig. 4.10. (a) Cross section HRTEM at the interface of TiW/SiC after 30 min annealing at 950 oC (b) SAED analysis for ohmic contact sample.

(a) (b) Fig. 4.11. (a) Cross section HRTEM at the interface of TiW/SiC after 30 min annealing at 950 oC (b) SAED analys is for rectifying contact sample.

36 High Power Bipolar Junction Transistors in Silicon Carbide

4.2.3 Secondary Ion Mass Spectrometry (SIMS)

Secondary Ion Mass Spectrometry (SIMS) is a destructive method for measuring doping concentration profiles and thicknesses of epitaxial layers. A focused ion beams hit the surface of the sample to sputter secondary ions from the sample. The secondary ions are measured with a mass spectrometer to determine the quantitative elemental or isotopic composition of the surface. Figure 4.12 shows an example of the depth profile of SIMS with nitrogen concentration from N+ and N- emitter epi layers.

1020

19 -3 200 nm ND =6·10 cm N+ emitter 19 -3 400 nm ND =1.2·10 cm N emitter

P+ base

) 19 Drift region -3 10

SiC substrate

1018 Concentration (cm Concentration

17 10 05 10-7 1 10-6 1.5 10-6 2 10-6 Depth (m)

Fig. 4.12. The depth of profile of nitrogen in the two-step emitter layer using SIMS. The thickness

4.3 Electrical characterization

4.3.1 Extraction of junction temperature

Self-heating of SiC BJTs decreases the current gain with increasing power dissipation. When the BJTs are biased with a high current, the device lattice temperature and phonon scattering increase and this reduces the carrier mobility and the current gain. Different measurement techniques can be considered for investigating self-heating effects. In this work, junction temperatures and thermal resistance values were extracted from DC measurements using a method by Marsh [69].

Fig. 4.14 shows collector current IC versus the collector-emitter voltage VCE with a constant base current IB = 25 mA at the ambient temperatures 25 °C, 50 °C, and 75 °C in DC

37 H.-S. LEE Chapter 4. Characterization and Results

measurements. The negative slope of IC with increasing VCE is caused by the strong self- heating. The junction temperature Tj was extracted assuming a thermal impedance that is a linear function of the ambient temperature. The method uses three points with constant Ic and three different VCE values with the same IB at different ambient temperatures. If we have three ambient temperatures Tamb,x (x=1,2,3) and associated power dissipations, Pdiss,x, the same mean junction temperature within the devices can be described as

T j = Tamb,x + Rth,x Pdiss,x (4-1) where Rth,x is the thermal impedance and is defined by Rth,x =A+BTamb,x.

We have three unknown variables (Tj, A, B), which can be solved by three simultaneous equations.

−1 ⎛T ⎞ ⎛1 − P −T ⋅ P ⎞ ⎛T ⎞ ⎜ j ⎟ ⎜ diss,1 amb,1 diss,1 ⎟ ⎜ amb,1 ⎟ ⎜ A ⎟ = ⎜1 − Pdiss,2 −Tamb,2 ⋅ Pdiss,2 ⎟ ⋅⎜Tamb,2 ⎟ (4-2) ⎜ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ B ⎠ ⎝1 − Pdiss,3 −Tamb,3 ⋅ Pdiss,3 ⎠ ⎝Tamb,3 ⎠

Fig. 4.13 illustrates how this extraction results in two junction temperature (Tj) values of 102 °C and 78 °C, occurring at the intercepts of the measurement curves with the straight lines. The value of RTh at ambient temperature 25 °C is 19 °C/W. It should be pointed out that this RTh value includes a non-optimum thermal contact between sample and chuck.

0,12

25OC T O amb 50 C 75OC 0,10

Tj O 0,08 79 C 102OC

(A)

C I 0,06

0,04

0,02 0 20406080100 V (V) CE Fig. 4.13. DC measured collector current (IC) vs. collector-emitter voltage (VCE) including extraction of the junction temperature (Tj) at three ambient temperatures (Tamb) with identical base currents IB = 25 mA

38 High Power Bipolar Junction Transistors in Silicon Carbide

4.3.2 Linear transmission line model (LTLM)

The Linear Transmission Line Model (LTLM) was used for measurement of the ohmic contacts in this work. This technique was first proposed by Shockley [70] and further developed by Berger [71]. A schematic view of an LTLM structure is shown in Fig. 4.14.

25µm Emitter Implantation region 19 -3 20µm Peak NA≈7·10 cm 15µm Base 10µm 5µm

Z 19 -3 ND=5·10 cm 19 -3 ND=1·10 cm 17 -3 NA=3·10 cm 17 -3 NA=3·10 cm 15 -3 ND=4·10 cm + N substrate

(a) (b) Fig. 4.14. (a) A schematic view of the Linear TLM structure (b) Microscopic top view of LTLM structure.

Slope=ρs/Z 2RC

d 2L 5 10 15 20 25 T Fig. 4.15. A plot of total resistance (RT) as a function of TLM metal contact pad spacing (d).

The TLM structure was mesa etched between n+ emitter layer and p+ base layer as shown in Fig. 4.14. For contact resistance measurements, the TLM structure has to consist of three or more identical contacts on a highly doped line of pads with different distances.

39 H.-S. LEE Chapter 4. Characterization and Results

The total resistance RT can be described as

ρ d R = s + 2R (4-3) T Z C where ρs is the sheet resistance, RC is the contact resistance, d is the metal contact pad space and Z is metal pad width. The total resistance can be plotted as a function of contact pad spacing as shown in Fig. 4.15. The contact resistance RC and the sheet resistance ρs can be determined by a linear extrapolation in Fig.4.15. Finally, the specific contact resistance ρc is given by

ρs = RC LT Z (4-4)

where LT is the transfer length that it is determined as the intercept value in Fig. 4.15.

In this work (Paper III), we have examined ohmic contact formation in a SiC BJT process with sputter deposition of titanium tungsten contacts to both n-type and p-type followed by annealing at 950 oC with different annealing times: 5, 15, and 30 min. The contacts were characterized with linear transmission line method (LTLM) structures. Figure 4.16 shows the I-V curves of TiW contacts after different annealing times at 950 oC for a 5 µm contact distance for both emitter and base regions. The previous process run with rectifying contacts is also compared with ohmic contacts and does not have linear IV curves at all. The ohmic property of the p+ base contact improves dramatically between 5 and 15 min annealing, whereas the n+ emitter contact shows only little improvement after 5 minutes. After high temperature annealing at 950 oC for 30 min, the n+ emitter structure and p+ base structure contact resistance was 1.4 x 10-4 Ωcm2 and 3.7 x 10-4 Ωcm2, respectively.

120 100 5 min 100 5 min 80 10 min 80 15 min 60 30 min 60 30 min 40 40 20 20

0 120 0,0010 5 min

5 min 100 15 min -20 0,0008 80 30 min Current (mA) 10 min -20 0,0006 30 min 60 40 0,0004 Current (mA) -40 -40 20 0,0002 0

0,0000 -20 -60 -60 -0,0002 Current (mA) -40 Current (mA) -60 -80 -0,0004 -80 -80 -0,0006 -100 -0,0008 -120 -100 -100 -0,0010 -6 -4 -2 0 2 4 6 -3-2-10123 Voltage (V) -120 -120 Voltage (V) -3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3 Voltage (V) Voltage (V)

(a) (b)

Fig. 4.16. Current-voltage characteristics of 5 µm spaced n+ emitter structures for different annealing times (a) for the ohmic contact sample (b) for the non-ohmic rectifying sample. Insets show the p+ base structures for different annealing times at 950 ºC in Ar ambient.

Chapter 5

Summary and Future work This thesis deals with the fabrication and characterization of SiC Bipolar junction Transistor (BJTs) for high power applications. For the SiC BJT to become competitive with commercialized silicon based devices, it is important to achieve high current gains to reduce the power required by the drive circuit. Results including different type of BJTs and ohmic contact processing issues for bipolar transistors were presented in this thesis.

SiC Power BJTs 4H-SiC NPN BJTs were fabricated using aluminum implantation for the base contact formation and to obtain a junction termination extension. A high current gain of 64 was obtained for a 4H-SiC BJT with a breakdown voltage of 1100 V. The high current gain is attributed to high material quality obtained by a continuous epitaxial growth of the base- emitter layers. BJTs with varying geometry were characterized. High temperature electrical characterization of the 4H-SiC BJTs has been performed. The current gain at high temperature decreased 56 % at 300 °C compared to its value at 25 °C. The importance of considering self-heating effects were quantified by extracting the junction temperature in this thesis.

Ohmic contact processing issues for Bipolar Transistors For ohmic contact formation in a SiC BJT process titanium tungsten (TiW) contacts were deposited on both n-type and p-type followed by annealing at 950 oC. The contacts were characterized with linear transmission line method (LTLM) structures. To see the formation of compound phases, XRD θ-2θ scans and TEM with SAED analysis were performed. Formation of titanium tungsten carbide at the SiC/TiW interface was found as a key factor for formation of ohmic contacts although only a limited reaction between SiC and TiW was observed.

41 H.-S. LEE Chapter 5. Summary and Results

Future work For high current ( > 10 A) handling, large area devices (> 5 mm2) are required. To further improve the SiC power BJTs, some parts need much research, for example the passivation layer, the junction edge termination and ohmic contacts with low contact resistance. The thermal silicon dioxide has been preferred as a passivation layer in SiC BJTs. However, surface recombination is one of the factors which reduce the current gain even when using a thermally grown silicon dioxide. Improved passivation using state-of-the-art silicon dioxide should be considered for fabrication of passivation layers in the future. To obtain high voltage blocking capability, a junction termination extension (JTE) was used for this work. The breakdown voltage results in this works are still low compared with theoretical limitation. A better optimization using a JTE or a guard ring edge termination is needed. TiW was used as ohmic contact for both the emitter and the base regions of the SiC BJT. However, the reason why TiW in some cases did not form an ohmic contact to the highly n- doped region of SiC even after high temperature annealing needs further investigation. If we assume that TiW, due to its weak reaction with SiC, is more sensitive than other metals to the surface preparation of SiC, then argon pre-sputter before metal deposition can be an important factor for fabricating TiW ohmic contacts.

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