ELECTRICAL STUDIES OF METAL-INSULATOR-SEMICONDUCTOR STRUCTURES
by FEY LIN, B.S.
A THESIS IN PHYSICS
Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of
MASTER OF SCIENCE
August, 1988 T3
ACKNOWLEDGMENTS
I would like to express my deep gratitude to
Dr. V.K. Agarwal for his patience and very helpful
guidance in the direction of this thesis and to the
other member of my committee. Dr. R. L. Lichti, for his
helpful criticism. I also wish to thank the department
of physics for the financial support during the last two
years Also I would like to thank S. L. Buckner and R. Smith for their help. This work is a partial grant from
Texas Instrument, Inc. .
This thesis is dedicated to my parents and my
lovely wife, Bee-Min.
11 CONTENTS
ACKNOWLEDGMENTS ii
CONTENTS iii
ABSTRACT iv
LIST OF TABLES vi
LIST OF FIGURES vii
CHAPTER
I. INTRODUCTION 1
II. THEORECTICAL BACKGROUND 6 V Introduction 6 Energy-Band Diagrams When V ^ 0 8 Characteristic of Surface Space-Charge 12 Regi ons - Capacitance-Voltage Characteristics 14 Breakdown Measurement in MIS Structure 18 III. EXPERIMENTAL DETAILS 21
Introduction 21 Sample Preparation in Vacuum 21 C-V Plotter 28 Current-Voltage(Breakdown)Measurements 31 Experimental Procedure For C-V Measurement 31
IV. EXPERIMENTAL DATA AND RESULTS 37
Capacitance-Voltage Characteristics 37 Density of States Determination 43 Current-Voltage Characteristics 45
V. DISCUSSION AND CONCLUSION 54
Analysis of C-V Data 54 Analysis of I-V Data 57 Thickness Dependence Behavior of Breakdown Fields 58
LIST OF REFERENCES 61
iii ABSTRACT
The capacitance-voltage( C-V) measurements at high frequency in metal-insulator-semiconductor ( MIS) structures provide important information about the interfacial parameters. The C-V characteristic measurements on MIS structures are reported in which silicon is used as the host semiconductor, and evaporated films of fatty acid as the insulator. The data are compared with devices con-taining Si02 on Si.
It must be remarked here that II-VI and III-V group semiconductors lack the native oxide la- yer, and the purpose of this experimental studies is to assess the potential use of fatty acid film as insulator with these semiconductors. The d. c. dielectric breakdown properties and current-voltage measurements also have been investigated.
This work shows that thermally evaporated stearic acid films can be potential substitues as insulating layers in MIS devices. The magnitude of interface density of states are comparable in MIS structures containing only Si02 + fatty acid films. However, we have observed some unusual C-V characteristics on p-type silicon substrates, i.e., there is inversion under
1 v negative bias conditions which implies as if p-type surface is inverted to n-type. The fatty acid films
also have lower dielectric strengths than Si02. LIST OF TABLES
1. Experimental conditions and calculated results on density of states 48
2. Summaries of I-V data with initial breakdown voltage under different thicknesses for both Si02 and stearic acid films 53
3. Summaries of earlier works on films vs thickness 59
VI LIST OF FIGURES
1. Metal-Insulator-Semiconductor (MIS) structure
2. Energy-band diagram of ideal MIS structures at V = 0 (a) n-type semiconductor ( b) p-type semiconductor
Energy-band diagram for ideal MIS when V ?* 0, for the following cases : (a) accumulation (b) depletion (c) inversion 10
Band diagram with V ?* 0 for p-type semiconductor MIS structure 1 3
5. Schematic diagram showing the relative position of various elements inside the vacuum chamber 23
6. Sketch of the substrate holder and masks 25
7. Sketch of the evaporating sources 26
8. Top and side views of test specimens 27
9. Block diagram of C-V plotter 29
10. Sketch of the C-V probe assembly 30
11. Sketch of model 44-M probe 32
12. Sketch of the testing contact 33
13. Test circuit of current-voltage measurenent 34
1 4 Test circuit of capacitance-voltage measurement 36
1 5 C-V characteristics: n-type Si-Si02-Al with film thickness 700A, contact area 2. 35 mm , ramp rate 80mV/sec under zero bias voltage 38
1 6, C-V characteristics: n-type Si-Si02-Al with film thickness 700A, contact area 1. 34 mm , ramp rate 80mV/sec und^r zero bias voltage 39
17. C-V characteristics: n-type^ Si-Si02-Al with oxide ^film thickness 461A, contact area 2. 57mm , ramp rate 80mV/sec 41
VI 1 18. C-V characteristics: p-type Si-SiO2-Stearic acid-2 Al with film thickness 441^, contact area 1.33 mm , ramp rate 80mV/sec under zero bias voltage 42
19. same sample as in Figure 18, (a) i nvert plot (b) retrace plot 44
20. C-V curve exhibiting voltage shift for on p-type Si-Si02-stearic acid-AKfilm thickness 44lA) curve A : no bias stressing curve B : following the bias stressing of 15 V for 20 minutes 46
21. C-V curve exhibiting voltage shift for n-type Si- Si02-tlrfilm thickness 70ot) curve A : no bias stressing curve B : following the bias stressing of 50 V for 5 minutes 47
22 I-V characteristics for Si-Si02-Al structures^ with film thickness 461S, contact area 1.57mm and ramp rate .47V/sec 50
23. I-V characteristic of Si-Si02-stear1c acid-Al ^ with film thickness 441A, contact area 1. 33mm , and ramp rate . 47V/sec 51
24 I-V characteristic of Si-SiO2-Stearic acid-Al with film thickness 500X, contact area 1. 33 mm and ramp rate . 39V/sec 52
VI 11 CHAPTER I
INTRODUCTION
Metal-insulator-semiconductor (MIS) structures have been studied extensively over the past few decades.
The study of the electrical bahavior of MIS devices is of great importance in the understanding of the physical features such as the nature of the interfacial characteristics between the semiconductor and the insulator. Due to the availability of natural oxide of silicon, SiO and Si02» the MIS structures containing oxides as insulators over silicon have been studied most extensively. In the case of other semiconductor host systems from the II-VI and III-V groups, the lack of a natural oxide has led to the use of insulating films of other oxides, nitrides, etc. In this thesis, the structure which contains only on oxide layer is referred to as Metal-Oxide-Semiconductor( MOS) and the structure which contains a very thin native oxide plus fatty acid insulating layer is referred to as Metal-Insulator-
Semi conductor( MIS) .
Typically, the deposition of insulating films such as oxides and nitrides require the use of processes involving high temperature and/or the use of energetic particles which create a large density of surface states on the host material. This problem can be alleviated by the use of alternative insulating films. As an example, one can use lower melting point organic materials such as stearic acid as the insulating layer. Typically, there are two methods to grow the fatty acid films.
The first method involves deposition by the dipping method due to Langmuir and Blodgett (1) and the other is thermal evaporation under vacuum.
The motivation for the present work originated from the fact that fatty acids can be thermally evaporated at relatively low temperatures without inducing appreciable surface states on the host semiconductor.
Additionally, a thermally grown fatty acid films can be washed off easily which allows the use of host semiconductor over and over. This may lead to significant materials saving particularly in the characterization phase of device research.
This experimental study is an investigation of the thermally grown fatty acid films as the insulating barrier. Althrough we have studied only the thermally grown fatty acid films, it is more common to deposit fatty acid films by the Langmuir-Blodgett( LB) technique.
This technique involves the spreading of a floating monolayer on a clean water surface which is then transfered onto substrate by repeated excursions of the substrate through water surface. The LB technique allows layer-by-layer film growth with known film thicknesses, uniformity and relatively very low density of pinholes. However we chose to investigate themally evaporated stearic acid films for the following reasons; they are easy to deposit in the labortary using conventional vacuum systems, which can be easily integrated with processes used in semiconductor device industry. Furthermore, this process does not require dipping the host semiconductor in and out of water, a key element in the L-B process causing some concern among semiconductor device researchers.
First we investigate the capacitance vsrsus vol tage, C-V, characteristics of the aluminum-silicon dioxide-silicon structures. Special attention is paid to the flat band voltage shift and charge storage in materials like silicon dioxide. The reason for using these samples is that the silicon-silicon dioxide system has become a well characterized interface. A detailed understanding of many of its features is still lacking, but the empirical knowledge of this interface and the ability to control its properties are quite extensive.
In fact, the experimental characteristic of aluminum- silicon dioxide-silicon structures fabricated by thermal oxidation, including a low-temperature annealing step, follow the theorectical curve very closely (2).
In the present work, two types of Si substrates have been used; those having a natural oxide layerC-25A) were used to make metal-oxide-stearic acid structures, and the ones with thicker oxide(several hundred
Angstrons) were used with no stearic acid film for compar 1 son, C-V plots are obtained on both types of struct ures.
Finally dielectric breakdown of MIS stuctures is
discussed. It is important to realize that the breakdown strength is an important characteristic of thin insulating films, A stable thin film capacitor with high breakdown fields requires a continuous, homogeneous dielectric film and suitable electrodes. The breakdown characteristics are also influenced by the substrate, insulator materials, film thickness range, film deposition process and testing method, In producing silicon-oxide, extremely high temperature
(about 950° C ) is necessary. This in turn leads to surface degradation of host semiconductor due to the formation of donor-like states at the interface To overcome these difficulties, we have used stearic acid films grown by thermal evaporation in vacuum requirinq relatively low temperature( 3) , Such films are known to have reasonably high breakdown fields, particularly after they are annealed electrically or thermally.
The general theoretical background for MIS device structures is reviewed in chapter two. Chapter three explains our experimental procedures. The experimental results are discussed in chapter four. Finally, chapter five includes the discussion and interpretation of experimental results. CHAPTER II
THEORECTICAL BACKGROUND
Int roducti on
The MIS structure was first proposed as a voltage- variable capacitor in 1959 by Moll(3) and by Pfann and
Garrett( 4) , The MIS diode was first employed in the study of a thermally oxidized silicon surface by
TermanC 5) and by Lehovec and Slobodskoy ( 6), We start discussion with an ideal MIS structure as shown in
Figure 1 where d is the insulator thickness and V is the applied voltage on the metal plate.
An ideal MIS structure is defined as follows.
(A) At zero applied biasCV = 0), the energy difference
®ms between the metal work function 0^, and the semiconductor work function Og* is zero. The work function is the minimum energy necessary for an electron to escape into vacuum from an initial energy at the
Fermi level. ( B) The only charges that can exist in the structure under any biasing conditions are those in the semiconductor and those with the equal but opposite sign on the insulator. (C) There is no carrier transport through the insulator under dc biasing conditions, i.e.. the resistivity of the insulator is infinite. The V D 0 METAL INSULATOR 1 7VTTr7~TT77 ^ SEMICONDUCTOR /
Figure 1 Metal-Insulator-Semiconductor ( MIS) r. trucl. ure 8 energy-band diagram of an ideal MIS structure for V = 0 is shown in Figures 2a and 2b for n-type and p-type semiconductors, respectively. Eg is the band gap, 05 is the potential barrier between the metal and the insulator, q is the electron charge, 0^ is the metal work function, d is the insulator thickness, E^ is the energy level in conduction band, Ey is the energy level in valence band, Ep is the Fermi level, E^ is the intrinsic Fermi level, X is the semiconductor electron affinity, X^ is the insulator electron affinity, and
^eis the potential difference between the Fermi level Ep and the intrinsic Fermi level E^. The ideal MIS theory discussed here serves as a basis for understanding practical MIS structures and for exploring the physics of semiconductor surfaces.
Enerq.y-Band Pi aqrams When X £0.
When an ideal MIS structure is biased with positive or negative voltages, basically three cases may exist at the semiconductor surface (Figure 3).
We consider the p-type semiconductor first. When a negative voltage is applied to the metal plate, the top of the valence band bends upward and is close to the
Fermi level (Figure 3a). For an ideal MIS structure, no .3> CI rr- \
> cr Q) to D< I dJ >v u -P 3 1 U +> P4 > 0 S: 3 ..-^ CO ^1 jO N: 4J >..^ Ul X u C/5 0 h-l -p 0 tsx I :z —( T) ^c cd C GD 0 TJ oTil l •H
<+-< ID 0 U] E 0;
P-type n-typo
— ^c 'mnv. —% V > 0 — - :z, < 0 — E, Cn) W7/ r .^F + + •> -I- -I- -i-
Cc OT7/ V < 0 E V > 0 1 (b) W77; H1- + 4- •Xd
(c) V << 0 •" E C
>> 0 - Ei E7 E Ey + -h+jt + + 4- f Xd,max
Figure 3 : Energy-band diagram for ideal MIS when V j* 0, for the following cases : (a) accumulation (b) depletion (c) inversion 11 current flows in the structure: therefore, the Fermi level remains constant in the semiconductor. Since the carrier density depends exponentially on the energy difference (Ep - Ey). this band bending causes an accumulation of majority carriers (holes) near the semiconductor surface. This is the "accumulation" case.
When a small positive voltage(V>0) is applied, the bands bend downward and the majority carriers are depleted
(Figure 3b). This is the "depletion" case. When a larger positive yoltage is applied, the bands bend further downward so that the intrinsic level E^ at the surface crosses over the Fermi level Ep (Figure 3c), At this point the number of electrons (minority carriers) at the surface is larger than that of the holes and the surface is thus inverted. This is the "inversion" case.
In the case of an n-type semiconductor, with the polarity of voltages reversed, the same sequence of events take place. With a positive gate voltage the majority carriers (electrons) accumulate at the surface making the semiconductor more n-type. With a negative ga te voltage, a depletion layer is formed as electrons are pushed back from the surface. At inversion, the depletion layer reaches a maximum width. Any further increase in gate bias is balanced by the inversion layer charge, which consist of mobile holes 1 2
Characteristics of Surface Space-Charge Regi ons
We consider ideal semiconductor devices with the implicit assumption that the surface effects often completely dominate the characteristics of the device.
We will consider these surface effects in some detail.
Surface effects on p-n junctions are primarily due to the fact that ionic charges outside the semiconductor surface will induce an image charge in the semiconductor and thereby lead to the formation of surface space- charge regions. If a surface space-charge region is formed, it will modify the junction space-charge region and can lead to changes in the junction characterictics.
Figure 4 shows a more detailed band diagram at the surface of a p-type semiconductor.
In the equilibrium case of a metal-insulator- semiconductor structure, no dc current flow is possible across the space-charge region. This is because any such current flow would have to go through the insulator which has an infinite resistance in the ideal case.
Thus the system will be under thermal equilibrium i.e., np = ni where n is the electron concentration, p is the hole concentration, and n^ is the intrinsic carr ier density. The Fermi level will be constant throughout the surface space-charge region. 1 3
OXIDE P-TYPE SEMICONDUCTOR J i :L
_Ec (a) __Ep accumulation '+ t t + t \ V HOLES
(b) depletion •r-r Ev ACCEPTOR IONS
ELECTRON: — ^c (c) 1^ i^-i
inversion /^tt-t-t-t-
Figure 4 Band diagram with V ^^ 0 for p-type semiconductor MIS structure 14
Figure 4(a) shows the condition corresponding to a negative voltage applied to the metal gate. This negative potential will attract positive charge in the semiconductor, which in the case of a p-type semiconductor will consist of a region of accumulation of holes near the insulator-semiconductor interface.
Figure 4(b) shows that if a small positive voltage is applied to the gate, a negative charge will be induced in the semiconductor. This is due to holes being pushed away from the interface, leaving behind a depletion region consisting of uncompensated acceptor ions.
Figure 4(c) shows that if a larger positive voltage is applied to the gate, a narrow region is formed with the minority carriers (electrons) in the inversion regi on.
Capacitance-Voltaqe Characteristies
If we deal with an ideal MIS structure, charges in the system will be neutralized. Thus, QM = ^n "•" ^N/^W =
Qs and V = Vj^ + ©g where Q^, Q^ and Qg represent charges per unit area on the metal, the electrons per unit area in the inversion region, and the total charges per unit area in semiconductor, respectively. The term QN^^W represents the density of ionized acceptors per unit 1 5 area of space-charge region with space-charge width W and N^ being the number density of acceptors. V is the applied voltage, and Vj^ and 0s are the potential variation across the insulator and semiconductor, respectively. According to Gauss's Law and Poisson's equation, the electric displacement is continuous at the interface; thus, the total capacitance per unit area C of the MIS structure is given by
C( total) = F/cm'
This represents the series combination of insulator capacitance per unit area, Cj^, and the capacitance per unit area of the surface-charge region, Cg, in the semiconductor. In our laboratory the C-V measurement system allows high frequency (1 MH2) measurements.
When a positive voltage is applied to the MIS structure, it will induce more negative charge in the semiconductor. For a p-type semiconductor, the holes will come out from the semiconductor surface and the width of the depletion region increases a little The increase is proportional to the drop in the capacitance. For low frequency measurements the capacitance, both inversion and accumulation bias, is 16 almost equal to the capacitance of the insulator, The capacitance starts out at a maximum at accumulation and drops in depletion. However, when the inversion condition is reached, the inversion layer can actually alter its charge at the same rate as the ac signal.
Since the signal frequency is low and the inversion layer physically resides at the oxide-semiconductor interface, the oxide capacitance and the total capacitance increases again to the maximum value. The reason for this is that the gate charge fluctuates slowly enough and the inversion charge can follow the variation directly for the low frequency 10-100 Hz range. In this case, a definition for low-frequency is one for which the inversion-layer charge can be increased or decreased at the same rate as the small ac signal on the gate. On the other hand, if the measurement frequency is high ,then there is a sheet layer of charge at the oxide-semiconductor interface in the inversion region, but the ac fluctuation of the gate charge occurs at a high enough rate that only the widening and narrowing of the depletion layer can follow the charge fluctuation. In the capacitance versus applied bias measurement, the frequency used must be high enough such that the thermal generation of carriers cannot follow the gate voltage variation. The high- 1 7 frequency capacitance-voltage measurement for a MIS structure is normally divided into three regions; accumulation, depletion and inversion.
When the MIS structure is in the accumulation phase, the measured total capacitance is
C ( Accumulation ) = C
where Cj^ is the insulator capacitance. In depletion region, the capacitance drops with increasing gate voltage. Thus, the total capacitance is a series combination of insulator capacitance and semiconductor capaci tance.
C '' ( Depletion ) = ( C^ ) ^ + ( Cg ) ^
where Cj^ = Ki ^ / x^ is the capacitance per unit area in the insulator and Cg = Kg ^/x^ is the capacitance per unit area of space-charge region in the semiconductor. Xi, Ki, Kg, and ^ represent the thickness of insulator, dielectric constant of insulator, dielectric constant of semiconductor and permittivity of free space, respectively. It is nece ssary to consider the effect of depletion-layer width x^ adjacent to the insulator/semi conduct or 1 8 interface and the insulator thickness x^. The depletion capacitance decreases as the dc bias is changed from the
flat band to the onset of inversion. The depletion
biasing and x^ also increase. Therefore, the capacitance in depletion bias is analogous to two
parallel plate capacitors (C^ and Cg) in series,
and
C j_ Cg C( deplet i on) = Ci+Cg ^^ KiXd/KgXi
In inversion region, the capacitance remains at a
constant minimum value and x^j reaches maximum value once
inversion is reached.
Breakdown Measurement i n MIS St ruet ure
There are many likely practical applications of
using different organic materials as insulators in MIS structures. Therefore dielectric breakdown of organic
insulating films has been of great interest for many years. In order to know the breakdown characteristics of MIS structures, we have used current - voltaae measurem ents to determine the nature of the breakdown mechanism. There are several ways of describing the dielectric strength of thin insulating films The following three methods (8) have received special 1 9 at tent i on (A) determining the current - voltage characteristics of a capacitor, with particular attention just prior to the breakdown event, ( B) using a large number of test data and observe the statistical distribution of breakdown values. ; and ( C) testing MIS structure with very thin metal electrodes in order to allow self-healing breakdown measurements.
Although electrical breakdown in thin films and bulk solids has been observed for past few years, breakdown mechanisms are still an active subject of investigation, both in semiconductor and in insulators.
Among others Forlani-Minnaja(9) and Klein(10) have independently - developed theories of breakdown in dielectric thin films relating the breakdown field and film thickness. Osburn and Ormond ( 11 ) have studied the electric breakdown strength of thermally grown Si02 films in the thickness range useful for MOSFET applications. The dielectric breakdown properties of thermally grown Si02 may vary depending on the properties of the film, applied bias voltage, instrument impedance, metallurgical contact thickness. oxide thickness, capacitor area and ramping time The breakdown model due to O'Dwyer (12-13) relates the breakdown field to the power-dependent function of the dielectric film thickness d. Our major goal has been to 20 use thermal evaporation method to produce stearic acid film and to compare the results with Si02 film. Tn the case of stearic acid thin films. the pre-and post- breakdown studies have been carried out on both the thermally evaporated films and those grown by the L-B technique The current-voltage characteristics investigated by Agarwal and Huang(14) indicate that the breakdown field of stearic acid films is thickness depende nt The breakdown field F has an inverse relationship with the thickness of thin film. The power law used in this case is F « d . where a i'3 0.8 and
1.3 for -thermally evaporated films in the thickness ranges of 60 - 200 nm and 18-60 nm, res pec t i ve 1 y( 1 4) . CHAPTER III
EXPERIMENTAL DETAILS
Introduction
A discussion of the experimental details of this study is included in this chapter. The first section discusses the sample preparation by thermal deposition using a vacuum system and experimental set-up. The specific experimental procedures used to take the data are covered in this section. A schematic of the system is also shown. The second section describes the capacitance-voltage plotter and its function. Finally, a brief discussion of the current - voltage breakdown measurement is included in the next section. Detailed data analysis procedures are presented in the next chapter.
Sample Preparat i on i_n. Vacuum
The metal-oxide-semi conduct or samples were fabricated on n-type, < 1 00>-orientation silicon wafers.
The wafers already had a film of silicon dioxide grown at about 1000° C in dry oxygen. The silicon-silicon dioxide substrates were cleaned and polished with distilled methanol in an ultrasonic cleaner. Finally,
21 ^ 22 the samples were washed thoroughly with distilled methanol and transferred to a vacuum system (=10
Torr) . In this vacuum chamber( Figure 5) we prepared two kinds of samples. In one, aluminum was evaporated directly on to oxide coating thus fabricating Si-Si02-Al structure. In the other a certain thickness of stearic acid insulator film was deposited prior to the top aluminum electrode. Thus these structures had double insulating layer (Si02 + fatty acid) The fabricated structures were stored in a dessicator. The electrode were deposited by vacuum evaporation at a rate of about
2-5 A per second. For electrode deposition, a special m ask was used with different size holes punched in it In the case of structures with stearic acid film, the vacuum chamber had to be opened to place the mask following stearic acid film deposition. Figure 6 shows the schematic of the mask used to deposit the top aluminum electrode. The deposition rate of stearic acid is also about 2-5 A per second. The substrate was cooled down by the coolant line during deposition.
During the electrode and film deposition, the temperature of the substrate was maintained below the melting point of stearic acid. In order to monitor the temperature of the substrate and the stearic acid source during the deposition, an Omega Digital 23
18 INCHES BELL JAR
.^,E;:.SOR HEAD
(for thickness COOLING LINE do 1. V. rrrii nn 11 on)
SHUTTER SUBSTRATE HOLDER
MASK
SOURCE
VACUUM SYSTEM
Figure 5 Schematic diagram showing the relative position of various elements inside the vacuum chamber 24
Temperature Indicator( model-400B) and Copper-Constantan
thermocouple were used. The film thickness was monitored by
a quartz crystal monitor( Sloan Digital Thickness Monitor,
model DTM-200) . It consists of two major components : a
sensor head and a digital display measurement unit. The
sensor head( Figure 5) consists of a crystal holder and an
electric oscillator, housed in a stainless steel case. The
crystal is mounted so that it can be exposed directly to the
vapor stream from the deposition source. The thickness
measurements are made by determining the change in frequency
that results from the addition of mass to the crystal. In
order to avoid overheating of the sensor head, this was
water cooled. This resulted in the stabilization of the
frequency change of the quartz crystal. Figure 6 shows the
sketch of the substrate holder and masks. The value for the
capacitance is determined by the size of the upper
electrode, which is determined by the size of the holes in
the mask. The diameter of the holes in the mask are not
uniform; therefore, several samples of differing capacitance
values are produced. The high purity aluminum wire was evaporated from a
tungsten boat( Figure 7A) . Aluminum was chosen because of
its relatively low melting point(660 C) and good adhesion
properties with stearic acid films. The stearic acid was evaporated using a tantalum boat with a cover(Figure 7B).
Figure 8 shows the schematics of planar and cross section
views of the device structures. 25
SUBSTRATE METAL PLATE
CYLINDRICAL HOLE
—r SCREW FRONT VIEW
SCREV]
MASK CROSS SECTION VIEW
MASK A MASK B
/
oo OO
t> o O O oo
TOP VIEW
Figure G : Sketch of the substrate holder and maskis 26
Figure 7 : Sketch of the evaporating sources •7.1
ww:. TRST J n;;en ON
TOP VIEW
TOP ELECTRODE
TTTTTTTTnT/rmiTT: DIELECTRIC LAYER BOTTOM ELECTRODE SIDE VIEW
TOP ELECTRODE
DIELECTRIC LAYER
SUBSTRATE
SIDE VIEW (1)
Figure 8 : Top and si do views of 1: est specimens 28
C-V Plotter
The model 410 C-V plotter(Micromanipulator Company,
Inc.) is a versatile unit specially designed for measuring various properties of semiconductor devices and materials. It provides accurate capacitance and conductance measurements as a function of applied bias voltage for MIS and MOS structures. The C-V plotter employs a 1 MH2 frequency, 1 5 mV sinewave capacitance meter and a variable d, c. ramp generator for bias voltage stressing. The block diagram of this C-V plotter is shown in Figure 9, The C-V plotter can be used for capacitance measurements in the range from
0.5 pf to 200 pf(at 25°C + 2°C) with an accuracy of 2% of reading. The' recorder output is 10 V full-scale and the resistance is 300 ohm. The ramp generator has an output voltage range from +1 V to +100 V with current limit of +10 mA maximum. The ramping rate is adjustable from zero to 500 mV/s times ramp multiplier setting which has a scale from 1 to 10 and the recorder output is +10 V full scale. The stress voltage range is from zero to +100 V with a resolution of 0, 2 V and the operating temperature range is from 15 C to 45 C.
In order to have better capacitance measurements of the sample, a special probe assembly( Figure 10) was used to make a better contact with the gate region on 29
PROBE MIS INPUT i^y WAFER
MODEL 410 C-V \ PLOTTER Y CHUCK €)
o RECORDER OUTPUT ^ DRIVE 1 M Hz SINE WAVE • I I
:(
Figure 9 : Block diagra m o f C-V plotter 30
o r-i
•^ 2: 0 (X H 0 E- td U J W CQ Z < Z u 0c J < w z > E 0 »-' (D in O pc; "LQ w H O od Q) •J XI PQ w o u<: o ^^ o ft > < I
Z 1=5 Q) -C •P CO ^-^ 0 +j Q) CO Q) u •H 31 the test wafer. Figure 11 shows a sketch of the 44-M probe. The point radius of this probe is 0.5 microns. The probe which contains the electrical connection to the C-V plotter input connector is a removable assembly that allows the investigator to change the sample or adjust the contact area on the test wafer, In operation, the coaxial cables were used 1 n interconnecting the Model 410 and the device under test to minimize stray capacitance and series inductance. Current-Voltage( Breakdown) Measurements For current-voltage measurements, the samples were placed in contact with the sample holder using conducting silver paste( Figure 12). The contact resistance was small compared to that of the sample resistance. The block diagram of the experimental set up for the I-V breakdown measurement is shown in Figure 1 3 The d,c. breakdown tester capable of supplying a maximum of 87 volts and 8 mA was used in these tests. The d, c. voltage and current were measured with the aid of a X-Y Recorder(Houston Instrument, model-100). Experi ment al Procedure For C-V Measurement The basic idea of capacitance-voltage cha racteristic was to observe the capacitance change as 32 Fi gure 11 Sketch of model 44-M probe 33 ALUMINUM CHUCK (1) TESTING SAMPLE HOLDER TOP ELECTRODE SILVER PASTE DIELECTRIC LAYER BOTTOM ELECTRODE (2) TESTING CONTACT Figure 12 : Sketch of the testing contact 34 X-Y V SAMPLE X-Y R V Figure 13 : Test circuit of current-voltage measurement 35 a function of bias voltage. Figure 14 shows the test circuit of C-V measurement in a MIS device. In this study, the test wafer was put on metalli c chuck( aluminum) with a good electrical contact between the test wafer substrate and the chuck, A 44-M probe assembly makes contact with the gate region on the test wafer. The 15 mV rms 1 MH2 drive signal is applied to the substrate. The input signal to the C-V plotter is taken from the gate. The system was connected with a X-Y recorder(Model 100 by Houston Instrument). The X-axis corresponds to the voltage and Y-axis corresponds to the capacitance signal. For the purpose of monitoring device capacitance-voltage characteristics, a Digital Mul timeter-Counter was added. The multimeter is capable of 3 measuring voltage up to 10 volt and current down to 10 ampere range. 36 Y AXIS X AXIS INPUT INPUT MULTIMETER -COUNTER MODEL 410 X-Y RECORDER INPUT DRIVE Q GATP SUBSTRATE DEVICE UNDER TEST Figure 14 : Test circuit of capacitance-voltage measurement CHAPTER IV EXPERIMENTAL DATA AND RESULTS Capacitance-Voltaqe Characteristi cs MIS structures with stearic acid film thickness ranging from 461-700? have been tested for C-V characteristics measurements. In these experiments, we have used two different kinds of MIt structures; one with silicon dioxide only and the other with silicon dioxide and stearic acid. Typical C-V characteristics for the Si-Si02-Al structures are shown in Figures 15 and 16, Figure 15 shows typical C-V characteristic curves on a test sample with an oxide film of thickness about 70oX on n-type silicon substrate. The contact area of this sample is about 2,35 mm' The bottom figure shows the C-V curve by applying voltages from -6 to +6 volts with ramp generator and the upper figure shows the C-V curve with retrace switch pushed. Figure 16 shows the C-V curves on the same semiconductor substrate and dielectric film but with a 2 different contact area which is about 1,34 mm , The C-V curve on the top represents data when the sample was ramped from -6 to +6 volts with retrace switch pushed 37 38 D. o c ^( 0 300 • a P. (d O 200 1 00. + 4 +6 C.4 p. w 400 voltage(volts) o0) c (0 o 300 200 ill ij :i_ »•_— ^•_^ 1 00 • -6 -4 -2 0 + •2 +4 ^-6 voltage(volts) Fi gure 15 C-V characteristics: n-type Si-Si02-Al with film thickness 700A, contact area 2. 35 mm"^, ramp rate 80mV/sec under zero bias voltage 39 r ^00 p. Q> fj C (0 300 o D. nJ O 200 100 + 2 + 4 +6 voltage(volts) a 400 0) a c (0 .r.. 3 0 0- o CO D. o 200- 1 00 - D -4 -2 0 + 2 + 4 + n voltage(volts) Fi gure 16 C-V characteristics: n-type Si-Si02-Al with film thickness 700^, contact area 1.34mm , ramp rate 80mV/sec under zero bias voltage 40 and the bottom curve shows when it was ramped from -6 to +6 volts only in forward direction. In order to make a meaningful comparison and appreciate the C-V characteristics on these MIS structures, the ramp voltages and ramp rate were maintained in the same range repeatedly. Figure 17 shows the C-V curve on another n- type Si-Si02-Al structure with a different Si02 thickness about 461? and 2 contact area about 2. 57 mm . The top one was taken following ramping from -6 to +6 volts with retrace switch pushed. The lower one was taken following ramping from -6 to +6 volts only in forward direction. MIS structures with stearic acid and Si02 films were also studied in this study. Figure 18 shows C-V characteristic on one of such test specimens fabricated on a p-type silicon substrate. This substrate had a natural oxide(Si02) layer of ^bout 25A thickness on top of which stearic acid film with a thickneps of about 441 A was evaporated. The contact area of the test specimen was - 1.33 mm 2 . The lower curve was the first regular C-V plot and the top one is just the repeat plot to check reproducibility. It was found that the C-V plots for structures containing stearic acid film are not as smooth as the ones without stearic acid(e.g. , Figures 15-17). The results are discussed 41 **••• •••• •••,•-•..*»...',_, .t»», * ' • ' • 1 • .V : • _ . I : ~ ,' '*".'.":•• c^ 300 p. Q) * • ' 1 . O c ' . . • ... OJ .200 . ...,.* , ••••* , ^ ... , ^^^^.^ .-:.;-...... ;.,. ...;...:...• . .^...... __..•-.:..- . ac i p. (d o • 1 • . . • 1 ' ' : ' ' * * 1 00 • ' . ' ...... ^ .*..•. . , • . • • • < -4 -6 -2 0 + 2 ' +4 +6 Voltage(volts) p. 0) o c (0 200 . •'.. o (d P. (d o 1 00 I • : : I = i '. : I , ..L-.I..-„.l ! ' = ! i ; i_' L-L:. . ! : i . ! I :•-;—rT~r"T'i •• ': : : -6 -4 -2 0 +2 +4 +6 voltage(volts) Figure 17 : C-V characteristics: n-type Si-Si02-Al with film thickness 46lX, contact area 2. 57 mm , ramp rate 80mV/sec 42 — .u - voltage(volts) , ...... I. • . • • •...;. • • ., • 1 . * ' p. 0) o 150- •. • • - . c • . •••. ' • ' • • • 1 o (d ' • "." "l '^ • ' ••••-;-• -•• - pu ' • • • * ....-• • ^ . •.• . « . - • (d 1 00 • ; , • ' ' ' ! ' u • / I ' . • ^ * v-;;; .\ . ;. r • .: • i • : " '. : • ' \ \ ' • • • \ •• I ' • / 50- ••T--r-:--;-rr:--tr-rT"":'.';--^ i ; i ! i M i • ' • • ; : • r • : • 1 • ' : • \ \ \ ' ' \ • . • : ' •• • ! • ' 1 : • 1 • i • -6 -4 -2 0 + 2 + 4 + 6 voltage(volts) Fi gure 18 C-V characteristics: p-type Si-Si02- stearic acid-Al with film thickness 441A, contact area 1.33 mm , ramp rate 80mV/sec under zero bias voltage 43 in the next chapter. Figure 19 shows two more C-V curves for the same stearic acid MIS structure. The top one is an invert plot when voltage was ramped from +6 to -6 volts and the lower one is with the retrace switch pushed. D e n s i t v of States Determi nati on The density of states, N, between semiconductor and insulator surface can be determined simply by noting the voltage shift of the measured C-V characteristic caused by the bias stressing of the device structure(17). The parallel shift of the C-V characteristic is related to the density of states and -2 the unit of N used is cm for a very thin capacitor. Thus, for the given measured V and an insulator thickness, the density of states can be calculated as follows: N = Co K I AV qd whe re -2 -1 N = density of states, cm eV permitivity of free space, -1 2 -1 -1 8.85x10 coulomb volt m 44 CM 1 50 P. i : .i._l._L..Lj.. • i I l-i^liJ-^ t t I i I I ' - • I ! O c I i , » I . • ; • ' . _ ; (d 4J •-—'(a) invert plot-—' •H 00. O (d a rt) o 50. • +2 • +4 •»-6 - .. .' . vol t age( vol ts) .'•• (b) retrace plot voltage(volts) Fi gure 19 : same sample as in Figure 18, (a) invert plot (b) retrace plot 45 Ki = insulator dielectric constant (3.8 for silicon dioxide and 2.6 for stearic acid) q = electronic charge, 1.6x10 -1 9 coulomb d = insulator thickness, m . Figure 20 shows the typical C-V plot on the Si- Si02-stearic acid-Al samples when this was bias stressed. A bias stress of 15 volts was applied for 20 minutes. Note the parallel shift of about .125 volts in the C-V characteristic. Figure 21 also shows the typical C-V plot on the Si-Si02-Al sample when this was bias stressed. A bias stress of 50 volts was applied for 5 minutes. Note the parallel shift of about . 224 volts in the C-V characteristic. Table 1 shows the typical calculated values of N for structures containing both the stearic acid and silicon dioxide films, and only silicon dioxide film. Current-Voltage Characteristics The current- voltage( I - V) characteristics of the MIS test samples with film thickness ranging from 441A-700A have been tested for d. c. breakdown behavior. The I-V curve of a device with only Si02 film ( film thickness of about 700A) shows an initial current in the /i A range until the applied voltage reaches a critical value At this voltage, the current increase rapidly by 2-3 orders 46 to 4J l-« • o Q; > a >> > • + a> D^ 1 ..^ in (C P.o< T- .*J r- l-l C «* CM o o «* o > L. tn D» O CO c • ^ CM 0) •H + c CO 4-> .:!^ CO CM o 0) •H •H L. .c £ 4J CO 4J CO (d • CN td •H c •H 4- 4-> CM •M £i rH NM' CO 0 rH CO 0) > < 0) 1 (.4 Dt-a 4-> c •H CO D» •H O c 4J (d CO •H •H (d s • o .O o •H o •H •H ia iH (0 JC L^ rH OJ X (d 0 0 4J 0 0) c CM 3 c 0) CO ,, . . -M > 1 E LI CM< (Q • OJ 3 O O 1 O •M Q) 0) (N to > > > 1 l^ C L. 1 •M 3 3 0 u tn O U CM ^ O 1 CM - (U U D tD •H Cr, VD * 1 o o o in o in (jd )aouHq Toedeo 47 •H tn > Q) p. 0 in CM n-t y 0 olts ) > (.4 D 0 c CM ID ge ( m + if t res i .It a 0 4-> > CO CO ^ a> ^f^S CO ^' 01 o< D> (d (d 0 C •iH jj 0 •iH ja CQ i-H rv CO 0 CO 0) > CO Q) J: CO L. .p en 0) 4.^ 4. c c CO o» •H M c 4-> 0 CO •M •fi •H (d 3 JQ JZ •M 0 •H 4J JQ rH x: rH CO 0 X E 0 0 a> (U rH C CM 4-> •M 3 (U CM , , .. C > U, •H u t-{ < CQ E 3 *i 0 1 0) 0) in (N 1 CM > > 1 > 0 (.4 i^ u 1 •PH 3 3 0 0 to 0 U CM CM I L. o 0 0 o I 0 0 o o CO CN (jd )aouB:j loedeo 48 1 CO 4-) r-i 'E 3 O CO O O 3 CV] rH > CO 3 O iH (d o T3 c cd CO c 0 •H CO .*J IZ o CO f-H o o te CN3 CS] rH CM CrI E E o O l-i o E- E E TH This voltage is identified as the "initial breakdown voltage." Figure 22 shows a typical I-V characteristic on a test specimen with oxide film thickness of about 461A. The data was taken after the voltage had been applied by a d.c. breakdown system with a ramp rate .47V/S at room temperature. Figures 23 and 24 show the typical I-V characteristics on samples containing stearic acid films with thickness of about 441A and 500A, respectively. The data derived from I-V characteristics on initial breakdown voltages and corresponding breakdown fields are summarized in Table 2. Further discussion and analysis of these results are given in the following chapter. 50 2. 8 4J c 2. 4. 3 O 2. 0 1. 6' 1 . 2- 8* 1 2 24 Voltage(volts) Figure 22 I-V characteristics for Si-Si02-Al structures with film thickness 461X, contact area 1. 57mm and ramp rate . 47V/sec 51 E C u u 3 2. 0" 1. 6« 1. £• . 8« . 4» 24 12 36 48 Voltage(volts) Figure 23 I-V characteristic of Si-Si02-stearic acid Al with film thickness 441A, contact area 1.33mm , and ramp rate .47V/sec E C Q> U U 3 O 4» r L 12 24 36 48 60 Voltage(volts) Figure 24 I-V characteristic of Si-Si02-stearic acid-Al with film thickness 50oA, contact area 1.33mm and ramp rate .39V/sec 53 REFERENC E F i gur e 2 4 Figur e 2 Figur e 2 3 to OJ r-l E E E E E Q. •-^ E > :> > (C oc CO CO CO cn cr. (0 c o o o c ^— o to FIEL D X X X X X X BREAKDOW N in ID t>^ CM O Cd 4J (d X3 > I VOLTAG E 2 6 . V 29 . 6 V 3 0 . 7 V 59 . 4 V 61.7 V 57 . 6 V CM O to Q) INITIA L BREAKDOW N •M J- (d E E to ID 46 1 I 5 0 A 44 1 A 484 A 7 0 A tN THICKNES S Xi (d H (M CM (M (D o o INSULATO R •M •M •M STEARI C ACI D STEAR I ACI D STEARI C ACI D to to to CHAPTER V DISCUSSION AND CONCLUSION The major goal of this experimental study is to investigate and compare the C-V characteristics of MIS structures containing only Si02, and Si02 and stearic acid films. Another objective is to measure the initial breakdown voltaqes( d. c. ) of these MIS structures. Current-voltage characteristics of the "annealed" test specimens containing stearic acid films were also studied. Results from these experiments are discussed and interpreted in the following sections. Analysis of C-V Data Following the C-V characteristic measurements on all the test specimens, the following conclusions can be drawn from a comparison of devices containing silicon dioxide and Si + stearic acid films. The MOS structures in this study consist of an n-type silicon. a silicon dioxide layer, and an aluminum metal contact The resulting capacitance-voltage characteristics are shown in Figures 15-17. When a large positive bias is applied to the metal gate, electrons are pushed back to the silicon surface. The silicon then behave much like a 54 55 metal and the capacitance measured is that of the oxide layer alone. It is denoted as accumulation case. When a small positive bias is applied to the metal gate, electrons are repelled and a region depleted of majority carriers is formed at the silicon surface. This situation is called the depletion case. The depletion region adds to the width of the dielectric and the measured capacitance begins to drop. With decreasing negative bias, the width of the depletion region increases. At some negative bias, an inversion region is formed at the surface and additional charge induced in the silicon appear in the form of holes in this narrow inversion region. Thus the depletion region width approaches a maximum value and consequently the capacitance reaches a minimum value. Thus, the C-V plots on all the devices containing Si02 clearly exhibit inversion and accumulation regions in the negative and positive bias conditions, respectively. C-V characteristics under reverse biasing conditions show almost no hysteresis. For the stearic acid MIS structures, the resulting C-V characteristics are shown in Figure 18-19. The MIS structures consist of p-type silicon with a very thin oxide layer( "^20-25^) , a stearic acid layer, and an aluminum metal contact. When a large negative bias is 56 applied to the metal gate, holes are attracted to the silicon surface. The silicon should then behave much like a metal and one expects a maximum measured value of capacitance. But our experimental C-V curves show unexpected results. On the left side of Figure 18(i.e., under negative bias conditions), the C-V curves exhibit a considerably lower capacitance than expected. This shows that instead of accumulation, there is inversion under negative bias conditions which implies as if p- type surface is inverted to n-type. Although, the C-V characteristics are reproducible, the physics to explain such behavior is not fully understood. In these devices we have also observed an appreciable shift of C-V curves between forward and reverse biasing conditions. However, it must be pointed out that the calculted density of interfacial states in these devices are comparable to those containing only Si02(Tablel). The small difference of density of states values may be caused by the charges located on the outer surface of the insulator and insulator-oxide layers. Our experiments were limited and did not have the ability to determine the charge and mobile ion drifting into the Si02 and stearic acid layers. 57 Analysis of I-V Dat In the I-V measurements of both Si02 and stearic acid films, measurements were made with the circuit shown in Figure 12 wherein a ramp voltage (i.e., increasing linearly with time) was applied to these MOS and MIS samples. Breakdown was accompanied by a rapid voltage drop across the test specimens which would be recorded on the I-V characteristic. Present investigations on stearic acid and silicon dioxide films have exhibited the "onset breakdown" event. Table 2 shows these breakdown voltages and corresponding breakdown- fields for various thicknesses of S1O2 and fatty acid films. The I-V plots on some samples are shown in Figures 22-24. The onset breakdown fields for devices containing Si02 films shown an increasing with decreasing film thickness, as expected. However, caution must be exercised in the interpretation of this limited data. The I-V curves, in principle, can be divided into three regions; an initial linear region, non-linear region where the current increases exponentially, and the voltage collapse through current runaway. At some threshold voltages greater than the initial breakdown voltage, the energy stored in the capacitor is more than it can dissipate and therefore the energy gets discharged through a conducting channel 58 leading to the "runaway" in the I-V curves. This must be noted here that onset breakdown fields are higher for Si02 films than fatty acid films. This can be ascribed to the better quality of Si02 films which were grown by sputtering. Fatty acid films, on the other hand, were grown by thermal evaporation which presumably have relatively higher density of voids, pinholes and/or inhomogeneities. Thi ckness Dependence Behavi or of Breakdown Fields The breakdown properties of the thermally grown Si02 and stearic acid films show a wide variation. Depending on which measurement conditions are used, this variability may or may not be observed. With regard to thickness dependent behavior of breakdown fields, the work has been done by several groups on a variety of dielectric films. Most of them have found that the breakdown field is thickness dependent given by F « d -a where F is the breakdown field and d is film thickness. Table 3 summarizes some of the earlier results on thickness dependent behavior. In the present work, I-V characteristics have been obtained on oxide and insulator films in thickness range from 4OO-7O0X. Based on our observations, we find that the breakdown field is thickness dependent and this 59 Vi Ui rSH. ^' 1-^ d) »:^ fx^ o-j CM CM te TH o fxq T-H [XH •H s: w -p te CT > S r-H •H o< »< o G w o< O O O O o o o CD Cvl •z< CoO 1 1 CO te Q O V O O r/j CM CD O r/:; ^1 w 0 J-i ?-( 12^ «H O O (D bii "'•H '-H TH h-oH CM r^ OO U D: • • ^ d CO ^ (D II II II O tJ O 0 CT Qj •H (0 1 TJ -^ In conclusion, the fatty acid films grown on silicon substrates by thermal evaporation in vacuu m exhibit some unusual C-V characteristics but the results are reproducible. More work would be necessary to understand the possible inversion from p-type to n-type conditions under negative bias conditions. However, since the density of interface states in the case of fatty acid films are comparable to Si02, the former may be good substitute as insulators on semiconductors. The breakdown fields of fatty acid films can also be improved by electrical or thermal annealing which has been demonstrated in our laboratory(27) LIST OF REFERENCES 1. K. B. Blodgett and I. Langmuir, Phys. Rev., 5_1_, 964( 1937) . Dewitt G. Ong, Modern MOS Technology. McGraw-Hill, Inc.: New York, £, 1984. J. L. Moll, Variable Capaci tance with Large Capaci ty Change. Hescon Convention Record, 3., 32(1959). 4. W. G. Pfann and C. G. B. Garrett, Proc. IRE, 47, 201 1 ( 1 959) 5. L. M. Terman, Solid State Electron., 5., 285(1962). 6. K. Lehovec and A. Slobodskoy, Phys. Status Solidi, 3., 447(1963). 7. A. S. Grove, Ph.vsics and Technology of Semi conductor Devi ces, John Wiley and Sons: New York, 1967 ( pp. 263-276) 8. C. M. Osburn and D. W. Ormond, J. Electrochem, Soc, , 119, 591(1972). 9. F. Forlani and N. Minnaja, Phys. Status Solidi, 4_, 311, (1964). 10. N.Klein, Thin Solid Films, Z. 149(1971) 1 1. C. M. Osburn and D. W. Ormond, J Electrochem. Soc. , 119, 597( 1 972) . 12. J. J. 0' Dwyer, The Theor.v of Pi electri c Breakdown i n Solids, Oxford University Press: Fair Lawn, NJ, 1 964. 1 3. J. J. 0' Dwyer, J. Appl. Phys., 40., 3887(1969) 1 4. C. H. Huang and V. K. Agarwal, J. Vac. Sci Technol 3., 2000( 1985) . 15. J. J. 0' Dwyer, ibid., 3£, 4356(1968). 61 62 16. S. M. Sze, Ph.vsi cs of Semi conductor Devi ces. John Wiley and Sons: New York, 1 969( pp. 425-436) . 1 7. Measurement S.vstems for Semi conductor Characteri zati on, EG&G Princeton Applied Research: Princeton, 1984. 18. R. Niedermayer and H. Mayer, Basi c Problems i n Thi n Fi Im Ph.vsics. Vandenhoeck and Ruprecht: Germany, 1966( pp. 604-61 3) , 19. S. M. Sze, Physics of Semiconductor Devices, John Wiley and Sons: New York, 374(1981). 20. G.G.Roberts, Solid-State Commun. , 12., 683(1979). 21. M. C. Petty and G.G.Roberts, Electron. Lett., 1_5., 335( 1979) . 22. G. G. Roberts, M. C. Petty, S. Baker, M. T. Fowler andN, J, Thomas, Thin Solid Films, 1 32. 113(1985), 23. I.Lundstrom and M. Stenberg, Chem. Phys. Lipids 1 2, 181(1974). 24. I. Lundstorm, M. S. Shivaraman and C. Svensson, Surface Sci. , 61, 497( 1 977) . 25. G. G. Roberts, K. P. Pande and W. A. Barlow, Electron Lett. , U., 581 ( 1 977) . 26. S. D. Senturia, C. M. Sechen and J. A. Wishneusky, J. Appl. Phys., 30., 106(1977). 27. R.Smith, "Effects of thermal annealing on the electrical breakdown of thin fatty acid films." Thesis, Texas Tech University(1988). PERMISSION TO COPY In presenting this thesis in partial fulfillment of the requirements for a master's degree at Texas Tech University, I agree that the Library and my major department shall make it freely avail able for research purposes. Permission to copy this thesis for scholarly purposes may be granted by the Director of the Library or my major professor. It is understood that any copying or publication of this thesis for financial gain shall not be allowed without my further written permission and that any user may be liable for copy right infringement. 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