Instruction Set Comparisons Procedure Examples CS 740 Procedure linkage • Passing of control and data Code Example

Sept. 12, 2003 • stack management int rfact(int n) { Control if (n <= 1) • Register tests return 1; return n*rfact(n-1); Topics • Condition codes } • Code Examples • loop counters – Procedure Linkage – Sparse Matrix Code • Instruction Sets – Alpha – PowerPC –VAX – x86 –2– CS 740 F’03

Alpha rfact VAX

Registers rfact: Pinnacle of CISC • $16 Argument n ldgp $29,0($27) # setup gp rfact..ng: • Maximize instruction density • $9 Saved n lda $30,-16($30) # $sp -= 16 .frame $30,16,$26,0 • Provide instructions closely matched to typical program operations – Callee save stq $26,0($30) # save return addr stq $9,8($30) # save $9 • $0 Return Value .mask 0x4000200,-16 Instruction format .prologue 1 • OP, arg1, arg2, … Stack Frame bis $16,$16,$9 # $9 = n cmple $9,1,$1 # if (n <= 1) then – Each argument has arbitrary specifier • 16 bytes bne $1,$80 # branch to $80 subq $9,1,$16 # $16 = n - 1 – Accessing operands may have side effects • $9 bsr $26,rfact..ng # recursive call mulq $9,$0,$0 # $0 = n*rfact(n-1) Condition Codes • $26 return PC br $31,$81 # branch to epilogue .align 4 • Set by arithmetic and comparison instructions $sp + 8 save $9 $80: $sp + 0 save $26 bis $31,1,$0 # return val = 1 • Basis for successive branches $81: ldq $26,0($30) # restore retrn addr Procedure Linkage ldq $9,8($30) # restore $9 addq $30,16,$30 # $sp += 16 • Direct implementation of stack discipline ret $31,($26),1

–3– CS 740 F’03 –4– CS 740 F’03 VAX Registers VAX Operand Specifiers

• R0–R11 General purpose Forms Varie s wit – R2–R7 Callee save in example code h pus Notation Value Side Eff Use h/pop – Use pair to hold double SP Ri ri General purpose register • R12 AP Argument pointer Temp Space $v v Immediate data – Stack region holding procedure arguments (Ri) M[ri] Memory reference • R13 FP Frame pointer Local Current v(Ri) M[ri+v] Mem. ref. with displacement Vars – Base of current stack frame Frame A[Ri] M[a+ri*d] Array indexing • R14 SP Stack pointer FP Saved – A is specifier denoting address a – Top of stack Caller – d is size of datum State • R15 PC Program counter (Ri)+ M[ri] Ri += d Stepping pointer forward AP Arg Count – Used to access data in code -(Ri) M[ri-d] Ri –= d Stepping pointer back • N C V Z Condition codes Previous Args Frame Examples – Information about last operation result Address • Push sr move sr ,–(SP) – Negative, Carry, 2’s OVF, Zero c c • Pop dest move (SP)+, dest –5– CS 740 F’03 –6– CS 740 F’03

VAX Procedure Linkage VAX rfact

Caller Registers _rfact: SP .word 0x40 # Save register r6 • Push Arguments Argn • r6 saved n movl 4(ap),r6 # r6 <- n – Relative to SP • • r0 return value cmpl r6,$1 # if n > 1 • proc: mask jgtr L1 # then goto L1 • Execute CALLS narg, proc • 1st instr. Stack Frame movl $1,r0 # r0 <- 1 Arg1 ret # return – narg denotes number of argument words • save r6 L1: – proc starts with mask denoting registers to be pushab -1(r6) # push n-1 saved on stack CALLS narg Note calls $1,_rfact # call recursively mull2 r6,r0 # return result * n CALLS Instruction • Destination ret SP argument last • Creates stack frame FP Saved SP – Saved registers, PC, FP, AP, mask, PSW State Temp Space FP r6 • Sets AP, FP, SP AP narg Current Argn Saved Caller Frame Callee • State • Compute return value in R0 • AP 1 • n • Execute ret Previous Arg1 – Undoes effect of CALLS Frame –7– CS 740 F’03 –8– CS 740 F’03 x86 x86 – Memory Architecture

• Pre-history: 8080 • 80486 • 8-bit microprocessor • MMX • Segmented architecture • Accumulator machine • CS, DS, ES, SS • 8086/8088 • P-III • Addressing Modes • 16-bit machine • Added SSE • Added registers, but many implicit • P4 • Absolute Extended Accumulator Machine #0x45612789 • Added SSE2 • Chosen by IBM • Register indirect • Now floating point looks like a • 16-bit address space general register machine too r • 8087 • Base+displacement • Floating point processor r+0x01234567 • Extended stack machine • Indexed • 80286 r+s • 24-bit address space • Indexed+displacement • 80386 r+s+0x01234567 • 32-bit machine • Base + scaled index • Almost a general purpose register r+(s<

–9– CS 740 F’03 –10– CS 740 F’03

X86 - Registers X86 - Instructions

• Very few registers. Lots of meaning attached to • Standard ones you would expect, and … each • Call, Callf • Accumulator: AX (AH,AL) -> EAX • Ret, retf • Count, loop: CX • Loop: if (--CX) goto PC+0x?? • Data, Mult, Div: DX • Push, Pop • Base: BX • MOVS • Stack pointer: SP • Base pointer: BP (fp) • Prefixes: repeat, lock, … • Source & Dest index regs: SI, DI • Postfixes: address specifiers • 8 Floating point • Condition codes, PC • Can vary in length from 1 byte to 17

–11– CS 740 F’03 –12– CS 740 F’03 X86 - rfact Sparse Matrix Code

_rfact: pushl %ebp ! save old stack base movl %esp,%ebp ! point BP to args Task subl $20,%esp ! get some more stack space • Multiply sparse matrix times dense vector pushl %ebx ! save reg movl 8(%ebp),%ebx ! Get argument – Matrix has many zero entries cmpl $1,%ebx – Save space and time by keeping only nonzero entries jle L3 leal -1(%ebx),%eax ! TRICKY! – Common application addl $-12,%esp ! allocate space for args pushl %eax ! save arg Compressed Sparse Row Representation call _rfact ! make call imull %eax,%ebx ! multiply result [(0,3.5) (1,0.9) (3,2.2)] movl %ebx,%eax ! put back in accumulator 3.50.9 2.2 jmp L5 [(1,4.1) (3,1.9)] .align 4 4.1 1.9 L3: 4.6 0.72.7 3.0 [(0,4.6) (2,0.7) (3,2.7) (5,3.0)] movl $1,%eax [(2,2.9)] L5: 2.9 movl -24(%ebp),%ebx ! restore reg 1.2 2.8 [(2,1.2) (4,2.8)] movl %ebp,%esp ! restore sp [(5,3.4)] popl %ebp ! restore fp 3.4 ret

–13– CS 740 F’03 –14– CS 740 F’03

CSR Encoding CSR Example

Parameters typedef struct { Parameters int nrow; • nrow Number of rows (and columns) int nentries; • nrow = 6 • nentries Number of nonzero matrix entries double *val; • nentries = 13 int *cindex; Val int *rstart; Val } csr_rec, *csr_ptr; • List of nonzero values (nentries) [3.5, 0.9, 2.2, 4.1, 1.9, 4.6, 0.7, 2.7, 3.0, 2.9, 1.2, 2.8, 3.4] Cindex Cindex [0, 1, 3, 1, 3, 0, 2, 3, 5, 2, 2, 4, 5] • List of column indices (nentries) Rstart [(0,3.5) (1,0.9) (3,2.2)] Rstart [0, 3, 5, 9, 10, 12, 13] [(1,4.1) (3,1.9)] • List of starting positions for each row (nrow+1) [(0,4.6) (2,0.7) (3,2.7) (5,3.0)] [(2,2.9)] [(2,1.2) (4,2.8)] [(5,3.4)]

–15– CS 740 F’03 –16– CS 740 F’03 CSR Multiply: Clean Version CSR Multiply: Fast Version

void csr_mult_smpl(csr_ptr M, double *x, double *z) void csr_mult_opt(csr_ptr M, ftype_t *x, ftype_t *z) { { int r, ci; ftype_t *val = M->val; for (r = 0; r < M->nrow; r++) { int *cindex_start = M->cindex; z[r] = 0.0; int *cindex = M->cindex; for (ci = M->rstart[r]; ci < M->rstart[r+1]; ci++) int *rnstart = M->rstart+1; z[r] += M->val[ci] * x[M->cindex[ci]]; } ftype_t *z_end = z+M->nrow; } while (z < z_end) { ftype_t temp = 0.0; Innermost Operation int *cindex_end = cindex_start + *(rnstart++); • z[r] += M[r,c] * x[c] while (cindex < cindex_end) • Column c given by temp += *(val++) * x[*cindex++]; cindex[ci] cindex[ci] *z++ = temp; } • Matrix element M[r,c] = } by val[ci] z M * x r Performance • Approx 2X faster • Avoids repeated memory references –17– CS 740 F’03 –18– CS 740 F’03

Optimized Inner Loop VAX Inner Loop

Registers • r4 cip while (...) while (...) • r2,r3 temp temp += *(valp++) * x[*cip++]; temp += *(valp++) * x[*cip++]; • r5 valp • r6 cip_end • r10 x Observe Inner Loop Pointers • muld3 instruction does 1/2 of the work! cip steps through cindex L36: valp steps through Val movl (r4)+,r0 # r0 <- *cip++ Multiply next matrix value by vector element and add to sum muld3 (r5)+,(r10)[r0],r0 # r0,r1 <- *valp++ * x[r0] addd2 r0,r2 # temp += r0,r1 cmpl r4,r6 # if not done jlssu L36 # then goto L36

–19– CS 740 F’03 –20– CS 740 F’03 Power / PowerPC PowerPC Curiosities

History Loop Counter • IBM develops Power architecture mtspr CTR r3 – Basis of RS6000 »CTR <--r3 – Somewhere between RISC & CISC bc CTR=0, loop • IBM / Motorola / Apple combine to develop PowerPC architecture »CTR–– – Derivative of Power » If (CTR == 0) goto loop – Used in Power Macintosh Updating Load/Store CISC-like features lu r3, 4(r11) • Registers with control information » EA <-- r11 + 4 – Set of condition registers (CR0–7) holding outcome of comparisons » r3 <-- M[EA] – link register (LR) to hold return PC » r11<-- EA – count register (CTR) to hold loop count Multiply/Accumulate • Updating load / stores fma fp3,fp1,fp0,fp3 – Update base register with effective address » fp3 <-- fp1*fp0 + fp3 –21– CS 740 F’03 –22– CS 740 F’03

PowerPC Structure IBM Compiler PPC Inner Loop

Registers while (...) System Partitioning • r3 *cip temp += *(valp++) * x[*cip++]; • Branch Unit Branch Processing • r4 x __L208: – Fetch instructions Unit rlinm r3,r3,3,0,28 # *cip * 8 • r10 valp-8 lfdx fp0,r4,r3 # fp0 <- x[*cip] – Make control decisions Link Reg Count Reg • r11 cip lfdu fp1,8(r10) # fp1 <- *(++valp) • Integer Unit Cond Regs • fp3 temp lu r3,4(r11) # r3 <- *++cip fma fp3,fp1,fp0,fp3 # fp3 += fp1*fp0 – Integer & address • CNT # iterations computations # Decrement & loop bc BO_dCTR_NZERO,CR0_LT,__L208 • Floating Point Unit Observations – Floating Pt. computations • Makes good use of PPC features Integer Floating Point – Multiply-Add Register State Execution Execution Unit Unit – Updating loads • Partitioned like system Integer FP – Loop counter • Allows units to operate Registers Registers autonomously • Requires sophisticated compiler – Converted p++ into ++p – Determine loop count a priori –23– CS 740 F’03 –24– CS 740 F’03 CodeWarrior Compiler PPC Inner Loop Performance Comparison

while (...) Experiment Registers temp += *(valp++) * x[*cip++]; • 10 X 10 matrices • r4 x lwz r0,0(r8) # r0 = *cip • 100% density • r3 valp addi r8,r8,4 # cip++ • 100 multiply accumulates • r8 cip lfd fp1,0(r3) # fp1 = *valp Machine MHz µsecs Cyc/Ele Compiler • fp2 temp addi r3,r3,8 # valp++ slwi r0,r0,3 # r0 *= 8 VAX 25? 2448 122? GCC lfdx fp0,r4,r0 # fp0 = x[] MIPS 25 365 18 GCC fmadd fp2,fp1,fp0,fp2 # temp += () * () 62 63 8 cmplw r8,r10 # Compare r8 : r0? PPC 601 IBM Observations blt *-32 # Loop if < Pentium 90 79 11 GCC HP Precision 100 50 10 GCC • Limited use of PPC features UltraSparc 160 38 12.5 GCC – Multiply-Add PPC 604e 200 14 5.6 CodeWarrior • High performance on modern machines MIPS R10000 185 13.4 5 SGI – They can do lots of things at once Alpha 21164 433 12.2 10.5 DEC – Instruction ordering less critical –25– CS 740 F’03 –26– CS 740 F’03

Summary

Alpha • Simple register state • Every operation has single effect – Load, store, operate, branch VAX • Hidden control state • Operations vary from simple to complex • Side effects possible Power PC • Complex control state • Operations simple to medium • Side effects possible • Hard target for code generator X86 • Well, what can you say: best selling desktop/server proc around

–27– CS 740 F’03