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42 er Chapter architectures in favor of evolving its current architectures [McLean, 1977]. The VAX-11/780—A Virtual Address second intangible area is the preservation of those attrib- utes (other than price) which make minicomputer systems attrac- Extension to 1 tive. These include the DEC PDP-1 Family^ approachability, understandability, and ease of use. Preservation of these attributes suggests that simply an extended W. D. Strecker modelling virtual address minicomputer after a large mainframe is computer not wholly appropriate. It also suggests that during architectural design, tradeoffs must be made between Introduction more than just performance, functionality, and cost. Performance or functionality features which are so complex that they apprecia- Large Virtual Address Space Minicomputers bly compromise understanding or ease of use must be rejected as inappropriate for the minicomputer systems. Perhaps most useful definition of a minicomputer* system is based on on one's such price: depending perspective systems are VAX-II Overview typically found in the $20K to $200K range. The twin forces of — VAX-11 is the Virtual Address eXtention market pull as customers build increasingly complex systems on of PDP-11 architecture et minicomputers—and technology push—as the semiconductor [Bell al, 1970; Bell and Strecker, 1976]. The most distinctive industr\' feature of VAX-11 is the extension of the virtual provides increasingly lower cost logic and memor>' address from 16 — bits as on the PDP-11 to bits. elements have induced minicomputer manufacturers to produce provided 32 With the 8-bit byte the of basic addressable the extension a systems considerable performance and memory capacity. Such unit, provides virtual address of about 4.3 systems are typified by the DEC PDP-11/70. From an architectur- space gigabytes which, even given rapid improve- al of ment in should be point view, the characteristic which most distinguishes many memory technology, adequate far into the of future. these systems from larger mainframe computers is the size of the virtual Since maximal PDP-11 was address space: the immediately available address space compatibility a strong goal, early seen an VAX-11 efforts focused on by individual process. For many purposes the 65K byte design literally extending the PDP-11: the instruction virtual address space typically provided on minicomputers (such preserving existing formats and instruction set and the virtual as the PDP-11) has not been and probably will not continue to be a fitting address extension around them. The objective here was to to the extent severe limitation. However, there are some applications whose permit, possible, the running of existing is in the extended virtual address programming impractical in a 65K byte virtual address space, programs environment. While and this was were perhaps most importantly, others whose programming is realizing objective possible (there three distinct designs), it was feft that the extended architecture appreciably simplified by having a large virtual address space. designs were in the areas of Given the relative trends in hardware and software costs, the overly compromised efficiency, functionafity, and ease. latter point alone will insure that large virtual address space programming it was decided to minicomputers play an increasingly important role in minicom- Consequently, drop the constraint of the PDP-11 instruction format in puter product oflferings. designing the extended virtual In address or native mode of the VAX-11 architecture. principle, there is no great challenge in designing a large space Howev- er, in order to run PDP-11 virtual address minicomputer system. For example, many of the existing programs, VAX-11 includes a PDP-11 large mainframe computers could serve as architectural models for compatibility mode. Compatibility mode provides the basic PDP-11 instruction set such a system. The real challenge lies in two areas: less only privileged instructions — (such as HALT) and instructions are compatibility very tangible and important; and simplicity— floating point (which optional on most PDP-11 not intangible but nonetheless important. processors and required by most PDP-11 The first area is preserving the customer's and the computer software). In addition to a of manufacturer's investment in existing systems. This investment compatibility mode, number other features to exists at preserve PDP-11 investment have been in the many levels: basic hardware (principally busses and provided VAX-11 the VAX-11 peripherals); systems and applications software; files and data architecture, operating system VAXA'MS, and the VAX-11/780 of the VAX-11 bases; and personnel familiar with the programming, use, and implementation architecture. These features include: operation of the systems. For example, just recently a major computer manufacturer abandoned a major eifort for new comput- 1 The equivalent native mode data types and formats are identical to those on the PDP-11. Also, while extended, the 'AFIPS Proc. NCC, 1978, pp. 967-980. VAX-11 native mode instruction set and addressing modes 716 42 VAX-11/780—A Virtual Address Extension to the DEC PDP-11 Family 717 Chapter | Four of the are in the VAX-11 are ver>' close to those on the PDP-11. As a consequence registers assigned special meaning VAX-11 native mode assembly language programming is architecture: quite similar to PDP-11 assembly language programming. contains the 2 The VAX-11/780 uses the same peripheral busses (Unibus 1 R15 is the program counter (PC) which and Massbus) as the PDP-11 and uses the same peripher- address of the next byte to be interpreted in the instruction als. stream. is which the address of 3 The VAXA^MS operating system is an evolution of the 2 R14 the stack pointer (SP) contains PDP-11 RSX-llM and IAS operating systems, offers a the top of the processor defined stack used for procedure similar although extended set of system services, and uses and interrupt linkage. the same command languages. Additionally, VAXA'MS 3 R13 is the frame pointer (FP). The VAX-11 procedure supports most of the RSX-llM/IAS system service requests calling convention builds a data structure on the stack issued in mode. by programs executing compatibility called a stack frame. FP contains the address of this 4 The VAXA'MS file system is the same as used on the structure. RSX-llM/IAS operating systems permitting interchange of 4 R12 is the argument pointer (AP). The VAX-11 procedure files and volumes. The file access methods as implemented calling convention uses a data structure called an argument the RMS record are also the same. by manager list. AP contains the address of this structure. 5 VAX-11 high level language compilers accept the same source as the PDP-11 and languages equivalent compilers The remaining element of the user visible processor state execution of compiled programs gives the same results. (additional processor state seen mainly by privileged procedures is discussed later) is the 16-bit processor status word (PSW). The is well the The coverage of all these aspects of VAX-11 beyond PSW contains the N, Z, V, and C condition codes which indicate of The remainder of this discusses scope any single paper. paper respectively whether a previous instruction had a negative result, native architecture and an the design of the VAX-11 mode gives a zero result, a result which overflowed, or a result which of the VAX-11/780 overview system. produced a carry (or borrow). Also in the PSW are the IV, DV, and FU bits which enable processor trapping on integer overflow, decimal overflow, and floating underflow conditions respectively. VAX-11 Native Architecture (The trapping on conditions of floating overflow and divide by zero for any data type are always enabled.) Processor State Finally, the PSW contains the T bit which when set forces a trap at the end of each instruction. This trap is useful for program Like the PDP-11, VAX-11 is organized around a general register debugging and analysis purposes. processor state. This organization was favored because access to operands stored in general registers is fast (since the registers are Data and Formats internal to the processor and register accesses do not need to pass Types and because a through a memory management mechanism) only The VAX-11 data types are a superset of the PDP-11 data types. in an instruction are needed to a small number of bits designate Where the PDP-11 and VAX-11 have equivalent data types the most the are used on register. Perhaps importantly, registers (as formats (representation in memory) are identical. Data type and the in with a set of modes PDP-11) conjunction large addressing data format identity is one of the most compelling forms of which flexible methods. permit unusually operand addressing compatibility. It permits free interchange of binary data between was to a stack based architec- Some consideration given pure PDP-11 and VAX-11 programs. It facilitates source level compati- ture. However it was because real data rejected program suggests bility between equivalent PDP-11 and VAX-11 languages. It also the of two or three instruction formats superiority operand greatly facilitiates hardware implementation of and software VAX-11 is stack and [Myers, 1977b]. Actually quite oriented, support of the PDP-11 compatibihty mode in the VAX-11 although it is not optimally encoded for the purpose, can easily be architecture. as a stack architecture if desired. used pure The VAX-11 data types divide into five classes: VAX-11 has 16 32-bit general registers (denoted R0-R15) which are used for both fixed and floating point operands. This is in 1 Integer data types are the 8-bit byte, the 16-bit word, the contrast to the PDP-11 which has 16-bit eight general registers 32-bit longword, and the 64-bit quadword Usually these 64-bit The set of fixed and and six floating point registers.
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