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Pep8cpu: a Programmable Simulator for a Central Processing Unit J Pep8CPU: A Programmable Simulator for a Central Processing Unit J. Stanley Warford Ryan Okelberry Pepperdine University Novell 24255 Pacific Coast Highway 1800 South Novell Place Malibu, CA 90265 Provo, UT 84606 [email protected] [email protected] ABSTRACT baum [5]: application, high-order language, assembly, operating This paper presents a software simulator for a central processing system, instruction set architecture (ISA), microcode, and logic unit. The simulator features two modes of operation. In the first gate. mode, students enter individual control signals for the multiplex- For a number of years we have used an assembler/simulator for ers, function controls for the ALU, memory read/write controls, Pep/8 in the Computer Systems course to give students a hands-on register addresses, and clock pulses for the registers required for a experience at the high-order language, assembly, and ISA levels. single CPU cycle via a graphical user interface. In the second This paper presents a software package developed by an under- mode, students write a control sequence in a text window for the graduate student, now a software engineer at Novell, who took the cycles necessary to implement a single instruction set architecture Computer Organization course and was motivated to develop a (ISA) instruction. The simulator parses the sequence and allows programmable simulator at the microcode level. students to single step through its execution showing the color- Yurcik gives a survey of machine simulators [8] and maintains a coded data flow through the CPU. The paper concludes with a Web site titled Computer Architecture Simulators [9] with links to description of the use of the software in the Computer Organiza- papers and internet sources for machine simulators. Most simula- tion course and its availability for download on the Internet. tors for teaching computer organization at the undergraduate level Categories and Subject Descriptors have a command line interface. Those that have a graphical user B.1.5 [Control Structures and Microprogramming]: Microcode interface are usually for machines with smaller instruction sets and Applications – Instruction set interpretation. C.0 [Computer Sys- fewer addressing modes than Pep/8. tems Organization]: General – Modeling of computer architec- Section 2 describes the Pep/8 computer at the assembly, ISA, and ture. K.3.2 [Computers and Education]: Computer and microcode level. Section 3 describes the CPU simulator and shows Information Science Education – Computer science education. some of its capabilities. Section 4 gives examples of how the simu- lator is used in the Computer Organization course. The concluding General Terms section includes details about the simulator’s availability. Design, Languages 2. THE Pep/8 VIRTUAL MACHINE Keywords Pep/8, CPU, Data section, Simulation, Virtual machine, Micropro- 2.1 The assembly and ISA levels gramming, Assembly language, MIPS Pep/8 is a classical 16-bit von Neumann computer with an accu- mulator (A), an index register (X), a program counter (PC), a stack 1. INTRODUCTION pointer (SP), and an instruction register (IR). It has eight address- Virtual machines in computer science are used both for teaching ing modes: immediate, direct, indirect, stack-relative, stack-rela- concepts and for implementing algorithms in industry. [4] The tive deferred, indexed, stack-indexed, and stack-indexed deferred. most famous virtual machine for teaching is probably Knuth’s The instruction set is based on an expanding opcode yielding a MIX [1], and the most widespread machine for implementing total of 39 instructions, which come in two flavors – unary and algorithms in industry is probably the Java virtual machine [2]. nonunary. The unary instructions consist of a single 8-bit instruc- Pep/8 is a virtual machine for teaching computer systems concepts tion specifier, while the nonunary instructions have the instruction [7] based on the seven levels of abstraction popularized by Tanen- specifier followed by a 16-bit operand specifier (OpSp). For the nonunary instructions, the addressing modes determine the operand from the operand specifier as follows: Permission to make digital or hard copies of all or part of this work for per- sonal or classroom use is granted without fee provided that copies are not Addressing mode Operand made or distributed for profit or commercial advantage and that copies Immediate OpSp bear this notice and the full citation on the first page. To copy otherwise, or Direct Mem [OpSp] republish, to post on servers or to redistribute to lists, requires prior spe- Indirect Mem [Mem [OpSp]] cific permission and/or a fee. Stack-relative Mem [SP + OpSp] SIGCSE'07, March 7?11, 2007, Covington, Kentucky, USA. Stack-relative deferred Mem [Mem [SP + OpSp]] Copyright 2007 ACM 1-59593-361-1/07/0003...$5.00. Indexed Mem [OpSp + X] Stack-indexed Mem [SP + OpSp + X] 0 1 8 14 15 22 23 A IR T3 M1 0x00 0x01 Stack-indexed deferred Mem [Mem [SP + OpSp] + X] 2 3 9 10 16 17 24 25 LoadCk X T4 M2 0x02 0x03 4 5 11 18 19 26 27 5 At the assembly level, students learn the compilation process by C SP T1 T5 M3 0x04 0x08 5 translating small programs to Pep/8 assembly language. The Pep/8 6 7 12 13 20 21 28 29 B PC T2 T6 M4 0xFFA 0xFC 5 addressing modes illustrate the memory model of the high-order 30 31 A CPU registers M5 0xFE 0xFF language. For example, global variables are accessed with direct CBus ABus BBus addressing, local variables with stack-relative addressing, local Bus arrays with stack-indexed addressing, and dynamic variables via MARB pointers with indirect addressing. MARCk The following code fragment is an example of what Pep/8 assem- MARA MDRCk bly language looks like. MDR BR main data: .EQUATE 0 ;struct field MDRMuxMDRMux next: .EQUATE 2 ;struct field AMux AMux ; MDRMux ;******* main () CMux 4 ALU ALU first: .EQUATE 4 ;local variable CMux Cin p: .EQUATE 2 ;local variable Cout value: .EQUATE 0 ;local variable C CCk main: SUBSP 6,i ;allocate locals Mem V VCk LDA 0,i ;first = 0 ANDZ Addr STA first,s ANDZ Z ZCk Zout DECI value,s ;cin >> value 0 Data 0 while: LDA value,s ;while (value != -9999) 0 0 N NCk CPA -9999,i MemWWrite BREQ endWh MemRead LDA first,s ; p = first STA p,s Figure 1. LDA 4,i ; first = new node CALL new STX first,s • A two-port register bank LDA value,s ; first->data = value • A 16-function arithmetic logic unit (ALU) LDX data,i • A set of four status bit latches (NZVC) STA first,sxf • A memory address register (MAR) The fragment is part of a program that is a translation of a C++ program containing local pointers. An assembly language symbol • A memory data register (MDR) such as first corresponds to the variable identifier in the C++ • Three 8-bit multiplexers (AMux, CMux, MDRMux) program and equates to its offset on the run-time stack. The letter i • A three-input, one-output combinational circuit (ANDZ) specifies immediate addressing, the letter s specifies stack-relative addressing, and the letters sxf specify stack-relative deferred The control section, not shown in the figure, is to the right of the addressing. data section. The control lines coming in from the right are from the control section. There are two kinds of control signals – combi- Most virtual machines for teaching have software support to pro- national circuit controls and clock pulses. Names of the clock vide students with hands-on experience in programming at the pulses all end in Ck and all act to clock data into a register or latch. assembly level, and Pep/8 is no exception. In the Computer Sys- For example, MDRCk is the clock input for the MDR. When it is tems course, students are given complete C++ programs and pulsed, the input from the MDRMux is clocked into the MDR. required to translate them as a compiler would. They have access to an assembler that translates their programs to the ISA level, The two-port register bank has 32 8-bit registers. Because Pep/8 is which they can then test on a virtual machine simulator. a 16-bit machine, the accumulator consists of the two registers at register addresses 0 and 1. The index register consists of registers 2 The Computer Systems course is a prerequisite for the Computer and 3, and so on for the stack pointer, program counter, and Organization course. So, students in Computer Organization instruction register. Registers 11 through 21 are temporary scratch already have a working knowledge of the high-order language, pad registers not visible to the programmer at the assembly or ISA assembly language, and ISA levels of a von Neumann machine levels. Registers 22 through 31 are read-only memory (ROM) that based on an implementation of the Pep/8 computer. Pep8CPU is a are convenient for masking operations. software package that takes students down to the microcode level in the Computer Organization course. All the thick buses in the figure, except for the system bus, are eight bits wide. The five lines labeled A provide an address to the 2.2 The microcode level register bank that selects one of the 32 registers to be placed on Figure 1 shows the data section of the Pep/8 central processing ABus. Similarly, the five lines labeled B select a register for BBus. unit. It consists of the following parts: The ALU is strictly combinational with no storage. The four lines Cycle 1 transfers the operand specifier into the MAR. A=9 puts the labeled ALU select which of the 16 functions the ALU will per- high-order byte on ABus, B=10 puts the low-order byte on BBus, form.
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