Chapter 1: Microprocessor architecture
ECE 3120 – Fall 2013
Dr. Mohamed Mahmoud http://iweb.tntech.edu/mmahmoud/ [email protected] Outline
1.1 Computer hardware organization 1.1.1 Number System 1.1.2 Computer hardware organization
1.2 The processor
1.3 Memory system operation
1.4 Program Execution
1.5 HCS12 Microcontroller 1.1.1 Number System
- Computer hardware uses binary numbers to perform all operations.
- Human beings are used to decimal number system. Conversion is often needed to convert numbers between the internal (binary) and external (decimal) representations.
- Octal and hexadecimal numbers have shorter representations than the binary system.
- The binary number system has two digits 0 and 1
- The octal number system uses eight digits 0 and 7
- The hexadecimal number system uses 16 digits: 0, 1, .., 9, A, B, C,.., F
1 - 1 - A prefix is used to indicate the base of a number.
- Convert %01000101 to Hexadecimal = $45 because 0100 = 4 and 0101 = 5
- Computer needs to deal with signed and unsigned numbers
- Two’s complement method is used to represent negative numbers
- A number with its most significant bit set to 1 is negative,
otherwise it is positive. 1 - 2 1- Unsigned number %1111 = 1 + 2 + 4 + 8 = 15 %0111 = 1 + 2 + 4 = 7 Unsigned N-bit number can have numbers from 0 to 2N-1 2- Signed number %1111 is a negative number. To convert to decimal, calculate the two’s complement The two’s complement = one’s complement +1 = %0000 + 1 =%0001 = 1 then %1111 = -1 %0111 is a positive number = 1 + 2 + 4 = 7.
- Unsigned 8-bit number can have numbers from 0 to 255 %00000000 to %11111111 - Signed 8-bit number can have numbers from -128 to +127 to %10000000 to %01111111 1 - 3 - Signed N-bit number can have numbers from -2N-1 to 2N-1-1 - Unsigned 3-bit number can represent numbers from 0 (= %000) to 7 (=111) - Signed 3-bit number can represent numbers from -4 (= %100) to 3 (= %011)
Computer does not know whether a bit sequence represents a signed or an unsigned number -> It is the programmer’s responsibility! 1 - 4 1.1.2 Computer hardware organization
- A Computer consists of hardware and software - The hardware consists of processor, input devices, output devices and memory.
Computer Hardware Organization
1 - 5 1- Processor - Also called Microprocessor (MP) or Central Processing Unit (CPU). - Executes programs. - Performs (1) all of the computational operations and (2) the coordination of the usage of resources of a computer - Ex. can a memory and an input device write data on a shared bus simultaneously? NO, control signals are issued by processor to coordinate the devices operations.
2- Input devices - Used to enter the programs to be executed and the data to be processed into the computer. - Examples: keyboard, keypad, switches, sensors, scanners, bar code readers, etc. 1 - 6 3- Output devices - The results of the operations done by the processor should be displayed or printed on a media so that the user can see them. - Examples: seven segment displays, light emitting diode (LED), liquid crystal displays (LCD), a monitor, etc.
4- Memory - Programs to be executed and data to be processed are stored in memory so that the processor can readily access them.
5- Buses - Address bus: The set of conductor wires that carry address signals. - Data bus: The set of conductor wires that carry data signals - Control bus: The set of conductor wires that carry control signals 1 - 7 Outline
1.1 Computer hardware organization
1.2 The processor
1.3 Memory system operation
1.4 Program Execution
1.5 HCS12 Microcontroller - A processor consists of arithmetic logic unit (ALU), control unit , and registers . -The ALU performs the arithmetic and logic operations requested by the user’s program. - An ALU that can perform 4 operations (addition, summation, AND, OR) is shown in Figure 1.1.
1 - 8 -All four operations are performed simultaneously by different circuits whereas the instruction opcode tells the multiplexer to select one of the four units’ outputs as the result - The adder is used to perform addition and subtraction operations - The ALU is more complicated if the processor designer wants to implement more operations directly in the hardware.
Remember how multiplexer works :
Selector
Select Output 00 I I0 0
I 01 I1 Inputs 1 MUX output I2 10 I2
I3 11 I3 1 - 9 The ALU operations operates in the following manner :- 1- Opcode = 00 - The comparator output = 0, MUX2 output = CIN, MUX1 output = B, the adder inputs are n-bit A and n-bit B. - The result of the adder is A + B + CIN, CIN is the carry input. - MUX3 selects the output of the adder and the carry because the opcode is 00. 00
0
0
A + B+ CIN
1 - 10 2- Opcode = 01 - The comparator output = 1, MUX2 output = 1, MUX1 output = B (one’ complement of B), the adder inputs are n-bit A and n-bit B. - The result of the adder is A + B + 1 = A - B. Remember B + 1 = - B. B + 1 is the two’s complement of B. - MUX3 selects the output of the adder and the carry (called borrow) because the opcode is 01. 01
1
1
A + B + 1 = A - B 1 - 11 3- Opcode = 10 The MUX3 selects the output of the AND. It is the n bits resulted from performing logic AND operation for A and B.
4- Opcode = 11 The MUX3 selects the output of the OR. It is the n bits resulted from performing logic OR operation for A and B.
Remember :-
X means zero or one
The ALU in Fig. 1.1 can be expanded to perform more
instructions 1 - 12 2- Control Unit - The control unit decodes machine codes and performs the operations specified by the machine code. - A machine instruction has a mandated field called the opcode which can tell what operations are needed to execute the instruction. Other fields are optional and used to specify the operands to be operated on. - A machine instruction is a combination of 0s and 1s. - Instruction execution is timed by a clock signal . A clock signal is a square signal. At each cycle, some operations are performed. One machine instruction may need multiple cycles to be executed. - A program usually has multiple instructions that are normally stored in sequential locations in memory. 1 - 13 - The control unit uses a program counter (PC) to keep track of the address of the instruction to be executed next . - The first step to execute an instruction is to fetch it from the memory location pointed by PC and place it in the instruction register (IR) where it is decoded, and executed. - The result of the decoding process is appropriate control signals to execute the instruction. - Whenever the processor fetches an instruction, the PC will be incremented by the length of that instruction so that it points to the next instruction . - Both PC and IR are two registers inside the microprocessor. - The processor may not execute instructions in sequence due to the need to execute instructions based on the condition or the need to repeat a certain group of instructions . - The processor uses conditional and unconditional branch (or jump ) instructions to change the program flow. 1 - 14 - Conditional branches are performed when a condition is satisfied, e.g., the previous instruction caused a carry. - After executing an instruction, the condition code register (CCR) is usually automatically updated to reflect the result of the instruction. - The CCR is usually used to make a condition in conditional branch. Each bit in the register is independent and has a different indication. - Example, a zero flag bit is set if the instruction result is zero a sign flag bit is 1 if the result is negative and so on. - EX.: A = A – B jump if A = B If zero flag = 1 jump to --- 1 - 15 3- Registers - A register is a storage location inside the CPU. - A register is used to hold data or address during the execution of an instruction. - A register, very close to the ALU, provides fast access to operands for program execution. - Some processors provide a dedicated register (often called an accumulator ) as one of the operands of most of the instructions. - The number of registers varies from processor to processor - Unlike memory, registers are not used to store the program or large data. - Accessing memory is much slower than accessing registers
1 - 16 2- Computer software - Computer programs are known as software - A program is a sequence of instructions - Machine instruction: A sequence of binary digits which can be executed by the processor 0001 1000 0000 0110: A ← [A] + [B] 0100 0011: A ← [A] + 1 - Machine instruction: Hard to understand, enter, debug, and maintain for human being - Assembly language: An assembly instruction is a mnemonic representation of a machine instruction. Examples: ABA;A ← [A] + [B] DECA ;A ← [A] – 1
1 - 17 - Assembler is a program that translates an assembly language program to the equivalent machine language code that can be executed by the microprocessor. - Compiler is a program that translates a high level programming language to the equivalent machine code. - Source code: A program written in assembly or high-level language - Object code: The output of an assembler or compiler
1 - 18 Compiler and assembler
- Compiler is more complex than assembler - Each assembly language instruction is usually translated to one machine language instruction - But, one statement written in high level language may be translated into tens or hundreds of machine language instructions and this translation is not usually optimal - Assembly language uses mnemonic symbol to represent each machine translation - The assembly language can make programming much easier than in machine language - The microprocessor can execute only machine language programs
1 - 19 Microprocessor VS Microcontroller - A microprocessor (MP) needs external devices such as memory, I/O ports, etc to run a program. - A microcontroller (MCU) contains a processor, memory and I/O ports within a single chip . - It can also contains timer, serial communication interface, and A/D (analog/digital) and D/A converters - Microcontrollers have been used in almost every product that requires a certain amount of intelligence. - Microcontrollers have been used in displays, printers, keyboards, modems, charge card phones, home appliances such as washing machines and microwave ovens, automobile control, and so on.
1 - 20 Embedded Systems - An embedded system is a special purpose computer system designed to perform a dedicated function . - Software written for embedded systems is often called firmware and is stored in flash memory chips. - Examples of embedded systems: MP3 players, traffic lights, digital watches
1 - 21 Outline
1.1 Computer hardware organization
1.2 The processor
1.3 Memory system operation
1.4 Program Execution
1.5 HCS12 Microcontroller Semiconductor Memory
- Widely used in embedded systems. - Non-volatile memory does not lose the information when there is no power, but volatile memory does. - Read only memory: the MP can read but cannot write.
- Reading memory is nondestructive – memory does not lose data when CPU reads.
- Writing memory is destructive – when the CPU writes data to memory, the old data is written over and destroyed. 1- Random Access Memory (RAM) - Read/write by MP. - Same amount of time is required to access any location on the same chip. - Dynamic random access memory (DRAM), and Static random access memory (SRAM) are volatile. 1 - 22 -Magneto RAM (MRAM) and Ferroelectric RAM (FRAM) are non-volatile. 2- Read-only memory (ROM) : - Nonvolatile. - Mask-Programmed ROM (MROM) is programmed once during manufacture. - Programmable read-only memory (PROM): programmed once by the end user by using a special device. -Erasable programmable ROM (EPROM): Electrically programmable many times by user by using a special device. The whole chip can be erased by ultraviolet light. -Electrically erasable programmable ROM (EEPROM): Electrically Programmable many times by user by using a special device. Electrically erasable by using a special device. can be erased one location, one row, or whole chip in one
operation 1 - 23 Flash memory: - Electrically erasable and programmable many times by the MP. - Can erase a block or the whole chip. - The most widely used nonvolatile memory technology. - Most microcontrollers use on-chip flash memory as their program memory .
1 - 24 Memory System Operation
- Each memory location has two components: address and contents .
- The organization of a memory chip is indicated by m x n, where m is the number of locations in the chip and n indicates the number of bits in one location .
- The number of address bits needed for selecting a memory
location is Log 2m - For example a memory chip has 16 bits addressing bits, how many locations are in this memory? 216 = 64 Kbytes - How many addressing bits are needed to point to 64 Kbytes
locations? Log 264K = 16 bits - The memory data bits are connected to the data bus.
- The memory address bits are connected to the address bus. 1 - 25 -[reg ] and [addr ] specifies the contents of a register and the memory location at address addr, respectively.
- m[addr] the notation for the memory location at addr [$40] the content of the memory location at $40
[A] the content of register A
[A] → m[$40] copy the content of register A to the memory location at $40
- Registers are referred to by their names whereas memory locations are referred to by their addresses
Byte = 8 bits, Word = 2 bytes = 16 bits, Nibble = 4 bits Kilobyte (KB) = 210 bytes =1026 bytes
Megabyte (MB) = K2 Bytes = 220 bytes = 1,048,576 bytes 1 - 26 Gigabyte (GB) = K3 Bytes = 230 bytes = 1,073,741,824 bytes Read Operation - RD in the MP is connected to OE (output enable) in the memory and WR is connected to WE (write enable) - The processor places the address of the memory location that it intends to read on the address bus and asserts the RD signal. (RD = 1 and WR = 0) - After some time, the data stored in the location referred by the address will be out of the memory to the data bus to be read by the MP - RD and WR are two control signals to inform the memory to read or write. n bits d bits
m = 2d locations
1 - 27 Write Operation
- The processor places the address of the location that it intends to write on the address bus.
- The processor also places the data that it intends to write on the data bus and asserts the WE signal. RD = 0 and WR =1
- The memory chip stores the data on the data bus in the selected memory location after some time.
- If a memory location is one byte but we want to store a bigger data, e.g., 16-bit number what should we do ? Store the data in two locations. To read the data, we read two location and to write, we write two times.
- RD and WR can not be 1 at the same time but can be zeros.
1 - 28 Outline
1.1 Computer hardware organization
1.2 The processor
1.3 Memory system operation
1.4 Program Execution
1.5 HCS12 Microcontroller - In most embedded systems, all the program is stored in a nonvolatile memory. - Where does the processor start to execute program after power on ? (1) From a fixed location such as address 0 (Atmel microcontroller), or (2) Fetch the starting address from a fixed location in the memory ($FFFE and $FFFF in HCS12) - How does the processor update the program counter (PC) ? Increment the program counter by the length of the instruction just executed. - How flow control instructions (such as Jump and subroutine call) are executed ? Set the PC with the address of the target next instruction.
- D flip-flop When set = 0, Q = 1 at the first rising edge clock 1 - 29 When reset = 0, Q = 0 at the first rising edge clock Otherwise: Q = D at the first rising edge clock (CLK) - The PC is 16-bit register having 16 flip-flops, each flip-flop stores one bit - A common building block for the PC circuit is shown below. 1- Whenever the power is turned on, the flip-flops are reset, PC = 0 and the instruction fetch will start from address 0.
1 - 30 2- If the instruction being executed is a conditional branch and the branch condition is true , the branch signal will be 1, the MUX1 output is the branch offset
The new PC value = the old PC value + the branch offset
1
0
1 - 31 3- If the instruction being executed is a jump instruction , then PC = Jump target (or the target address)
1
1 - 32 3- If the instruction being executed is not a program flow control instruction , then
The new PC value = the old PC value + 1 The PC is incremented by 1 after each instruction byte is fetched.
0
0
1 - 33 Architecture of the Processor X
- Used to explain the instruction execution process. - Has a separate data memory and program memory spaces. - An 8-bit accumulator A and a 16-bit register ptr. - 8-bit value can be used to specify a data memory location from 0 to 255. - For data memory locations with address higher than 255, the processor uses the 16-bit register ptr to specify the address. - Processor X uses a MDR register to hold data to be written and read from data memory. - Opcode of any instruction is the first byte - The instruction set implemented by the processor is given in Table 1.3.
1 - 34 How the processor X will execute this instruction sequence ld 0x20, #0 ; place 0 in data memory at 0x20 ld 0x21, #20 ; place 20 in data memory at 0x21 ld ptr, #0x2000 ; load 0x2000 into the ptr register loop: ld A,@ptr ; load the memory contents pointed to by ptr and A, #0x03 ; and the value 0x03 with accumulator A bnz next ; branch if the result is not 0 inc 0x20 ; increment the memory location at 0x20 by 1 next: dbnz 0x21,loop ; decrement memory location at 0x21 and branch ; if the contents of 0x21 is not zero yet 1 - 35 Instruction ld 0x20, #0 (machine code 75 20 00) - Place 0 in data memory at 0x20 1- Fetch instruction: Processor X places 0 (contents of PC) on the address bus to read from program memory. 2- It reads the first byte (opcode) = 0x75. PC is incremented to 0x0001. Figure 1.5 shows the opcode read cycle. 3- From the opcode, the control unit recognizes that it needs to read the following two bytes after the opcode. It reads 0x20 and 0x00 and holds them in IR. PC is incremented after each read operation to be 3. 4- Data memory address bus ← 0x20 Data bus ← 0x00 Performs a write operation to write the value 0 to location 0x20. As shown in Fig. 1.6
1 - 36 1 - 37 Instruction ld 0x21, #20 (machine code 75 21 14) - Similar to previous instruction. - PC = 0x0006 and [0x21] ← 20.
Instruction ld ptr, #0x2000 (machine code 90 20 00)
- load 0x2000 into the ptr register 1- Fetch instruction: the program memory address bus ← PC value (0x06), request to read. Figure 1.7 shows the opcode read cycle. 2- Opcode = 0x90 and PC = 0x07. 3- From the opcode, we need to read the following two locations. Read 0x20 and 0x00 and PC = 0x09. 4- ptr ← 2000
1 - 38 1 - 39 Instruction ld A, @ptr (machine code E0)
- A = the memory contents pointed to by ptr
Why this machine instruction is too short?? Because the operands are registers. If possible, try not to use the immediate values or the memory often to reduce the program space.
1- Fetch opcode: program memory address bus ← PC value (0x09), request to read, increment PC by 1 to be 0x0A. 2- The opcode does not require reading more from the program memory. 3- Execute: The processor reads the memory location pointed by ptr. Data memory address bus ← the contents of ptr and request a read operation. 3- The control unit recognizes that the instruction requires storing the returned value by the memory in register A. 1 - 40 Instruction and A, #0x03 (machine code 54 03) - And the value 0x03 with accumulator A
1- Fetch opcode: The program memory address bus ← PC value (0x0A), request a read, the opcode byte (0x54) is returned, PC is incremented to 0x0B. 2- Fetch operand: the control unit recognizes that it needs to read following value to the opcode. 3- Program memory address bus ← PC value, Request to read, PC ← 0x0C. 4- The memory return value is 0x03. 5- Perform an AND operation on the contents of A and the value 0x03 and places the result in A
1 - 41 Instruction bnz next (machine code is 70 02) - branch if the result is not 0
1- Fetch: The program memory address bus ← PC value (0x0C). Perform a read operation. PC is incremented to 0x0D. 2- The opcode (0x70) tells the processor to perform another read to fetch the branch offset. The program memory address bus ← PC value (0x0D), read 0x02 and store in IR. PC incremented to 0x0E. 4- If A is not 0 then update PC to skip the next instruction, else execute to next instruction
- Notice: Some instructions need more phases, and then more execution time, and some instructions need more memory. Usually the instructions that need memory read/write takes more memory time 1 - 42 Instruction inc 0x20 (machine code 05 20) - Increment the memory location at 0x20 by 1
1- Fetch: The program memory address bus ← PC (0x0E), request read, PC is incremented to 0x0F. 2- The returned opcode (0x05) requires performing another read to fetch an 8-bit address from program memory. 3- The program memory address bus ← PC (0x0F), request read, PC is incremented to 0x10F. The returned value = 0x20. 3- Read the content of the memory location 0x20 : the data memory address bus ← 0x20 and requests a read. Store the returned value in MDR register. 4- Add one to the MDR register. 5- Store MDR and memory location 0x20 : the data memory address bus ← 0x20, the data memory data bus ← content of MDR , and requests a write. 1 - 43 Instruction dbnz 0x21, loop (machine code is D5 21 0A) - Decrement memory location at 0x21 and branch if the contents of 0x21 is not zero yet
1- Fetch: The program memory address bus ← PC. Request a read operation. PC is incremented to 0x11. 2- The opcode (0xD5) requests reading two more read operations to fetch a byte of data memory address and a byte of branch offset . PC is incremented to 0x13. 0x21 and 0x0A are held in IR 3- Read the content of memory at 0x21, place it in MDR. 4- Decrement MDR by 1. Place the result on the memory location 0x21. 5- If MDR is not zero, new PC = old PC + 0x0A. Otherwise, PC is not changed.
1 - 44 Outline
1.1 Computer hardware organization
1.2 The processor
1.3 Memory system operation
1.4 Program Execution
1.5 HCS12 Microcontroller 1.5.1 CPU registers 1.5.2 Addressing modes 1.5.3 A sample of instructions The HCS12 Features
- 16-bit CPU - Operating clock frequency 25 Mhz - 0 KB to 4KB of on-chip EEPROM - 2KB to 14KB of on-chip SRAM - 32 KB to 512KB on-chip flash memory - Timer - Serial communication interfaces - 10-bit A/D converter - I/O pins to interface to I/O devices
1 - 45 Outline
1.1 Computer hardware organization
1.2 The processor
1.3 Memory system operation
1.4 Program Execution
1.5 HCS12 Microcontroller 1.5.1 CPU registers 1.5.2 Addressing modes 1.5.3 A sample of instructions Two types of registers :- 1- CPU registers : used to perform general purpose operations such as arithmetic, logic, and program flow control. 2- I/O registers : used to configure the operations of the I/O devices, to hold data transferred in and out of the devices, and to record the status of I/O operations - CPU registers do not occupy memory space. - I/O registers are treated as memory locations when they are accessed
CPU registers : - Some registers are 8 bits others are 16 bits. 1- General-purpose accumulators A and B - Both A and B are 8 bits. - Most arithmetic functions are done on them A and B can be concatenated to form a single 16-bit register accumulator referred as The D accumulator 1 - 46 The HCS12 CPU Registers
7 AB0 7 0 8-bit accumulator A and B or 15 D 0 16-bit double accumulator D
15 X 0 Index register X
15 Y 0 Index register Y
15 SP 0 Stack pointer
15 PC 0 Program counter
SXHINZVC Condition code register Carry Overflow Zero Negative I Interrupt mask Half-Carry (from bit 3) X Interrupt Mask Stop Disable 1 - 47 Figure 1.10 HCS12 CPU registers. When A changes B is unaffected and vice versa but when D changes both A and B change. 2- Index registers X and Y: 16 bits. Used to hold addresses. They are also used in several arithmetic instructions. 3- Stack pointer (SP) : 16 bits. A stack is a first-in-first-out data structure. SP points to the top byte of the stack as shown in figure. Stack grows towards lower addresses 4- Program counter : 16 bits holds the address of the next instruction to be executed.
5- Condition code register (CCR): Push 8-bit register used to Lower address Top of stack SP 1- Keep track of the program execution status. P 2- Enable and disable interrupts 3- Control the execution of conditional instructions Higher address 1 - 48 Outline
1.1 Computer hardware organization
1.2 The processor
1.3 Memory system operation
1.4 Program Execution
1.5 HCS12 Microcontroller 1.5.1 CPU registers 1.5.2 Addressing modes 1.5.3 A sample of instructions - A HCS12 instruction consists of one or two bytes of opcode and zero to five bytes of operand addressing information. - Opcode bytes specify the operation to be performed by the CPU. - The first byte of a two-byte opcode is always $18. - Addressing modes specify the operand to be operated on . - The addressing mode may specify a value , a register , or a memory location to be used as an operand.
The Basic Addressing Modes 1. Inherent 5. Relative 2. Immediate 6. Indexed 3. Direct 7. Indexed-Indirect 4. Extended 1 - 49 1- Inherent Mode - Either do not need operands or all operands are CPU registers . The instruction has only an opcode . -Operands can be detected from the opcode. The CPU does not need to access the memory to fetch operand - Examples:- INX ;IncrementX DECA ; Decrement A Clra ; clear A
2- Immediate Mode - Operands’ values are included in the instruction. - An immediate value can be 8 or 16 bits depending on the context of the instruction - An immediate value is preceded by # character 1 - 50 - Example: LDAA #$55 ; A ← $55 LDX #$1000 ;X ← $1000 movw #$10, $100 ; m[$100] ← $00 and m[$101] ← $10 ;Store the hex values $00 and $10 in the memory locations at $100 and $101
3- Direct Mode - Can specify memory locations in the range of $00 to $FF. - Only one byte is included in the instruction to specify the address. This can save program space and execution time. Examples : LDAA $20 ; A ← [$20] A = the value at memory location $0020 LDAB $40 ; B ← [$40]
LDX $20 ; XH ← [$20] X L ← [$21] 1 - 51 What would be the difference between : ldaa $45 ldaa #$45 4- Extended Mode - Same as Direct mode but with using 16-bit memory address. - Used to access any location in the 64 kB memory LDAA $4000 ; A ← [$4000] LDX $FE60 ; X ← [$FE60]:[$FE61] places the first byte in the high-order byte 5- Relative Mode - Used only by branch instructions. - A branch offset is the distance of the branch (or jump) - A short branch instruction consists of an 8-bit opcode and a signed 8-bit offset that can specify a range of -128 ~ +127. - A long branch instruction consists of an 8-bit opcode and a signed 16-bit offset that can specify a range of -32768 ~ +32767. 1 - 52 - Each conditional instruction tests certain status bits in the condition code register. - If the bits are in a specified state, the offset is added to PC and the execution continues at that address - If the bits are not in the specified state, the execution continues with the instruction next to the branch instruction. - A programmer uses a label to specify the branch target and the assembler will figure out the actual branch offset and add it to the machine instruction. This makes programming easier and readable.
- Example: minus … … bmi minus ;go to minus if N flag in CCR register= 1
1 - 53 6- Indexed Mode 6.1 Indexed with constant offset 6.2 Indexed with a data register (accumulator) offset 6.3 Indexed with auto pre-/post-increment/decrement of index register 6.4 Indexed-Indirect 6.4.1 Indexed-Indirect with a constant and index register 6.4.2 Indexed-Indirect with a D register and index register
6.1 Indexed with constant offset - The address of an operand = a base register + an offset - The base register can be (X, Y, PC, or SP) - The offset can be a 5-bit, 9-bit, and 16-bit signed value.
5-bit Constant Offset : - The range of the offset is from -16 to +15. - ldaa 4, X ; A ←[4+[X]] 1 - 54 Load A with the content of the memory location at address X+4 ldaa 0,X ; A = [0 + [X]] stab -8,X ; Store b at memory location X - 8
9-bit Constant Offset Indexed Addressing - The range of the offset is from -256 to +255. ldaa $FF,X ldab -20,Y ldd 100, Y A = [100+[Y]], B = [101+[Y]] 16-bit Constant Offset Indexed Addressing - This mode allows access any location in the 64-KB range. ldaa 2000, X staa 4000, Y
6.2 Indexed with a data register (accumulator) offset - The operand address = accumulator + base index register. - The accumulator can be A, B, or D
- The base index register can be X, Y, SP, or PC. 1 - 55 - Examples: ldaa B,X ;load A with the content of memory location X+B stab B,Y ldy D, X Ldx D, SP ;X ←[[D]+[SP]]:[1+[D]+[SP]] ;2 bytes are loaded into X staa B, X ;m[[B]+[X]] ←[A] store A in the memory location with address equal to X+B
6.3 Indexed with auto pre-/post-increment/decrement of index register - The base register r can be X, Y, or SP. (No PC ) - New r = old r + (or -) n - n is the amount of decrement or increment. It is in the ranges -8 thru -1 or 1 thru 8. - Post-decrement/increment: Operand address = old r
- Pre-decrement/increment: Operand address = new r 1 - 56 Effective New value of Syntax Example Comment address base register n, -r [r]-n [r]-n std 2, -SP predecrement n, +r [r]+n [r]+n ldd 2, +SP Preincrement n, r- [r] [r]-n std 2, X- Postdecrement n, r+ [r] [r]+n std 2, Y+ Postincrement
- Examples: Assume X has the value $1000
staa 2, -X ;[1000-2=$9FE] ← A X ← 1000-2=$9FE ldaa 2, +X ; [1000+2=$1002] ← A; X ← 1000+2=1002
sty 2, X- ; YH ← [$1000] and Y H ← [1001], X ← 1000-2=$9FE ldaa 4, X+ ; A ← [$1000], X = 1004
1 - 57 6.4 Indexed-Indirect - The sum of the base register and offset does not point at the operand address but to the address of memory location where the operand address can be found (address of address )
6.4.1 16-bit Offset Indirect Indexed Addressing - Syntax of the addressing mode is [n, r] - n is 16 bit offset - r is base register X, Y, SP, PC - The operand address = the content of the memory location at n + r - The square brackets distinguish this addressing mode from the 16-bit constant offset indexing .
- If X = $1000, X + 10 = $100A ldaa [10, X] - It reads 16 bits in the locations $100A and next one $100B. Assume this value is $2000 - A = the value stored in location $2000 1 - 58 6.4.2 Accumulator D Indirect Indexed Addressing - The syntax of this addressing mode is [D, r] - r is base register, X, Y, SP, or PC - The operand address is stored in the memory location D + r - Example: Go To statement
jmp [D, PC] ; PC points to go1 instruction go1 dc.w target1 ; if D =0; jump to go1 and then target1 go2 dc.w target2 ; if D =2; jump to go2 and then target2 go3 dc.w target3 ; if D =4; jump to go3 and then target3 … target1 … . target2 … . target3 …
Notice: dc.w reserves two bytes to hold the location of the symbol that follows 1 - 59 How this piece of code is useful ? The locations of target1, target2, and target 3 are known at the time of program execution, but the target of the jmp depends on the value of D that is computed during program execution or received from user.
- For example: In a calculator program, If user enters 1, 2, or 3, this should be equivalent to add, sub, or square operations. - Add, sub, or square code can be written at target1, target2, and target3 respectively. - This piece of code can be used to execute the operation requested by user.
What is the difference between :- ldaa 10, X
ldaa [10, X] 1 - 60 1 - 61 Outline
1.1 Computer hardware organization
1.2 The processor
1.3 Memory system operation
1.4 Program Execution
1.5 HCS12 Microcontroller 1.5.1 CPU registers 1.5.2 Addressing modes 1.5.3 A sample of instructions What to keep in mind when using instructions: - How does the instruction affect registers and/or memory? - How does the instruction affect the CCR? - Is it clear where the input numbers are and where the results (destination) should go? - Is the program using signed numbers? - What kind of addressing modes are available for a particular instruction?
1- The LOAD and STORE Instructions - The LOAD instruction copies the content of a memory location or an immediate value to an accumulator or a CPU register . - Memory contents are not changed. - STORE instructions copies a CPU register into a memory location . The register contents are not changed -N and Z flags of the CCR register are automatically updated
and the V flag is cleared. 1 - 62 - For load: All except for the relative mode can be used to select the memory location or value to be loaded into an accumulator or CPU register. - For store, all except for the relative and immediate modes can be used to select memory location to store contents of the CPU register.
- Examples: ldaa 0, X ;A = the content of the memory location pointed by X+0 staa $20 ;store the content of A in the memory location $20 stx $8000 ;store the content of register X in memory location at $8000 and $8001 ldd #100 ldab $1004 ;B = the content of $1004 ldx #$6000 ;X = $6000 this can be the beginning address of an array ldd 0, X ;read the fist two bytes in the array ldd 2, X ;read the second two bytes in the array 1 - 63 1 - 64 2- Transfer Instruction - Transfer instructions copy the contents of a CPU register or accumulator into another CPU register or accumulator . Source register is not changed - The TAB (transfer A to B) and TBA (transfer B to A) instructions affect the N, Z, and V condition code bits. -The TFR instruction does not affect any condition code bits. - For example, TFR D,X ; [D] ⇒ X TFR A,B ; [A] ⇒ B TFR X,A ; X[7:0] ⇒ A, lower 8 bits of X are copied to A TFR A,X ; A is signed extended to 16-bit and assigned to X - When transferring from a 8-bit register to a 16-bit register, the 8-bit register is signed extended to 16 bits. - To extend a positive number, add zeros on the left
- To extend a negative number, add ones on the left 1 - 65 3- The exchange instruction - The EXG instruction swaps the contents of a pair of registers or accumulators. - For example: exg A, B exg D,X exg A,X ; A ← X[7:0], X ← $00:[A] Unsigned Exchange 8- ← ← bits register with 16 bits exg X,B ; X $00:[B], B X[7:0] one
- Signed Exchange
SEX A,X
Copies the contents of A in the lower byte and duplicates the bit 7 of A to every bit of the of the upper byte of X
1 - 66 1 - 67 4- Move Instructions - Move data bytes or words from a source to a destination. - The source can be immediate values , index registers addressed memory , or memory location. - The destination can be index registers addressed memory or memory locations. - Notice I/O register is considered as a memory location. - Example: movb $1000, $2000 ; Copies the byte at memory location $1000 to the memory location at $2000 movw 0,X, 0,Y ; Transfer 16 bit word pointed by X to the location pointed by Y
1 - 68 5- Add and Subtract Instructions
- The destinations are always a CPU register or accumulator. - There are two-operand and three-operand versions of these instructions. - Three-operand ADD or SUB instructions: - Always include the C flag as one of the operand. - Used to perform multi-precision addition or subtraction. - For example, adda $1000 ; A ⇐ [A] + [$1000] adca $1000 ; A ⇐ [A] + [$1000] + C suba $1002 ; A ⇐ [A] + [$1002] sbca $1000 ; A ⇐ [A] - [$1000] - C
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To compute the squared value in A:- tab ;[A] →B mul ;[A] x [B] →A:B 1 - 72 Questions
Mohamed Mahmoud