EC 413 Computer Organization

Applications & Algorithms Programming Language Compiler Operating System Firmware ISA Processor Memory organization I/O system Datapath & Control Digital Design Circuit Design Layout Department of Electrical & Computer Engineering

1 Another System View We are building some AI will soon take very smart systems ! over the world! This is lot of fun, Albert!!!

Instruction Set Architecture (ISA) § Instructions are the language the computer understand § Instruction Set is the vocabulary of that language § It serves as the hardware/software interface § Defines data types § byte, int, float, double, string, vector… § Defines set of programmer visible state § Known as the programmer’s model of the machine § Defines instruction semantics (operations, sequencing) § operand location: register, immediate, indirect, . . . § add, sub, mul, move, compare, … Department of Electrical & Computer Engineering

Instruction Set Architecture (ISA) § Instructions are the language the computer understand § Instruction Set is the vocabulary of that language § It serves as the hardware/software interface § Defines instruction format (bit encoding) § Number of explicit operands per instruction § Operand location § Number of bits per instruction § Instruction length: fixed, short, long, or variable., … § Examples: RISC-V, MIPS, Alpha, x86, IBM 360, VAX, ARM, JVM

2 Instruction Set Architecture (ISA) § Many possible implementations of the same ISA § 360 implementations: model 30 (c. 1964), z900 (c. 2001) § x86 implementations: 8086 (c. 1978), 80186, 286, 386, 486, Pentium, Pentium Pro, Pentium-4, Core i7, AMD Athlon, AMD Opteron, Transmeta Crusoe, SoftPC § MIPS implementations: R2000, R4000, R10000, ... § JVM: HotSpot, PicoJava, ARM Jazelle, ... § RISC-V: RV32I, RV32E, RV64I, RV128I, … § Open-Source

Instruction Set Architecture (ISA) § Many possible implementations of the same ISA § ISA classes: Stack, Accumulator, and General- purpose register § Most current systems use general-purpose register (GPR) based ISA

Instruction Set Architecture (ISA) § Four principles are used in designing instruction set architecture: 1. Simplicity favors regularity § Total number of instructions in the instruction set 2. Smaller is faster § Number of addressable registers § Large number of registers increases access time 3. Good design demands good compromise § Computer designer must balance the programmer’s desire for more registers with the need to minimize access time 4. Make the common case fast

3 Instruction Set Architecture (ISA) § Instructions can be divided into 3 classes 1. Data movement instructions § Move data from a memory location or register to another memory location or register without changing its form § Load—source is memory and destination is register § Store—source is register and destination is memory § lw a4, 36(s0) 2. Arithmetic and logic (ALU) instructions § Change the form of one or more operands to produce a result stored in another location

Instruction Set Architecture (ISA) § Instructions can be divided into 3 classes 1. Data movement instructions 2. Arithmetic and logic (ALU) instructions § Change the form of one or more operands to produce a result stored in another location § Add, Sub, Shift, etc. § add x5,x6,x5 3. Branch instructions (control flow instructions)

Instruction Set Architecture (ISA) § Instructions can be divided into 3 classes 1. Data movement instructions 2. Arithmetic and logic (ALU) instructions 3. Branch instructions (control flow instructions) § Alter the normal flow of control from executing the next instruction in sequence § beqz x1, else

4 Instruction Set Architecture (ISA) § The instruction format § Size and meaning of fields within the instruction § Operation to perform § add rd,rs1,rs2 § Op code § add, load (lw), branch (j), etc. § Where to find the operands § rd,rs1,rs2 § Place to store result § rd § Common Instruction Formats

Instruction Set Architecture (ISA) § The instruction format § Common Instruction Formats § OPCODE + 0 addresses § OPCODE + 1 (usually a memory address) § OPCODE + 2 (registers, or register + memory address) § OPCODE + 3 (registers, or combinations of registers and memory)

Types of ISA Accumulator: 1-address add A Acc ß Acc + Mem[A] Stack: 0-address add ToS ß ToS + Next Memory-Memory: 2-address add A, B Mem[A] ß Mem[A] + Mem[B] 3-address add A, B, C Mem[A] ß Mem[B] + Mem[C] Register-Memory: 2-address add R1, A R1 ß R1 + Mem[A] load R1, A R1 ß Mem[A] Register-Register (Load/Store): 3-address add R1, R2, R3 R1 ß R2 + R3 load R1, R2 R1 ß Mem[R2] store R1, R2 Mem[R1] ß R2 Department of Electrical & Computer Engineering

5 ISA Complexity § Less operands leads to shorter decode time and longer programs § More operands implies complex operations that require longer decode time § Complex operations raises complexity of ISA but shorter programs § Metrics for measuring the ISA’s effectiveness: § Main memory space occupied by a program § Instruction length (in bits) and complexity § Total number of instructions in the instruction set

ISA and Performance § Instructions per program depends on source code, compiler technology and ISA § Cycles per instructions (CPI) depends upon the ISA and the microarchitecture § Time per cycle depends upon the microarchitecture and the base technology

Instruction Distribution SPEC2000 Int SPEC2000 FP Load 26% 15% Store 10% 2% Add 19% 23% Compare 5% 2% Cond br 12% 4% Cond mv 2% 0% Jump 1% 0% LOGIC 18% 4% FP load 15% FP store 7% FP others 19%

Reduced Instruction Set Computer § Relatively few number of instructions (~50) § Basic instructions § Relatively few different addressing modes § Fixed length instruction format § Only load/store instructions can access memory § Large number of registers § Hardwired rather than micro-program control

Reduced Instruction Set Computer § Simpler to design § Higher Performance § Smaller die size § Lower power consumption § Easier to develop compilers to take advantage of all features § Simple code generation § Regularity in CPI

7 Reduced Instruction Set Computer § RISC ISA is extensively used for desktop, server, and embedded: RISC-V, MIP S , PowerPC, UltraSPARC, ARM, MIPS16, Thumb § Apple iPods (custom ARM7TDMI SoC) § Apple iPhone (Samsung ARM1176JZF) § Palm and PocketPC PDAs and smartphones (Intel XScale family, Samsung SC32442 - ARM9) § Nintendo Game Boy Advance (ARM7) § Nintendo DS (ARM7, ARM9) § RISC-V

Reduced Instruction Set Computer § Disadvantages § Higher instruction counts § Lower instruction density § Put a greater burden on the software or system programmer

Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Small code sizes § Specialized complex instructions § Multi-clock instructions § Many different addressing modes § Including specialized modes for indexing through arrays

8 Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Including specialized modes for indexing through arrays § 12 addressing modes available in x86 § Immediate, Register operand, Displacement, Base, Base with displacement, Scaled index with displacement, Base with index and displacement, Base scaled index with displacement and Relative

Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Variable length instruction format

0 or 1 0 or 1 0 or 1 0 or 1 Bytes Instruction Segment Operand size Address size Prefix Override Override Override

0, 1, 2, 3, or 4 bytes 1 or 2 0 or 1 0 or 1 0, 1, 2 or 4 0, 1, 2 or 4 Instruction Prefixes Opcode ModR/M SIB Displacement Immediate

Mod Reg/Opcode R/M 7 6 5 4 3 2 1 0 Department of Electrical & Computer Engineering

Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Variable length instruction format § Examples : 68000, 80x86, VAX, PDP-11

9 Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Variable length instruction format § General advantages § Each instruction is more capable § Fewer instructions needed to implement a given task § More efficient use of slow main memory

Complex Instruction Set Computer § No extra load in accessing data in memory § Easy encoding § Operands being not equivalent § Restricted number of registers due to encoding memory address § Irregularity in CPI

Complex Instruction Set Computer § Disadvantages § Backward compatibility means with each new generation of computers instruction set and hardware become more and more complex § Individual instructions could be of almost any length § Different instructions will take different amounts of clock time to execute § Slows down the overall performance of the machine § Many specialized instructions are not used frequently enough to justify their existence

10 Complex Instruction Set Computer § Disadvantages § Many specialized instructions are not used frequently enough to justify their existence § Approximately 20% of the available instructions are used in a typical program § CISC instructions typically set the condition codes as a side effect of the instruction § Setting the condition codes take time § Programmers must remember to examine the condition code bits before a subsequent instruction changes them

CISC: x86 § x86 instruction set architecture (ISA) § IA-32: Intel Architecture 32-bit (i386) § Intel 80386 microprocessors in 1985 § Traditional Registers in X86 § General Purpose Registers § Pseudo General Purpose Registers § Stack: SP (stack pointer), BP (base pointer) § Strings: SI (source index), DI (destination index)

11 CISC: x86 § x86 instruction set architecture (ISA) § IA-32: Intel Architecture 32-bit (i386) § Intel 80386 microprocessors in 1985 § Traditional Registers in X86 § General Purpose Registers § Pseudo General Purpose Registers § Special Purpose Registers § IP (instruction pointer) and EFLAGS

CISC: x86 § EFLAGS § CF – Carry Flag § Set by arithmetic instructions that generate a carry or borrow § ZF – Zero Flag § Set if the result of the arithmetic operation is zero § SF – Sign Flag § On signed operands it indicates if the result is positive or negative § OF – Overflow Flag § Set this flag to indicate that the result was at least 1 bit too large to fit in the destination

CISC: x86 § The x86-64 architecture is a 64-bit superset of the 32-bit x86 instruction set architecture § x86-64 was designed by AMD who named it AMD64 § It has been cloned by Intel under the name Intel 64 § All instructions in the x86 instruction set can be executed by x86-64 CPUs § GPRs are extended to 16 § x86-64 should not be confused with the Intel Itanium architecture known as IA-64

12 CISC: x86 § GPR usage ‣ AX ← Accumulator (arithmetic) ‣ BX ← Base (memory addressing) ‣ CX ← Counter (loops) ‣ DX ← Data (data manipulation) § Modern extensions § “E” prefix for 32 bit variants → EAX, ESP § “R” prefix for 64 bit variants → RAX, RSP EAX

CISC: x86 § Registers usage conventions § Caller-save registers - eax, edx, ecx § The caller is responsible for saving the value before a call to a subroutine, and restoring the value after the call returns § Callee-save registers - ebp, ebx, esi, edi § If the callee needs to use more registers than are saved by the caller, the callee is responsible for making sure the values are stored/restored

: #include 8048374: 8d 4c 24 04 lea 0x4(%esp),%ecx 8048378: 83 e4 f0 and $0xfffffff0,%esp 804837b: ff 71 fc pushl -0x4(%ecx) int main(){ 804837e: 55 push %ebp 804837f: 89 e5 mov %esp,%ebp 8048381: 51 push %ecx printf(“Hello World!\n”); 8048382: 83 ec 04 sub $0x4,%esp 8048385: c7 04 24 60 84 04 08 movl $0x8048460,(%esp) 804838c: e8 43 ff ff ff call 80482d4 return 0x1234; 8048391: b8 2a 00 00 00 mov $0x1234,%eax 8048396: 83 c4 04 add $0x4,%esp } 8048399: 59 pop %ecx 804839a: 5d pop %ebp …

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13 80x86 Instruction Frequency Rank Instruction Frequency 1 load 22% 2 branch 20% 3 compare 16% 4 store 12% 5 add 8% 6 and 6% 7 sub 5% 8 register move 4%

9 9 call 1% 10 return 1% Total 96%

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CISC & RISC Summary Year Instr. Instr. Addr Registers Size Modes IBM 1973 208 2 - 6 4 16 370/168 VAX 1978 303 2 - 57 22 16 11/780 I 80486 1989 235 1 - 11 11 8 M 88000 1988 51 4 3 32 MIPS 1991 94 4 1 32 R4000 IBM 6000 1990 184 4 2 32

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Next Class § RISC-V ISA & Assembly Language

Department of Electrical & Computer Engineering