DOCSLIB.ORG

EC 413 Computer Organization

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
EC 413 Computer Organization EC 413 Computer Organization Instruction Set Architecture (ISA) Prof. Michel A. Kinsy Department of Electrical & Computer Engineering Full Ecosystem View Applications & Algorithms Programming Language Compiler Operating System Firmware ISA Processor Memory organization I/O system Datapath & Control Digital Design Circuit Design Layout Department of Electrical & Computer Engineering Another System View Software Instruction Set Hardware Department of Electrical & Computer Engineering 1 Another System View We are building some AI will soon take very smart systems ! over the world! This is lot of fun, Albert!!! Software Instruction Set Hardware Sure! That’s easy for you to say!!! Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Instructions are the language the computer understand § Instruction Set is the vocabulary of that language § It serves as the hardware/software interface § Defines data types § byte, int, float, double, string, vector… § Defines set of programmer visible state § Known as the programmer’s model of the machine § Defines instruction semantics (operations, sequencing) § operand location: register, immediate, indirect, . § add, sub, mul, move, compare, … Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Instructions are the language the computer understand § Instruction Set is the vocabulary of that language § It serves as the hardware/software interface § Defines instruction format (bit encoding) § Number of explicit operands per instruction § Operand location § Number of bits per instruction § Instruction length: fixed, short, long, or variable., … § Examples: RISC-V, MIPS, Alpha, x86, IBM 360, VAX, ARM, JVM Department of Electrical & Computer Engineering 2 Instruction Set Architecture (ISA) § Many possible implementations of the same ISA § 360 implementations: model 30 (c. 1964), z900 (c. 2001) § x86 implementations: 8086 (c. 1978), 80186, 286, 386, 486, Pentium, Pentium Pro, Pentium-4, Core i7, AMD Athlon, AMD Opteron, Transmeta Crusoe, SoftPC § MIPS implementations: R2000, R4000, R10000, ... § JVM: HotSpot, PicoJava, ARM Jazelle, ... § RISC-V: RV32I, RV32E, RV64I, RV128I, … § Open-Source Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Many possible implementations of the same ISA § ISA classes: Stack, Accumulator, and General- purpose register § Most current systems use general-purpose register (GPR) based ISA Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Four principles are used in designing instruction set architecture: 1. Simplicity favors regularity § Total number of instructions in the instruction set 2. Smaller is faster § Number of addressable registers § Large number of registers increases access time 3. Good design demands good compromise § Computer designer must balance the programmer’s desire for more registers with the need to minimize access time 4. Make the common case fast Department of Electrical & Computer Engineering 3 Instruction Set Architecture (ISA) § Instructions can be divided into 3 classes 1. Data movement instructions § Move data from a memory location or register to another memory location or register without changing its form § Load—source is memory and destination is register § Store—source is register and destination is memory § lw a4, 36(s0) 2. Arithmetic and logic (ALU) instructions § Change the form of one or more operands to produce a result stored in another location Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Instructions can be divided into 3 classes 1. Data movement instructions 2. Arithmetic and logic (ALU) instructions § Change the form of one or more operands to produce a result stored in another location § Add, Sub, Shift, etc. § add x5,x6,x5 3. Branch instructions (control flow instructions) Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Instructions can be divided into 3 classes 1. Data movement instructions 2. Arithmetic and logic (ALU) instructions 3. Branch instructions (control flow instructions) § Alter the normal flow of control from executing the next instruction in sequence § beqz x1, else Department of Electrical & Computer Engineering 4 Instruction Set Architecture (ISA) § The instruction format § Size and meaning of fields within the instruction § Operation to perform § add rd,rs1,rs2 § Op code § add, load (lw), branch (j), etc. § Where to find the operands § rd,rs1,rs2 § Place to store result § rd § Common Instruction Formats Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § The instruction format § Common Instruction Formats § OPCODE + 0 addresses § OPCODE + 1 (usually a memory address) § OPCODE + 2 (registers, or register + memory address) § OPCODE + 3 (registers, or combinations of registers and memory) Department of Electrical & Computer Engineering Types of ISA Accumulator: 1-address add A Acc ß Acc + Mem[A] Stack: 0-address add ToS ß ToS + Next Memory-Memory: 2-address add A, B Mem[A] ß Mem[A] + Mem[B] 3-address add A, B, C Mem[A] ß Mem[B] + Mem[C] Register-Memory: 2-address add R1, A R1 ß R1 + Mem[A] load R1, A R1 ß Mem[A] Register-Register (Load/Store): 3-address add R1, R2, R3 R1 ß R2 + R3 load R1, R2 R1 ß Mem[R2] store R1, R2 Mem[R1] ß R2 Department of Electrical & Computer Engineering 5 ISA Complexity § Less operands leads to shorter decode time and longer programs § More operands implies complex operations that require longer decode time § Complex operations raises complexity of ISA but shorter programs § Metrics for measuring the ISA’s effectiveness: § Main memory space occupied by a program § Instruction length (in bits) and complexity § Total number of instructions in the instruction set Department of Electrical & Computer Engineering ISA and Performance § Instructions per program depends on source code, compiler technology and ISA § Cycles per instructions (CPI) depends upon the ISA and the microarchitecture § Time per cycle depends upon the microarchitecture and the base technology Time = Instructions Cycles Time Program Program * Instruction * Cycle Department of Electrical & Computer Engineering Instruction Distribution SPEC2000 Int SPEC2000 FP Load 26% 15% Store 10% 2% Add 19% 23% Compare 5% 2% Cond br 12% 4% Cond mv 2% 0% Jump 1% 0% LOGIC 18% 4% FP load 15% FP store 7% FP others 19% Department of Electrical & Computer Engineering 6 RISC vs. CISC ISAs § What are the differences Department of Electrical & Computer Engineering Reduced Instruction Set Computer § Relatively few number of instructions (~50) § Basic instructions § Relatively few different addressing modes § Fixed length instruction format § Only load/store instructions can access memory § Large number of registers § Hardwired rather than micro-program control Department of Electrical & Computer Engineering Reduced Instruction Set Computer § Simpler to design § Higher Performance § Smaller die size § Lower power consumption § Easier to develop compilers to take advantage of all features § Simple code generation § Regularity in CPI Department of Electrical & Computer Engineering 7 Reduced Instruction Set Computer § RISC ISA is extensively used for desktop, server, and embedded: RISC-V, MIP S , PowerPC, UltraSPARC, ARM, MIPS16, Thumb § Apple iPods (custom ARM7TDMI SoC) § Apple iPhone (Samsung ARM1176JZF) § Palm and PocketPC PDAs and smartphones (Intel XScale family, Samsung SC32442 - ARM9) § Nintendo Game Boy Advance (ARM7) § Nintendo DS (ARM7, ARM9) § RISC-V Department of Electrical & Computer Engineering Reduced Instruction Set Computer § Disadvantages § Higher instruction counts § Lower instruction density § Put a greater burden on the software or system programmer Department of Electrical & Computer Engineering Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Small code sizes § Specialized complex instructions § Multi-clock instructions § Many different addressing modes § Including specialized modes for indexing through arrays Department of Electrical & Computer Engineering 8 Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Including specialized modes for indexing through arrays § 12 addressing modes available in x86 § Immediate, Register operand, Displacement, Base, Base with displacement, Scaled index with displacement, Base with index and displacement, Base scaled index with displacement and Relative Department of Electrical & Computer Engineering Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Variable length instruction format 0 or 1 0 or 1 0 or 1 0 or 1 Bytes Instruction Segment Operand size Address size Prefix Override Override Override 0, 1, 2, 3, or 4 bytes 1 or 2 0 or 1 0 or 1 0, 1, 2 or 4 0, 1, 2 or 4 Instruction Prefixes Opcode ModR/M SIB Displacement Immediate Mod Reg/Opcode R/M 7 6 5 4 3 2 1 0 Department of Electrical & Computer Engineering Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Variable length instruction format § Examples : 68000, 80x86, VAX, PDP-11 Department of Electrical & Computer Engineering 9 Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions
Load more

Recommended publications
  • E0C88 CORE CPU MANUAL NOTICE No Part of This Material May Be Reproduced Or Duplicated in Any Form Or by Any Means Without the Written Permission of Seiko Epson
    MF658-04 CMOS 8-BIT SINGLE CHIP MICROCOMPUTER E0C88 Family E0C88 CORE CPU MANUAL NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. Please note that "E0C" is the new name for the old product "SMC". If "SMC" appears in other manuals understand that it now reads "E0C". © SEIKO EPSON CORPORATION 1999 All rights reserved. CONTENTS E0C88 Core CPU Manual PREFACE This manual explains the architecture, operation and instruction of the core CPU E0C88 of the CMOS 8-bit single chip microcomputer E0C88 Family. Also, since the memory configuration and the peripheral circuit configuration is different for each device of the E0C88 Family, you should refer to the respective manuals for specific details other than the basic functions.
    [Show full text]
  • Mipspro C++ Programmer's Guide
    MIPSproTM C++ Programmer’s Guide 007–0704–150 CONTRIBUTORS Rewritten in 2002 by Jean Wilson with engineering support from John Wilkinson and editing support from Susan Wilkening. COPYRIGHT Copyright © 1995, 1999, 2002 - 2003 Silicon Graphics, Inc. All rights reserved; provided portions may be copyright in third parties, as indicated elsewhere herein. No permission is granted to copy, distribute, or create derivative works from the contents of this electronic documentation in any manner, in whole or in part, without the prior written permission of Silicon Graphics, Inc. LIMITED RIGHTS LEGEND The electronic (software) version of this document was developed at private expense; if acquired under an agreement with the USA government or any contractor thereto, it is acquired as "commercial computer software" subject to the provisions of its applicable license agreement, as specified in (a) 48 CFR 12.212 of the FAR; or, if acquired for Department of Defense units, (b) 48 CFR 227-7202 of the DoD FAR Supplement; or sections succeeding thereto. Contractor/manufacturer is Silicon Graphics, Inc., 1600 Amphitheatre Pkwy 2E, Mountain View, CA 94043-1351. TRADEMARKS AND ATTRIBUTIONS Silicon Graphics, SGI, the SGI logo, IRIX, O2, Octane, and Origin are registered trademarks and OpenMP and ProDev are trademarks of Silicon Graphics, Inc. in the United States and/or other countries worldwide. MIPS, MIPS I, MIPS II, MIPS III, MIPS IV, R2000, R3000, R4000, R4400, R4600, R5000, and R8000 are registered or unregistered trademarks and MIPSpro, R10000, R12000, R1400 are trademarks of MIPS Technologies, Inc., used under license by Silicon Graphics, Inc. Portions of this publication may have been derived from the OpenMP Language Application Program Interface Specification.
    [Show full text]
  • Cmp Instruction in Assembly Language
    Cmp Instruction In Assembly Language booby-trapsDamien pedaling sound. conjointly? Untidiest SupposableGraham precools, and uncleansed his ilexes geologisesNate shrouds globed her chokos contemptuously. espied or It works because when a short jump if the stack to fill out over an implied subtraction of assembly language is the arithmetic operation of using our point Jump if actual assembler or of assembly is correct results in sequence will stay organized. If you want to prove that will you there is cmp instruction in assembly language, sp can also accept one, it takes quite useful sample programs in game reports to. Acts as the instruction pointer should be checked for? Please switch your skills, cmp instruction cmp in assembly language. To double word register onto the next step process in assembly language equivalent to collect great quiz. The comparisons and the ip value becomes a row! Subsequent generations became new game code starts in main program plays a few different memory locations declared with. Want to switch, many commands to thumb instructions will not examine the difference between filtration and in assembly language are used as conditional jumps are calls to the call. Note that was no difference in memory operands and its corresponding comparison yielded an explicit, xor is running but also uses a perennial study guide can exit? Each question before you want to see the control flow and play this instruction cmp in assembly language? This value off this for assembly language, cmp instruction in assembly language? But shl can explicitly directed as efficient ways to compare values stored anywhere in terms indicated by cmp instruction in assembly language calling convention rules.
    [Show full text]
  • Microprocessors History of Computing Nouf Assaid
    MICROPROCESSORS HISTORY OF COMPUTING NOUF ASSAID 1 Table of Contents Introduction 2 Brief History 2 Microprocessors 7 Instruction Set Architectures 8 Von Neumann Machine 9 Microprocessor Design 12 Superscalar 13 RISC 16 CISC 20 VLIW 23 Multiprocessor 24 Future Trends in Microprocessor Design 25 2 Introduction If we take a look around us, we would be sure to find a device that uses a microprocessor in some form or the other. Microprocessors have become a part of our daily lives and it would be difficult to imagine life without them today. From digital wrist watches, to pocket calculators, from microwaves, to cars, toys, security systems, navigation, to credit cards, microprocessors are ubiquitous. All this has been made possible by remarkable developments in semiconductor technology enabling in the last 30 years, enabling the implementation of ideas that were previously beyond the average computer architect’s grasp. In this paper, we discuss the various microprocessor technologies, starting with a brief history of computing. This is followed by an in-depth look at processor architecture, design philosophies, current design trends, RISC processors and CISC processors. Finally we discuss trends and directions in microprocessor design. Brief Historical Overview Mechanical Computers A French engineer by the name of Blaise Pascal built the first working mechanical computer. This device was made completely from gears and was operated using hand cranks. This machine was capable of simple addition and subtraction, but a few years later, a German mathematician by the name of Leibniz made a similar machine that could multiply and divide as well. After about 150 years, a mathematician at Cambridge, Charles Babbage made his Difference Engine.
    [Show full text]
  • MIPS IV Instruction Set
    MIPS IV Instruction Set Revision 3.2 September, 1995 Charles Price MIPS Technologies, Inc. All Right Reserved RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and / or in similar or successor clauses in the FAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the Copyright Laws of the United States. Contractor / manufacturer is MIPS Technologies, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94039-7311. R2000, R3000, R6000, R4000, R4400, R4200, R8000, R4300 and R10000 are trademarks of MIPS Technologies, Inc. MIPS and R3000 are registered trademarks of MIPS Technologies, Inc. The information in this document is preliminary and subject to change without notice. MIPS Technologies, Inc. (MTI) reserves the right to change any portion of the product described herein to improve function or design. MTI does not assume liability arising out of the application or use of any product or circuit described herein. Information on MIPS products is available electronically: (a) Through the World Wide Web. Point your WWW client to: http://www.mips.com (b) Through ftp from the internet site “sgigate.sgi.com”. Login as “ftp” or “anonymous” and then cd to the directory “pub/doc”. (c) Through an automated FAX service: Inside the USA toll free: (800) 446-6477 (800-IGO-MIPS) Outside the USA: (415) 688-4321 (call from a FAX machine) MIPS Technologies, Inc.
    [Show full text]
  • MIPS Architecture • MIPS (Microprocessor Without Interlocked Pipeline Stages) • MIPS Computer Systems Inc
    Spring 2011 Prof. Hyesoon Kim MIPS Architecture • MIPS (Microprocessor without interlocked pipeline stages) • MIPS Computer Systems Inc. • Developed from Stanford • MIPS architecture usages • 1990’s – R2000, R3000, R4000, Motorola 68000 family • Playstation, Playstation 2, Sony PSP handheld, Nintendo 64 console • Android • Shift to SOC http://en.wikipedia.org/wiki/MIPS_architecture • MIPS R4000 CPU core • Floating point and vector floating point co-processors • 3D-CG extended instruction sets • Graphics – 3D curved surface and other 3D functionality – Hardware clipping, compressed texture handling • R4300 (embedded version) – Nintendo-64 http://www.digitaltrends.com/gaming/sony- announces-playstation-portable-specs/ Not Yet out • Google TV: an Android-based software service that lets users switch between their TV content and Web applications such as Netflix and Amazon Video on Demand • GoogleTV : search capabilities. • High stream data? • Internet accesses? • Multi-threading, SMP design • High graphics processors • Several CODEC – Hardware vs. Software • Displaying frame buffer e.g) 1080p resolution: 1920 (H) x 1080 (V) color depth: 4 bytes/pixel 4*1920*1080 ~= 8.3MB 8.3MB * 60Hz=498MB/sec • Started from 32-bit • Later 64-bit • microMIPS: 16-bit compression version (similar to ARM thumb) • SIMD additions-64 bit floating points • User Defined Instructions (UDIs) coprocessors • All self-modified code • Allow unaligned accesses http://www.spiritus-temporis.com/mips-architecture/ • 32 64-bit general purpose registers (GPRs) • A pair of special-purpose registers to hold the results of integer multiply, divide, and multiply-accumulate operations (HI and LO) – HI—Multiply and Divide register higher result – LO—Multiply and Divide register lower result • a special-purpose program counter (PC), • A MIPS64 processor always produces a 64-bit result • 32 floating point registers (FPRs).
    [Show full text]
  • Mi!!Lxlosalamos SCIENTIFIC LABORATORY
    LA=8902-MS C3b ClC-l 4 REPORT COLLECTION REPRODUCTION COPY VAXNMS Benchmarking 1-’ > .— u) 9 g .— mi!!lxLOS ALAMOS SCIENTIFIC LABORATORY Post Office Box 1663 Los Alamos. New Mexico 87545 — wAifiimative Action/Equal Opportunity Employer b . l)lS(”L,\l\ll K “Thisreport wm prcpmd J, an xcttunt ,,1”wurk ,pmwrd by an dgmcy d the tlnitwl SIdtcs (kvcm. mm:. Ncit her t hc llniml SIJIL.. ( Lwcrnmcm nor any .gcncy tlhmd. nor my 08”Ihcif cmployccs. makci my wur,nly. mprcss w mphd. or JwImL.s m> lcg.d Iululity ur rcspmuhdily ltw Ilw w.cur- acy. .vmplctcncs. w uscftthtc>. ttt”any ml’ormdt ml. dpprdl us. prudu.i. w proccw didowd. or rep. resent%Ihd IIS us wuukl not mfrm$e priwtcly mvnd rqdtts. Itcl”crmcti herein 10 my sp.xi!l tom. mrcial ptotlucr. prtxcm. or S.rvskc hy tdc mmw. Irdcnmrl.. nmu(a.lurm. or dwrwi~.. does nut mmwsuily mnstitutc or reply its mdursmwnt. rccummcnddton. or favorin: by the llniwd States (“mvcmment ormy qxncy thctcd. rhc V!C$VSmd opinmm d .mthor% qmxd herein do nut net’. UMrily r;~lt or died lhow. ol”the llnttcd SIJIL.S( ;ovwnnwnt or my ugcncy lhure of. UNITED STATES .. DEPARTMENT OF ENERGY CONTRACT W-7405 -ENG. 36 . ... LA-8902-MS UC-32 Issued: July 1981 G- . VAX/VMS Benchmarking Larry Creel —. I . .._- -- ----- ,. .- .-. .: .- ,.. .. ., ..,..: , .. .., . ... ..... - .-, ..:. .. *._–: - . VAX/VMS BENCHMARKING by Larry Creel ABSTRACT Primary emphasis in this report is on the perform- ance of three Digital Equipment Corporation VAX-11/780 computers at the Los Alamos National Laboratory. Programs used in the study are part of the Laboratory’s set of benchmark programs.
    [Show full text]
  • IDT79R4600 and IDT79R4700 RISC Processor Hardware User's Manual
    IDT79R4600™ and IDT79R4700™ RISC Processor Hardware User’s Manual Revision 2.0 April 1995 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any respon- sibility for use of any circuitry described other than the circuitry embodied in an IDT product. ITD makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights, or other rights of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology’s products are not authorized for use as critical components in life sup- port devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accor- dance with instructions for use provided in the labeling, can be reasonably expected to result in a sig- nificant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
    [Show full text]
  • (PSW). Seven Bits Remain Unused While the Rest Nine Are Used
    8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI The Flags Register It is a 16-bit register, also called Program Status Word (PSW). Seven bits remain unused while the rest nine are used. Six are status flags and three are control flags. The control flags can be set/reset by the programmer. 1. DF (Direction Flag) : controls the direction of operation of string instructions. (DF=0 Ascending order DF=1 Descending order) 2. IF (Interrupt Flag): controls the interrupt operation in 8086µP. (IF=0 Disable interrupt IF=1 Enable interrupt) 3. TF (Trap Flag): controls the operation of the microprocessor. (TF=0 Normal operation TF=1 Single Step operation) The status flags are set/reset depending on the results of some arithmetic or logical operations during program execution. 1. CF (Carry Flag) is set (CF=1) if there is a carry out of the MSB position resulting from an addition operation or subtraction. 2. AF (Auxiliary Carry Flag) AF is set if there is a carry out of bit 3 resulting from an addition operation. 3. SF (Sign Flag) set to 1 when result is negative. When result is positive it is set to 0. 4. ZF (Zero Flag) is set (ZF=1) when result of an arithmetic or logical operation is zero. For non-zero result this flag is reset (ZF=0). 5. PF (Parity Flag) this flag is set to 1 when there is even number of one bits in result, and to 0 when there is odd number of one bits. 6. OF (Overflow Flag) set to 1 when there is a signed overflow.
    [Show full text]
  • Instruction Set Architecture
    The Instruction Set Architecture Application Instruction Set Architecture OiOperating Compiler System Instruction Set Architecture Instr. Set Proc. I/O system or Digital Design “How to talk to computers if Circuit Design you aren’t on Star Trek” CSE 240A Dean Tullsen CSE 240A Dean Tullsen How to Sppmpeak Computer Crafting an ISA High Level Language temp = v[k]; • Designing an ISA is both an art and a science Program v[k] = v[k+ 1]; v[k+1] = temp; • ISA design involves dealing in an extremely rare resource Compiler – instruction bits! lw $15, 0($2) AblLAssembly Language lw $16, 4($2) • Some things we want out of our ISA Program sw $16, 0($2) – completeness sw $15, 4($2) Assembler – orthogonality 1000110001100010000000000000000 – regularity and simplicity Machine Language 1000110011110010000000000000100 – compactness Program 1010110011110010000000000000000 – ease of ppgrogramming 1010110001100010000000000000100 Machine Interpretation – ease of implementation Control Signal Spec ALUOP[0:3] <= InstReg[9:11] & MASK CSE 240A Dean Tullsen CSE 240A Dean Tullsen Where are the instructions? KKyey ISA decisions • Harvard architecture • Von Neumann architecture destination operand operation • operations y = x + b – how many? inst & source operands inst cpu data – which ones storage storage operands cpu • data “stored-program” computer – how many? storage – location – types – how to specify? how does the computer know what L1 • instruction format 0001 0100 1101 1111 inst – size means? cache L2 cpu Mem cache – how many formats? L1 dtdata cache CSE
    [Show full text]
  • AVR Control Transfer -AVR Branching
    1 | P a g e AVR Control Transfer -AVR Branching Reading The AVR Microcontroller and Embedded Systems using Assembly and C) by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi Chapter 3: Branch, Call, and Time Delay Loop Section 3.1: Branching and Looping (Branch Only) Additional Reading Introduction to AVR assembler programming for beginners, controlling sequential execution of the program http://www.avr-asm-tutorial.net/avr_en/beginner/JUMP.html AVR Assembler User Guide http://www.atmel.com/dyn/resources/prod documents/doc1022.pdf 2 | P a g e TABLE OF CONTENTS Instruction Set Architecture (Review) ...................................................................................................................... 4 Instruction Set (Review) ........................................................................................................................................... 5 Jump Instructions..................................................................................................................................................... 6 How the Direct Unconditional Control Transfer Instructions jmp and call Work ...................................................... 7 How the Relative Unconditional Control Transfer Instructions rjmp and rcall Work ................................................ 8 Branch Instructions .................................................................................................................................................. 9 How the Relative Conditional Control Transfer Instruction
    [Show full text]
  • Overview of IA-32 Assembly Programming
    Overview of IA-32 assembly programming Lars Ailo Bongo University of Tromsø Contents 1 Introduction ...................................................................................................................... 2 2 IA-32 assembly programming.......................................................................................... 3 2.1 Assembly Language Statements................................................................................ 3 2.1 Modes........................................................................................................................4 2.2 Registers....................................................................................................................4 2.2.3 Data Registers .................................................................................................... 4 2.2.4 Pointer and Index Registers................................................................................ 4 2.2.5 Control Registers................................................................................................ 5 2.2.6 Segment registers ............................................................................................... 7 2.3 Addressing................................................................................................................. 7 2.3.1 Bit and Byte Order ............................................................................................. 7 2.3.2 Data Types.........................................................................................................
    [Show full text]