E0C88 CORE CPU MANUAL NOTICE No Part of This Material May Be Reproduced Or Duplicated in Any Form Or by Any Means Without the Written Permission of Seiko Epson
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MF658-04 CMOS 8-BIT SINGLE CHIP MICROCOMPUTER E0C88 Family E0C88 CORE CPU MANUAL NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. Please note that "E0C" is the new name for the old product "SMC". If "SMC" appears in other manuals understand that it now reads "E0C". © SEIKO EPSON CORPORATION 1999 All rights reserved. CONTENTS E0C88 Core CPU Manual PREFACE This manual explains the architecture, operation and instruction of the core CPU E0C88 of the CMOS 8-bit single chip microcomputer E0C88 Family. Also, since the memory configuration and the peripheral circuit configuration is different for each device of the E0C88 Family, you should refer to the respective manuals for specific details other than the basic functions. CONTENTS 1 OUTLINE ____________________________________________________ 1 1.1 Features .................................................................................................................... 1 1.2 Instruction Set Features ........................................................................................... 1 1.3 Block Diagram ......................................................................................................... 1 1.4 Input-Output Signal .................................................................................................. 2 2 ARCHITECTURE ______________________________________________ 4 2.1 Address Space and CPU Model ............................................................................... 4 2.2 ALU and Registers.................................................................................................... 5 2.2.1 ALU ................................................................................................................. 5 2.2.2 Register configuration .................................................................................... 5 2.2.3 Flags ............................................................................................................... 6 2.2.4 Complimentary operation and overflow ......................................................... 8 2.2.5 Decimal operation and unpack operation ..................................................... 10 2.2.6 Multiplication and division ............................................................................ 11 2.3 Program Memory .................................................................................................... 12 2.3.1 Configuration of the program memory .......................................................... 12 2.3.2 PC (Program counter) and CB (Code bank register) ................................... 13 2.3.3 Bank management .......................................................................................... 14 2.3.4 Branch instruction ......................................................................................... 14 2.4 Data Memory ........................................................................................................... 17 2.4.1 Data memory configuration ........................................................................... 17 2.4.2 Page registers EP, XP, YP ............................................................................. 18 2.4.3 Stack ............................................................................................................... 18 2.4.4 Memory mapped I/O ...................................................................................... 20 3 CPU OPERATION AND PROCESSING STATUS ____________________ 21 3.1 Timing Generator and Bus Control......................................................................... 21 3.1.1 Bus cycle ........................................................................................................ 21 3.1.2 Wait state ....................................................................................................... 22 3.2 Outline of Processing Statuses ................................................................................ 23 3.3 Reset Status.............................................................................................................. 24 3.4 Program Execution Status ....................................................................................... 25 3.5 Exception Processing Status ................................................................................... 25 3.5.1 Exception processing types and priority........................................................ 26 3.5.2 Exception processing factor and vectors ....................................................... 27 3.5.3 Interrupts ....................................................................................................... 27 3.5.4 Exception processing sequence ..................................................................... 28 E0C88 CORE CPU MANUAL EPSON i CONTENTS 3.6 Bus Authority Release Status ................................................................................... 31 3.7 Standby Status ......................................................................................................... 33 3.7.1 HALT status ................................................................................................... 33 3.7.2 SLEEP status ................................................................................................. 34 4 INSTRUCTION SETS ___________________________________________ 35 4.1 Addressing Mode ..................................................................................................... 35 4.2 Instruction Format .................................................................................................. 39 4.3 Instruction Set List................................................................................................... 40 4.3.1 Function classification .................................................................................. 40 4.3.2 Symbol meanings ........................................................................................... 41 4.3.3 Instruction list by functions ........................................................................... 42 4.4 Detailed Explanation of Instructions ...................................................................... 59 APPENDIX A Operation Code Map ________________________________ 195 B Instruction List by Addressing Mode ___________________ 198 C Instruction Index ___________________________________ 210 White ii EPSON E0C88 CORE CPU MANUAL 1 OUTLINE 1 OUTLINE The E0C88 is the core CPU of the 8-bit single chip microcomputer E0C88 Family that utilizes original EPSON architecture. It has a maximum 16M bytes address space and high speed, abundant instruction sets. It handles a wide range of operating voltages and features low power consumption. In addition, it has adopted a unified architecture and a peripheral circuit interface for its memory mapped I/O mode to flexibly meet future expansion of the E0C88 Family. 1.1 Features 1.2 Instruction Set Features The E0C88 boasts the below features. (1) It adopts high efficiency machine cycle plus Address space Maximum 16M bytes high speed and abundant instruction sets. (2) Memory management can be done easily by 12 Instruction cycle 1–15 cycles (1 cycle = 2 clocks) types of addressing modes. Instruction set 608 types (3) It has effective 16 bit operation functions including address calculation. Register configuration Data registers 2 Index registers 3 (4) It includes powerful decimal operation func- (One is used as a data register) tions such as a decimal operation mode and Program counter pack/unpack instruction. Stack pointer (5) It supports the realization of various types of System condition flag special service microcomputers through Customize condition flag customized flag instructions. Exception processing factors Reset, zero division and (6) It is composed of an instruction system that interrupt enables relocatable programming, thus permit- Exception processing vectors Maximum 128 vectors ting easy development of software libraries. Standby function HALT/SLEEP 1.3 Block Diagram Peripheral circuit interface Memory mapped I/O system Figure 1.3.1 shows the E0C88 block diagram. B A H L IX TEMP 1 TEMP 0 IY 8-bit Single Chip Microcomputer ALU SP Core CPU E0C88 PC SC TEMP 2 BR LR Micro Instruction Instruction Instruction Decoder Register EP Internal Data Bus (16-bit) XP CC YP System Clock CB Code Power Timing Bus System Interrupt Status Address Supply Generator Controler Controler Controler Controler Generator NB DD SS PL PK SR RD