EC 413 Computer Organization Instruction Set Architecture (ISA) Prof. Michel A. Kinsy Department of Electrical & Computer Engineering Full Ecosystem View Applications & Algorithms Programming Language Compiler Operating System Firmware ISA Processor Memory organization I/O system Datapath & Control Digital Design Circuit Design Layout Department of Electrical & Computer Engineering Another System View Software Instruction Set Hardware Department of Electrical & Computer Engineering 1 Another System View We are building some AI will soon take very smart systems ! over the world! This is lot of fun, Albert!!! Software Instruction Set Hardware Sure! That’s easy for you to say!!! Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Instructions are the language the computer understand § Instruction Set is the vocabulary of that language § It serves as the hardware/software interface § Defines data types § byte, int, float, double, string, vector… § Defines set of programmer visible state § Known as the programmer’s model of the machine § Defines instruction semantics (operations, sequencing) § operand location: register, immediate, indirect, . § add, sub, mul, move, compare, … Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Instructions are the language the computer understand § Instruction Set is the vocabulary of that language § It serves as the hardware/software interface § Defines instruction format (bit encoding) § Number of explicit operands per instruction § Operand location § Number of bits per instruction § Instruction length: fixed, short, long, or variable., … § Examples: RISC-V, MIPS, Alpha, x86, IBM 360, VAX, ARM, JVM Department of Electrical & Computer Engineering 2 Instruction Set Architecture (ISA) § Many possible implementations of the same ISA § 360 implementations: model 30 (c. 1964), z900 (c. 2001) § x86 implementations: 8086 (c. 1978), 80186, 286, 386, 486, Pentium, Pentium Pro, Pentium-4, Core i7, AMD Athlon, AMD Opteron, Transmeta Crusoe, SoftPC § MIPS implementations: R2000, R4000, R10000, ... § JVM: HotSpot, PicoJava, ARM Jazelle, ... § RISC-V: RV32I, RV32E, RV64I, RV128I, … § Open-Source Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Many possible implementations of the same ISA § ISA classes: Stack, Accumulator, and General- purpose register § Most current systems use general-purpose register (GPR) based ISA Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Four principles are used in designing instruction set architecture: 1. Simplicity favors regularity § Total number of instructions in the instruction set 2. Smaller is faster § Number of addressable registers § Large number of registers increases access time 3. Good design demands good compromise § Computer designer must balance the programmer’s desire for more registers with the need to minimize access time 4. Make the common case fast Department of Electrical & Computer Engineering 3 Instruction Set Architecture (ISA) § Instructions can be divided into 3 classes 1. Data movement instructions § Move data from a memory location or register to another memory location or register without changing its form § Load—source is memory and destination is register § Store—source is register and destination is memory § lw a4, 36(s0) 2. Arithmetic and logic (ALU) instructions § Change the form of one or more operands to produce a result stored in another location Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Instructions can be divided into 3 classes 1. Data movement instructions 2. Arithmetic and logic (ALU) instructions § Change the form of one or more operands to produce a result stored in another location § Add, Sub, Shift, etc. § add x5,x6,x5 3. Branch instructions (control flow instructions) Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § Instructions can be divided into 3 classes 1. Data movement instructions 2. Arithmetic and logic (ALU) instructions 3. Branch instructions (control flow instructions) § Alter the normal flow of control from executing the next instruction in sequence § beqz x1, else Department of Electrical & Computer Engineering 4 Instruction Set Architecture (ISA) § The instruction format § Size and meaning of fields within the instruction § Operation to perform § add rd,rs1,rs2 § Op code § add, load (lw), branch (j), etc. § Where to find the operands § rd,rs1,rs2 § Place to store result § rd § Common Instruction Formats Department of Electrical & Computer Engineering Instruction Set Architecture (ISA) § The instruction format § Common Instruction Formats § OPCODE + 0 addresses § OPCODE + 1 (usually a memory address) § OPCODE + 2 (registers, or register + memory address) § OPCODE + 3 (registers, or combinations of registers and memory) Department of Electrical & Computer Engineering Types of ISA Accumulator: 1-address add A Acc ß Acc + Mem[A] Stack: 0-address add ToS ß ToS + Next Memory-Memory: 2-address add A, B Mem[A] ß Mem[A] + Mem[B] 3-address add A, B, C Mem[A] ß Mem[B] + Mem[C] Register-Memory: 2-address add R1, A R1 ß R1 + Mem[A] load R1, A R1 ß Mem[A] Register-Register (Load/Store): 3-address add R1, R2, R3 R1 ß R2 + R3 load R1, R2 R1 ß Mem[R2] store R1, R2 Mem[R1] ß R2 Department of Electrical & Computer Engineering 5 ISA Complexity § Less operands leads to shorter decode time and longer programs § More operands implies complex operations that require longer decode time § Complex operations raises complexity of ISA but shorter programs § Metrics for measuring the ISA’s effectiveness: § Main memory space occupied by a program § Instruction length (in bits) and complexity § Total number of instructions in the instruction set Department of Electrical & Computer Engineering ISA and Performance § Instructions per program depends on source code, compiler technology and ISA § Cycles per instructions (CPI) depends upon the ISA and the microarchitecture § Time per cycle depends upon the microarchitecture and the base technology Time = Instructions Cycles Time Program Program * Instruction * Cycle Department of Electrical & Computer Engineering Instruction Distribution SPEC2000 Int SPEC2000 FP Load 26% 15% Store 10% 2% Add 19% 23% Compare 5% 2% Cond br 12% 4% Cond mv 2% 0% Jump 1% 0% LOGIC 18% 4% FP load 15% FP store 7% FP others 19% Department of Electrical & Computer Engineering 6 RISC vs. CISC ISAs § What are the differences Department of Electrical & Computer Engineering Reduced Instruction Set Computer § Relatively few number of instructions (~50) § Basic instructions § Relatively few different addressing modes § Fixed length instruction format § Only load/store instructions can access memory § Large number of registers § Hardwired rather than micro-program control Department of Electrical & Computer Engineering Reduced Instruction Set Computer § Simpler to design § Higher Performance § Smaller die size § Lower power consumption § Easier to develop compilers to take advantage of all features § Simple code generation § Regularity in CPI Department of Electrical & Computer Engineering 7 Reduced Instruction Set Computer § RISC ISA is extensively used for desktop, server, and embedded: RISC-V, MIP S , PowerPC, UltraSPARC, ARM, MIPS16, Thumb § Apple iPods (custom ARM7TDMI SoC) § Apple iPhone (Samsung ARM1176JZF) § Palm and PocketPC PDAs and smartphones (Intel XScale family, Samsung SC32442 - ARM9) § Nintendo Game Boy Advance (ARM7) § Nintendo DS (ARM7, ARM9) § RISC-V Department of Electrical & Computer Engineering Reduced Instruction Set Computer § Disadvantages § Higher instruction counts § Lower instruction density § Put a greater burden on the software or system programmer Department of Electrical & Computer Engineering Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Small code sizes § Specialized complex instructions § Multi-clock instructions § Many different addressing modes § Including specialized modes for indexing through arrays Department of Electrical & Computer Engineering 8 Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Including specialized modes for indexing through arrays § 12 addressing modes available in x86 § Immediate, Register operand, Displacement, Base, Base with displacement, Scaled index with displacement, Base with index and displacement, Base scaled index with displacement and Relative Department of Electrical & Computer Engineering Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Variable length instruction format 0 or 1 0 or 1 0 or 1 0 or 1 Bytes Instruction Segment Operand size Address size Prefix Override Override Override 0, 1, 2, 3, or 4 bytes 1 or 2 0 or 1 0 or 1 0, 1, 2 or 4 0, 1, 2 or 4 Instruction Prefixes Opcode ModR/M SIB Displacement Immediate Mod Reg/Opcode R/M 7 6 5 4 3 2 1 0 Department of Electrical & Computer Engineering Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions § Many different addressing modes § Variable length instruction format § Examples : 68000, 80x86, VAX, PDP-11 Department of Electrical & Computer Engineering 9 Complex Instruction Set Computer § Large number of instructions (~200-300 instructions) § Specialized complex instructions