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RISC and CISC Computer Architecture COLLEGE OF ELECTRICAL AND MECHANICAL ENGINEERING NATIONAL UNIVERSITY OF SCIENCES AND TECHNOLOGY (NUST) RISC AND CISC Computer Architecture By Farhat Masood BE – Electrical (NUST) II [RISC AND CISC] TABLE OF CONTENTS GENERAL ............................................................................................................................................... 1 ADDRESSING MODES IN CISC ............................................................................................................ 1 EVOLUTION OF RISC............................................................................................................................ 1 DEFINITION OF RISC ............................................................................................................................ 2 NON RISC DESIGN OR PRE RISC DESIGN ........................................................................................ 4 TYPICAL CHARACTERISTICS OF RISC ARCHITECTURE ................................................................ 5 RISC VS CISC – AN EXAMPLE ............................................................................................................ 7 THE CISC APPROACH.. .................................................................................................................... 7 THE RISC APPROACH. ..................................................................................................................... 8 ANALYSIS. ......................................................................................................................................... 9 THE PERFORMANCE EQUATION. ................................................................................................. 10 THE OVERALL RISC ADVANTAGE ................................................................................................ 10 RISC PROCESSORS (EXAMPLES) .................................................................................................... 11 DIGITAL EQUIPMENT CORPORATION (DEC) ............................................................................... 11 ADVANCED MICRO DEVICES (AMD) 29000. ................................................................................. 11 ADVANCED RISC MACHINE (ARM). .............................................................................................. 12 ATMEL AVR. .................................................................................................................................... 13 MICROPROCESSOR WITHOUT INTERLOCKED PIPELINE STAGES (MIPS) ............................. 13 PRECISION ARCHITECTURE – REDUCED INSTRUCTION SET COMPUTER (PA-RISC) .......... 14 PERFORMANCE OPTIMIZATION WITH ENHANCED RISC – PERFORMANCE COMPUTING (POWER-PC). ................................................................................................................................... 15 SUPERH. .......................................................................................................................................... 15 SCALABLE PROCESSOR ARCHITECTURE (SPARC). ................................................................ 17 CONCLUSION ...................................................................................................................................... 17 III [RISC AND CISC] LIST OF FIGURES FIGURE 1 TYPICAL RISC ARCHITECTURE BASED MACHINE - INSTRUCTION PHASE OVERLAPPING -------------- 2 FIGURE 2 ADVANCED RISC MACHINE (ARM) --------------------------------------------------------------------------- 3 FIGURE 3 TYPICAL CISC ARCHITECTURE – STACK DESIGN ----------------------------------------------------------- 4 FIGURE 4 REPRESENTATION OF STORAGE SCHEME FOR A GENERIC COMPUTER ---------------------------------- 7 FIGURE 5 DEC ALPHA MICROPROCESSOR DEVELOPED IN 1995 ---------------------------------------------------- 11 FIGURE 6 ADVANCED MICRO DEVICES (AMD) MICROPROCESSOR 29000 SERIES ------------------------------- 12 FIGURE 7 ADVANCED RISC MACHINE (ARM) MICROPROCESSOR DEVELOPED BY CONEXANT COMPUTERS 13 FIGURE 8 ATMEL AVR ATMEGA8 MICROPROCESSOR ---------------------------------------------------------------- 13 FIGURE 9 MIPS MICROPROCESSOR -------------------------------------------------------------------------------------- 14 FIGURE 10 HP 9000 PA-RISC MICROPROCESSOR ------------------------------------------------------------------- 15 FIGURE 11 POWERPC 600 SERIES DEVELOPED BY IBM COMPUTER ----------------------------------------------- 15 FIGURE 12 SUPERH MICROPROCESSOR --------------------------------------------------------------------------------- 16 FIGURE 13 SPARC II MICROPROCESSOR DEVELOPED BY SUN ------------------------------------------------------ 17 1 [RISC AND CISC] RISC AND CISC Generali 1. The dominant architecture in the PC market, the Intel IA-32, belongs to the Complex Instruction Set Computer (CISC) design. The obvious reason for this classification is the “complex” nature of its Instruction Set Architecture (ISA). The motivation for designing such complex instruction sets is to provide an instruction set that closely supports the operations and data structures used by Higher-Level Languages (HLLs). However, the side effects of this design effort are far too serious to ignore. Addressing Modes in CISC 2. The decision of CISC processor designers to provide a variety of addressing modes leads to variable-length instructions. For example, instruction length increases if an operand is in memory as opposed to in a register. a. This is because we have to specify the memory address as part of instruction encoding, which takes many more bits. b. This complicates instruction decoding and scheduling. The side effect of providing a wide range of instruction types is that the number of clocks required to execute instructions varies widely. c. This again leads to problems in instruction scheduling and pipelining. Evolution of RISCii 3. For these and other reasons, in the early 1980s designers started looking at simple ISAs. Because these ISAs tend to produce instruction sets with far fewer instructions, they coined the term Reduced Instruction Set Computer (RISC). Even though the main goal was not to reduce the number of instructions, but the complexity, the term has stuck. 4. There is no precise definition of what constitutes a RISC design. However, we can identify certain characteristics that are present in most RISC systems. 2 [RISC AND CISC] a. We identify these RISC design principles after looking at why the designers took the route of CISC in the first place. b. Because CISC and RISC have their advantages and disadvantages, modern processors take features from both classes. For example, the PowerPC, which follows the RISC philosophy, has quite a few complex instructions. Figure 1 Typical RISC Architecture based Machine - Instruction phase overlapping Definition of RISCiii 5. RISC, or Reduced Instruction Set Computer is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. a. Evolution/History. The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford 3 [RISC AND CISC] MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors (1) One Cycle Execution Time. RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called ; (2) Pipelining. A technique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions; (3) Large Number of Registers. The RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory Figure 2 Advanced RISC Machine (ARM) 4 [RISC AND CISC] Non RISC Design or Pre RISC Designiv 6. In the early days of the computer industry, programming was done in assembly language or machine code, which encouraged powerful and easy to use instructions. CPU designers therefore tried to make instructions that would do as much work as possible. With the advent of higher level languages, computer architects also started to create dedicated instructions to directly implement certain central mechanisms of such languages. Figure 3 Typical CISC Architecture – Stack Design 7. Another general goal was to provide every possible addressing mode for every instruction, known as orthogonality, to ease compiler implementation. Arithmetic operations could therefore often have results as well as operands directly in memory (in addition to register or immediate). 8. The attitude at the time was that hardware design was more mature than compiler design so this was in itself also a reason to implement parts of the functionality in hardware and/or microcode rather than in a memory constrained 5 [RISC AND CISC] compiler (or its generated code) alone. This design philosophy became retroactively termed Complex Instruction Set Computer (CISC) after the RISC philosophy came onto the scene. 9. An important force encouraging complexity was very limited main memories (on the order of kilobytes). It was therefore advantageous for the density of information held in computer programs to be high, leading to features such as highly encoded, variable length instructions, doing data loading as well as. These issues were of higher priority than
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