Ross Technology RT6224K User Manual 1 (Pdf)
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Find the Ross Technology RT6224K-200/512S at our website: Click HERE 830-0016-03 Rev A 11/15/96 PRELIMINARY Colorado 4 RT6224K hyperSPARC CPU Module Features D Based on ROSS’ fifth-generation D SPARC compliant — Zero-wait-state, 512-Kbyte or hyperSPARC processor — SPARC Instruction Set Architec- 1-Mbyte 2nd-level cache — RT620D Central Processing Unit ture (ISA) Version 8 compliant — Demand-paged virtual memory (CPU) — Conforms to SPARC Reference management — RT626 Cache Controller, Memory MMU Architecture D Module design Management, and Tag Unit — Conforms to SPARC Level 2 MBus — MBus-standard form factor: 3.30” (CMTU) Module Specification (Revision 1.2) (8.34 cm) x 5.78” (14.67 cm) — Four (512-Kbyte) or eight D Dual-clock architecture — Provides CPU upgrade path at (1-Mbyte) RT628 Cache Data Units module level (CDUs) Ċ CPU scaleable up to 200 MHz — MBus scaleable up to 66 MHz — Advanced packaging technology Ċ IntraĆModule Bus incorporates low for a compact design voltage logic to reduce power andD Each hyperSPARC processor features D High performance * increase speed — Superscalar SPARC CPU with inte- D Full multiprocessing implementation grated floating point unit, 16-Kbyte — 224-229 SPECint92 — Hardware support for symmetric, instruction cache, and 16-Kbyte — 247-259 SPECfp92 shared-memory multiprocessing data cache * in a 66MHz MBus system — Level 2 MBus support for cache — Speculative fetch keeps primary coherency caches loaded to assure high cache hit rates RT620D CPU IMCLK OSC IMA[31:0] IMD[63:0] RT626 RT628 RT628 VOLTAGE CMTU CDU CDU REGULATOR + 5V MBus (Level 2) Figure 1. Logic Block Diagram Selection Guide Part Number: RT6224K * Ć180/512 Ć180/1024 Ć200/512 Ć200/1024 CPU Operating Frequency (MHz) 180 180 200 200 Typical Power Consumption (w)** Second-level Cache Size 512K 1M 512K 1M SPECint92 / SPECfp92 224 / 247 229 / 259 SPECrateint92 / SPECratefp92 (single processor) SPECrateint92 / SPECratefp92 (dual processor) *See Appendix C for hyperSPARC ordering information ** Commercial • ROSS Technology, Inc. • 5316 Hwy. 290 West • Austin, Texas 78735 • TEL (512) 436-2000 •FAX (512) 892-3036 1 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 830-0016-03 Rev A 11/15/96 PRELIMINARY Colorado 4 RT6224K Functional Description Component Overview The RT6224K hyperSPARC Module is a complete SPARC Superscalar SPARC Processor (RT620D) CPU, including on-board primary and secondary cache The RT620D Central Processing Unit is the heart of ROSS’ memories. It is packaged as a compact PCB and interfaces to fifth-generation of microprocessor. The RT620D CPU archi- the remainder of the system via a SPARC-standard MBus tecture employs two advanced concepts for increasing com- connector. The CPU on the RT6224K consists of a high- puter system performance: superscalability and superpipelin- speed superscalar, highly pipelined processor with dual inte- ing. ger ALUs and an on-chip floating-point unit (RT620D), a Cache Controller, Memory Management, and Tag Unit The RT620D is a high performance full-custom CMOS im- (RT626), and four (512-Kbyte cache configuration) or eight plementation of integrated SPARC integer and floating-point (1-Mbyte cache configuration) RT628 Cache Data Units. The logic, with separate on-chip instruction and data caches. RT6224K fits within the clearance envelope for MBus mod- Advanced architecture and manufacturing technologies give ules per the SPARC MBus Specification. the RT620D ultra high performance without requiring soft- The RT6224K interfaces to the rest of the system via the ware recompilation. Figure 2 is a logic block diagram of the SPARC MBus and conforms to the SPARC Reference MMU. RT620D. This standardization allows the RT6224K to be interchange- IDP. The Integer Data Path comprises several units. Two able with other SPARC MBus-based CPU modules without independent Arithmetic and Logic Units (ALUs) handle inte- having to modify any portion of the memory system or I/O. ger arithmetic, logical, and shift instructions. The Load/Store This CPU “building block” strategy not only decreases the Unit (LSU) handles instructions that load and store data be- user’s time to market, but provides a mechanism for upgrad- tween memory and registers, which includes the loading and ing in the field. storing of both integer and floating-point data. The Special IDP Special Registers Integer Registers (IREGS) Floating Point Registers (FREGS) Input Selection Input Selection Input Selection Input Selection ALU ALULDST FPADD FPMUL Align Check Align Check FPDP Floating Program Global Decoder Floating Counter Point Point Dependency Checker Queue Unit Schedule and Control Scheduler Load Store Align Align FPSCHED Exception Logic ISCHED Data Address Instruction Address Instruction Instruction Intramodule Fetch Instruction Cache Data Cache Bus Controller Interface IFETCH ICACHE DCACHE IBIU Control Address Out Data/ Control Instruction In Figure 2. RT620D CPU Logic Block Diagram 2 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com 830-0016-03 Rev A 11/15/96 PRELIMINARY Colorado 4 RT6224K Register Unit (SRU) handles instructions that read and write virtually tagged. The DCACHE uses a write through with no the SPARC Special Registers (SREGS). The Integer Register write allocate policy, with a pseudo random replacement File (IREGS) is also contained in the IDP. algorithm. One doubleword is fetched for every DCACHE FPDP. The Floating-Point Data Path also comprises several miss. To improve the hit ratio, the next speculative fetch is units. These are the Floating-Point Queue (FPQ), the Float- performed in the same cache line in the DCACHE. ing-Point Arithmetic Unit (FAU), The Floating-Point Multi- Unlike the ICACHE, the DCACHE is always a subset of the plier Unit (FMU), the Floating-Point Register File (FREGS), secondary cache. Secondary cache snoop invalidates and line and the Floating-Point Status Register (FSR). The multiplier replacements automatically cause a line in the DCACHE to unit implements full double-precision multiplies. These be invalidated. Since the DCACHE is virtually addressed and floating-point units handle all SPARC floating-point instruc- has no context information, the entire DCACHE must be tions. flushed on context switches and page remapping. Also, the ISCHED. The Integer Scheduler performs key control func- DCACHE line size may not be the same as the secondary tions. It provides global instruction decodes to identify which cache, so a flush must always use a stride of 32 bytes to assure execution unit resources are required, and determines wheth- the DCACHE is flushed completely. er sequential or simultaneous execution is possible. IBIU. The Intra-Module Bus Interface Unit provides the in- The ISCHED also determines whether data forwarding can terface between the RT620D CPU and the external world. be performed and whether instruction dispatches (also called The IBIU samples incoming control signals and propagates “launches”) need to be delayed due to data dependencies. controls to appropriate functional blocks. The IBIU is respon- The ISCHED initiates instruction launch and identifies and sible for generating memory access control signals to the controls interrupt and trap handling. cache memory subsystem. Data and instructions are read from memory and data is written to memory, through the FPSCHED. The Floating-Point Instruction Scheduler per- IBIU. forms key control functions for the floating-point unit. When the Integer Unit detects floating-point instructions in the Cache Control, Memory Management, and Tag Unit decode stage, it offloads these instructions to the floating- (RT626) point functional units and continues processing. Therefore, The CMTU (RT626) is a combined Cache Controller and functional blocks exist that perform necessary decode, sched- Memory Management Unit optimized for multiprocessing uling, and control for the floating-point operations. systems. The CMTU is a high-speed CMOS implementation of the SPARC Reference MMU, combined with cache, a The FPSCHED performs floating-point instruction decoding, memory controller, and on-chip physical cache tag memory. resolves floating-point data dependency and data-forwarding The CMTU supports the SPARC MBus Level 2 protocol for conditions, and provides the ISCHED with floating-point multiprocessing systems. Figure 3 depicts the CMTU block execution status. Delayed instructions are stored temporarily diagram. in the Floating-Point Instruction Queue (FPQ). Instructions are launched from the FPQ as data dependencies are The CMTU directly connects to the RT620D Central Proces- resolved. sing Unit and RT628 Cache Data Units without any external circuitry. The RT626 CMTU uses four or eight RT628 CDUs IFETCH. The Instruction Fetch Unit consists of two