PC Hardware Contents

Home , Bootloader, Centuri, Coreboot, EXPEED, Fli4l, GeForce 256

1 Computer hardware 1 1.1 Von Neumann architecture ...... 1 1.2 Sales ...... 1 1.3 Diﬀerent systems ...... 2 1.3.1 Personal computer ...... 2 1.3.2 Mainframe computer ...... 3 1.3.3 Departmental computing ...... 4 1.3.4 Supercomputer ...... 4 1.4 See also ...... 4 1.5 References ...... 4 1.6 External links ...... 4

2 Central processing unit 5 2.1 History ...... 5 2.1.1 Transistor and integrated circuit CPUs ...... 6 2.1.2 Microprocessors ...... 7 2.2 Operation ...... 8 2.2.1 Fetch ...... 8 2.2.2 Decode ...... 8 2.2.3 Execute ...... 9 2.3 Design and implementation ...... 9 2.3.1 Control unit ...... 9 2.3.2 Arithmetic logic unit ...... 9 2.3.3 Integer range ...... 10 2.3.4 Clock rate ...... 10 2.3.5 Parallelism ...... 11 2.4 Performance ...... 13 2.5 See also ...... 14 2.6 Notes ...... 14 2.7 References ...... 15 2.8 External links ...... 15

3 Chipset 16

i ii CONTENTS

3.1 Computers ...... 16 3.2 Move toward processor integration in PCs ...... 17 3.3 See also ...... 17 3.4 Notes ...... 17

4 Graphics processing unit 18 4.1 History ...... 18 4.1.1 1980s ...... 18 4.1.2 1990s ...... 19 4.1.3 2000 to 2006 ...... 20 4.1.4 2006 to present ...... 20 4.1.5 GPU companies ...... 20 4.2 Computational functions ...... 21 4.2.1 GPU accelerated video decoding ...... 21 4.3 GPU forms ...... 21 4.3.1 Dedicated graphics cards ...... 21 4.3.2 Integrated graphics solutions ...... 22 4.3.3 Hybrid solutions ...... 22 4.3.4 Stream Processing and General Purpose GPUs (GPGPU) ...... 23 4.3.5 External GPU (eGPU) ...... 23 4.4 Sales ...... 23 4.5 See also ...... 24 4.5.1 Hardware ...... 24 4.5.2 APIs ...... 24 4.5.3 Applications ...... 24 4.6 References ...... 24 4.7 External links ...... 25

5 Random-access memory 26 5.1 History ...... 26 5.2 Types of RAM ...... 27 5.3 Memory hierarchy ...... 28 5.4 Other uses of RAM ...... 28 5.4.1 Virtual memory ...... 28 5.4.2 RAM disk ...... 28 5.4.3 Shadow RAM ...... 28 5.5 Recent developments ...... 28 5.6 Memory wall ...... 29 5.7 See also ...... 29 5.8 Notes and references ...... 29 5.9 External links ...... 30 CONTENTS iii

6 Read-only memory 31 6.1 History ...... 31 6.1.1 Use for storing programs ...... 32 6.1.2 Use for storing data ...... 33 6.2 Types ...... 33 6.2.1 Semiconductor based ...... 33 6.2.2 Other technologies ...... 34 6.3 Speed ...... 34 6.3.1 Reading ...... 34 6.3.2 Writing ...... 34 6.4 Endurance and data retention ...... 35 6.5 Content images ...... 35 6.6 See also ...... 35 6.7 Terminology ...... 35 6.8 References ...... 35

7 BIOS 36 7.1 History ...... 36 7.2 User interface ...... 36 7.3 Operation ...... 37 7.3.1 System startup ...... 37 7.3.2 Boot process ...... 37 7.3.3 Boot environment ...... 38 7.4 Extensions (option ROMs) ...... 39 7.4.1 Boot procedure ...... 39 7.4.2 Initialization ...... 40 7.4.3 Physical placement ...... 40 7.5 Operating system services ...... 40 7.5.1 Processor microcode updates ...... 41 7.5.2 Identiﬁcation ...... 41 7.5.3 Overclocking ...... 41 7.5.4 Modern use ...... 41 7.6 Conﬁguration ...... 41 7.6.1 Setup utility ...... 41 7.6.2 Reprogramming ...... 42 7.7 Hardware ...... 42 7.8 Vendors and products ...... 43 7.9 Security ...... 43 7.10 Alternatives and successors ...... 45 7.11 See also ...... 45 7.12 Notes ...... 45 7.13 References ...... 45 iv CONTENTS

7.14 Further reading ...... 46 7.15 External links ...... 46

8 Bootstrapping 47 8.1 Etymology ...... 47 8.2 Applications ...... 47 8.2.1 Computing ...... 47 8.2.2 Research ...... 49 8.2.3 Statistics ...... 49 8.2.4 Business ...... 49 8.2.5 Biology ...... 49 8.2.6 Law ...... 49 8.2.7 Linguistics ...... 49 8.2.8 Physics ...... 49 8.2.9 Electronics ...... 49 8.2.10 Electric power grid ...... 50 8.2.11 Cellular networks ...... 50 8.2.12 Media ...... 50 8.3 See also ...... 50 8.4 References ...... 50 8.5 External links ...... 51

9 Firmware 52 9.1 Origin of the term ...... 52 9.2 Personal computers ...... 52 9.3 Consumer products ...... 53 9.4 Automobiles ...... 53 9.5 Examples ...... 53 9.6 Flashing ...... 54 9.7 Firmware hacking ...... 54 9.7.1 HDD ﬁrmware hacks ...... 54 9.8 Security risks ...... 54 9.9 See also ...... 55 9.10 References ...... 55 9.11 External links ...... 55

10 Uniﬁed Extensible Firmware Interface 56 10.1 History ...... 56 10.2 Advantages ...... 56 10.3 Compatibility ...... 57 10.3.1 Processor compatibility ...... 57 10.3.2 Disk device compatibility ...... 57 CONTENTS v

10.4 Features ...... 58 10.4.1 Services ...... 58 10.4.2 Applications ...... 58 10.4.3 Protocols ...... 58 10.4.4 Device drivers ...... 58 10.4.5 Graphics features ...... 59 10.4.6 EFI System partition ...... 59 10.4.7 Booting ...... 59 10.4.8 Compatibility Support Module ...... 60 10.4.9 UEFI shell ...... 60 10.4.10 Extensions ...... 60 10.5 Implementation and adoption ...... 60 10.5.1 Intel EFI ...... 60 10.5.2 Platforms using EFI/UEFI ...... 60 10.5.3 Operating systems ...... 61 10.5.4 Use of UEFI with virtualization ...... 62 10.6 Applications development ...... 62 10.7 Criticism ...... 62 10.7.1 Secure boot ...... 62 10.7.2 Firmware issues ...... 63 10.8 See also ...... 63 10.9 Notes ...... 63 10.10References ...... 64 10.11Further reading ...... 66 10.12External links ...... 66

11 Bus (computing) 67 11.1 Background and nomenclature ...... 67 11.1.1 Internal bus ...... 68 11.1.2 External bus ...... 68 11.2 Implementation details ...... 68 11.3 History ...... 68 11.3.1 First generation ...... 69 11.3.2 Minis and micros ...... 69 11.3.3 Second generation ...... 70 11.3.4 Third generation ...... 70 11.4 Examples of internal computer buses ...... 70 11.4.1 Parallel ...... 70 11.4.2 Serial ...... 71 11.5 Examples of external computer buses ...... 71 11.5.1 Parallel ...... 71 11.5.2 Serial ...... 71 vi CONTENTS

11.6 Examples of internal/external computer buses ...... 71 11.7 See also ...... 71 11.8 References ...... 72 11.9 External links ...... 72 11.10Text and image sources, contributors, and licenses ...... 73 11.10.1 Text ...... 73 11.10.2 Images ...... 78 11.10.3 Content license ...... 81 Chapter 1

Computer hardware

For other uses, see Hardware. 1.1 Von Neumann architecture Computer hardware (usually simply called hardware Main article: Von Neumann architecture The template for all modern computers is the Von Neu-

Von Neumann architecture scheme.

mann architecture, detailed in a 1945 paper by Hun- garian mathematician John von Neumann. This describes a design architecture for an electronic digital computer with subdivisions of a processing unit consisting of an arithmetic logic unit and processor registers, a control unit containing an instruction register and program counter, a memory to store both data and instructions, external mass storage, and input and output PDP-11 CPU board mechanisms.[3] The meaning of the term has evolved to mean a stored-program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. This is referred to as the Von Neumann bottleneck and often limits the perfor- when a computing context is implicit) is the collection [4] of physical elements that constitutes a computer system. mance of the system. Computer hardware is the physical parts or components of a computer, such as the monitor, mouse, keyboard, computer data storage, hard disk drive (HDD), system 1.2 Sales unit (graphic cards, sound cards, memory, motherboard and chips), and so on, all of which are physical objects [1] For the third consecutive year, U.S. business-to-business that can be touched (that is, they are tangible). In con- channel sales (sales through distributors and commercial trast, software is instructions that can be stored and run resellers) increased, ending 2013 up nearly 6 percent at by hardware. $1 doller. The impressive growth was the fastest sales Software is any set of machine-readable instructions that increase since the end of the recession. Sales growth ac- directs a computer’s processor to perform speciﬁc oper- celerated in the second half of the year peaking in fourth ations. A combination of hardware and software forms a quarter with a 6.9 percent increase over the fourth quarter usable computing system.[2] of 2012.[5]

1 2 CHAPTER 1. COMPUTER HARDWARE

1.3 Diﬀerent systems similar, although may use lower-power or reduced size components. There are a number of diﬀerent types of computer system in use today. Case

1.3.1 Personal computer Main article: Computer case

The computer case is a plastic or metal enclosure that houses most of the components. Those found on desktop computers are usually small enough to ﬁt under a desk, however in recent years more compact designs have become more common place, such as the all-in-one style designs from Apple, namely the iMac. Laptops are computers that usually come in a clamshell form factor, again however in more recent years deviations from this form factor have started to emerge such as laptops that have a detachable screen that become tablet computers in their own right.

Power supply

Main article: Power supply unit (computer)

A power supply unit (PSU) converts alternating current (AC) electric power to low-voltage DC power for the internal components of the computer. Laptops are capable Hardware of a modern personal computer of running from a built-in battery, normally for a period 1. Monitor 2. Motherboard 3. CPU 4. RAM 5. Expansion of hours.[6] cards 6. Power supply 7. Optical disc drive 8. Hard disk drive 9. Keyboard 10. Mouse Motherboard

Main article: Motherboard

The motherboard is the main component of computer. It is a large rectangular board with integrated circuitry that connects the other parts of the computer including the CPU, the RAM, the disk drives(CD, DVD, hard disk, or any others) as well as any peripherals connected via the ports or the expansion slots. Components directly attached to or part of the motherboard include:

• The CPU (Central Processing Unit) performs most of the calculations which enable a computer to function, and is sometimes referred to as the “brain” of the computer. It is usually cooled by a heat sink and fan. Most newer CPUs include an on-die Graphics Inside a custom-built computer: power supply at the bottom has Processing Unit (GPU). its own cooling fan. • The Chipset, which includes the north bridge, me- The personal computer, also known as the PC, is one of diates communication between the CPU and the the most common types of computer due to its versatil- other components of the system, including main ity and relatively low price. Laptops are generally very memory. 1.3. DIFFERENT SYSTEMS 3

• The Random-Access Memory (RAM) stores the Input and output peripherals code and data that are being actively accessed by the CPU. Main article: Peripheral • The Read-Only Memory (ROM) stores the BIOS that runs when the computer is powered on or Input and output devices are typically housed externally otherwise begins execution, a process known as to the main computer chassis. The following are either Bootstrapping, or "booting" or “booting up”. The standard or very common to many computer systems. BIOS (Basic Input Output System) includes boot Input firmware and power management firmware. Newer motherboards use Unified Extensible Firmware In- Input devices allow the user to enter information into the terface (UEFI) instead of BIOS. system, or control its operation. Most personal computers have a mouse and keyboard, but laptop systems typ- • Buses connect the CPU to various internal compo- ically use a touchpad instead of a mouse. Other input nents and to expansion cards for graphics and sound. devices include webcams, microphones, joysticks, and image scanners. • The CMOS battery is also attached to the mother- Output device board. This battery is the same as a watch battery Output devices display information in a human readable or a battery for a remote to a car’s central locking form. Such devices could include printers, speakers, system. Most batteries are CR2032, which powers monitors or a Braille embosser. the memory for date and time in the BIOS chip.

Expansion cards 1.3.2 Mainframe computer Main article: Expansion card

An expansion card in computing is a printed circuit board that can be inserted into an expansion slot of a computer motherboard or backplane to add functionality to a computer system via the expansion bus.

Storage devices

Main article: Computer data storage

Computer data storage, often called storage or memory, refers to computer components and recording media that retain digital data. Data storage is a core function and fundamental component of computers. Fixed media Data is stored by a computer using a variety of media. Hard disk drives are found in virtually all older computers, due to their high capacity and low cost, but solid-state drives are faster and more power efficient, although currently more expensive than hard drives, so are often found in more expensive computers. Some systems may use a disk array controller for greater performance or reliability. An IBM System z9 mainframe Removable media To transfer data between computers, a USB flash drive or A mainframe computer is a much larger computer that Optical disc may be used. Their usefulness depends on typically fills a room and may cost many hundreds or being readable by other systems; the majority of machines thousands of times as much as a personal computer. They have an optical disk drive, and virtually all have a USB are designed to perform large numbers of calculations for port. governments and large enterprises. 4 CHAPTER 1. COMPUTER HARDWARE

1.3.3 Departmental computing [6] “How long should a laptop battery last?". Computer Hope. Retrieved 9 December 2013. In the 1960s and 1970s more and more departments [7] Alba, Davey. “China’s Tianhe-2 Caps Top 10 Supercom- started to use cheaper and dedicated systems for speciﬁc puters”. IEEE. Retrieved 9 December 2013. purposes like process control and laboratory automation. Main article: Minicomputer 1.6 External links

• Media related to Computer hardware at Wikimedia 1.3.4 Supercomputer Commons

A supercomputer is superficially similar to a mainframe, • Learning materials related to Computer hardware at but is instead intended for extremely demanding compu- Wikiversity tational tasks. As of November 2013, the fastest supercomputer in the world is the Tianhe-2, in Guangzhou, • “What You Need to Know About Hardware Beta [7] China. Tests” Centercode.com The term supercomputer does not refer to a specific technology. Rather it indicates the fastest computers available at any given time. In mid 2011, the fastest supercomputers boasted speeds exceeding one petaflop, or 1000 trillion floating point operations per second. Super computers are fast but extremely costly so they are generally used by large organizations to execute computationally demanding tasks involving large data sets. Super computers typically run military and scientific applications. Although they cost millions of dollars, they are also being used for commercial applications where huge amounts of data must be analyzed. For example, large banks employ supercomputers to calculate the risks and returns of various investment strategies, and healthcare organizations use them to analyze giant databases of patient data to determine optimal treatments for various diseases and problems incurring to our country.

1.4 See also

• Open-source computing hardware

1.5 References

[1] “Parts of computer”. Microsoft. Retrieved 5 December 2013.

[2] Smither, Roger. “Use of computers in audiovisual archives”. UNESCO. Retrieved 5 December 2013.

[3] von Neumann, John (1945). “First Draft of a Report on the EDVAC”.

[4] Markgraf, Joey D. (2007). “The Von Neumann bottleneck”. Retrieved 24 August 2011.

[5] US B2B Channel sales reach nearly $62 Bil- lion in 2013, by The NPD Group: https: //www.npd.com/wps/portal/npd/us/news/press-releases/ us-b2bchannel-sales-reach-nearly-62-billion-in-2013-according-to-the-npd-group/ Chapter 2

Central processing unit

“CPU” redirects here. For other uses, see CPU (disam- unit (ALU) that performs arithmetic and logic operations, biguation). hardware registers that supply operands to the ALU and “Computer processor” redirects here. For other uses, see store the results of ALU operations, and a control unit that Processor (computing). fetches instructions from memory and “executes” them by directing the coordinated operations of the ALU, registers and other components. Most modern CPUs are microprocessors, meaning they are contained on a single integrated circuit (IC) chip. An IC that contains a CPU may also contain memory, peripheral interfaces, and other components of a computer; such integrated devices are variously called microcontrollers or systems on a chip (SoC). Some computers employ a multi-core processor, which is a single chip containing two or more CPUs called “cores"; in that context, single chips are sometimes referred to as An Intel 80486DX2 CPU, as seen from above “sockets”.[3] Array processors or vector processors have multiple processors that operate in parallel, with no unit considered central.

2.1 History

Main article: History of general purpose CPUs Computers such as the ENIAC had to be physically rewired to perform different tasks, which caused these machines to be called “fixed-program computers”.[4] Bottom side of an Intel 80486DX2 Since the term “CPU” is generally defined as a device for software (computer program) execution, the earliest devices that could rightly be called CPUs came with the A central processing unit (CPU) is the electronic cir- advent of the stored-program computer. cuitry within a computer that carries out the instructions of a computer program by performing the basic arith- The idea of a stored-program computer was already metic, logical, control and input/output (I/O) operations present in the design of J. Presper Eckert and John specified by the instructions. The term has been used in William Mauchly's ENIAC, but was initially omitted so the computer industry at least since the early 1960s.[1] that it could be finished sooner. On June 30, 1945, be- Traditionally, the term “CPU” refers to a processor and fore ENIAC was made, mathematician John von Neu- its control unit (CU), distinguishing these core elements mann distributed the paper entitled First Draft of a Re- of a computer from external components such as main port on the EDVAC. It was the outline of a stored-program memory and I/O circuitry.[2] computer that would eventually be completed in August 1949.[5] EDVAC was designed to perform a certain num- The form, design and implementation of CPUs have ber of instructions (or operations) of various types. Sig- changed over the course of their history, but their fun- nificantly, the programs written for EDVAC were to be damental operation remains almost unchanged. Princi- stored in high-speed computer memory rather than spec- pal components of a CPU include the arithmetic logic ified by the physical wiring of the computer. This over-

5 6 CHAPTER 2. CENTRAL PROCESSING UNIT

called Harvard architecture of the Harvard Mark I, which was completed before EDVAC, also utilized a stored- program design using punched paper tape rather than electronic memory. The key difference between the von Neumann and Harvard architectures is that the latter sep- arates the storage and treatment of CPU instructions and data, while the former uses the same memory space for both. Most modern CPUs are primarily von Neumann in design, but CPUs with the Harvard architecture are seen as well, especially in embedded applications; for instance, the Atmel AVR microcontrollers are Harvard architecture processors. Relays and vacuum tubes (thermionic valves) were commonly used as switching elements; a useful computer requires thousands or tens of thousands of switching devices. The overall speed of a system is dependent on the speed of the switches. Tube computers like EDVAC tended to average eight hours between failures, whereas relay computers like the (slower, but earlier) Harvard Mark I failed very rarely.[1] In the end, tube-based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems. Most of these early synchronous CPUs ran at low EDVAC, one of the first stored-program computers. clock rates compared to modern microelectronic designs (see below for a discussion of clock rate). Clock signal frequencies ranging from 100 kHz to 4 MHz were very came a severe limitation of ENIAC, which was the con- common at this time, limited largely by the speed of the siderable time and effort required to reconfigure the com- switching devices they were built with. puter to perform a new task. With von Neumann’s design, the program, or software, that EDVAC ran could be 2.1.1 Transistor and integrated circuit changed simply by changing the contents of the memory. EDVAC, however, was not the first stored-program com- CPUs puter; the Manchester Small-Scale Experimental Ma- chine, a small prototype stored-program computer, ran its first program on 21 June 1948[6] and the Manchester Mark 1 ran its first program during the night of 16–17 June 1949. Early CPUs were custom-designed as a part of a larger, sometimes one-of-a-kind, computer. However, this method of designing custom CPUs for a particular application has largely given way to the development of mass- produced processors that are made for many purposes. This standardization began in the era of discrete transistor mainframes and minicomputers and has rapidly accelerated with the popularization of the integrated circuit (IC). The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of CPU, core memory, and external bus interface of a DEC PDP- nanometers. Both the miniaturization and standardiza- 8/I. Made of medium-scale integrated circuits. tion of CPUs have increased the presence of digital devices in modern life far beyond the limited application The design complexity of CPUs increased as various of dedicated computing machines. Modern microproces- technologies facilitated building smaller and more reli- sors appear in everything from automobiles to cell phones able electronic devices. The first such improvement came and children’s toys. with the advent of the transistor. Transistorized CPUs While von Neumann is most often credited with the de- during the 1950s and 1960s no longer had to be built out sign of the stored-program computer because of his de- of bulky, unreliable, and fragile switching elements like sign of EDVAC, others before him, such as Konrad Zuse, vacuum tubes and electrical relays. With this improve- had suggested and implemented similar ideas. The so- ment more complex and reliable CPUs were built onto 2.1. HISTORY 7

one or several printed circuit boards containing discrete the era of specialized supercomputers like those made by (individual) components. Cray Inc. During this period, a method of manufacturing many interconnected transistors in a compact space was de- 2.1.2 Microprocessors veloped. The integrated circuit (IC) allowed a large number of transistors to be manufactured on a single Main article: Microprocessor semiconductor-based die, or “chip”. At first only very basic non-specialized digital circuits such as NOR gates were miniaturized into ICs. CPUs based upon these “building block” ICs are generally referred to as “small- scale integration” (SSI) devices. SSI ICs, such as the ones used in the Apollo guidance computer, usually contained up to a few score transistors. To build an entire CPU out of SSI ICs required thousands of individual chips, but still consumed much less space and power than earlier discrete transistor designs. As microelectronic technology advanced, an increasing number of transistors were placed on ICs, thus decreasing the quantity of individual ICs Die of an Intel 80486DX2 microprocessor (actual size: needed for a complete CPU. MSI and LSI (medium- and 12×6.75 mm) in its packaging large-scale integration) ICs increased transistor counts to hundreds, and then thousands. In 1964, IBM introduced its System/360 computer architecture that was used in a series of computers capable of running the same programs with different speed and performance. This was significant at a time when most electronic computers were incompatible with one another, even those made by the same manufacturer. To facilitate this improvement, IBM utilized the concept of a microprogram (often called “microcode”), which still sees widespread usage in modern CPUs.[7] The Sys- tem/360 architecture was so popular that it dominated the Intel Core i5 CPU on a Vaio E series laptop motherboard mainframe computer market for decades and left a legacy (on the right, beneath the heat pipe). that is still continued by similar modern computers like the IBM zSeries. In the same year (1964), Digital Equip- In the 1970s the fundamental inventions by Federico ment Corporation (DEC) introduced another influential Faggin (Silicon Gate MOS ICs with self-aligned gates computer aimed at the scientific and research markets, along with his new random logic design methodology) the PDP-8. DEC would later introduce the extremely changed the design and implementation of CPUs for- popular PDP-11 line that originally was built with SSI ever. Since the introduction of the first commercially ICs but was eventually implemented with LSI compo- available microprocessor (the Intel 4004) in 1970, and nents once these became practical. In stark contrast with the first widely used microprocessor (the Intel 8080) in its SSI and MSI predecessors, the first LSI implementa- 1974, this class of CPUs has almost completely overtaken tion of the PDP-11 contained a CPU composed of only all other central processing unit implementation methods. [8] four LSI integrated circuits. Mainframe and minicomputer manufacturers of the time Transistor-based computers had several distinct advan- launched proprietary IC development programs to up- tages over their predecessors. Aside from facilitating in- grade their older computer architectures, and eventually creased reliability and lower power consumption, transis- produced instruction set compatible microprocessors that tors also allowed CPUs to operate at much higher speeds were backward-compatible with their older hardware and because of the short switching time of a transistor in com- software. Combined with the advent and eventual suc- parison to a tube or relay. Thanks to both the increased cess of the ubiquitous personal computer, the term CPU reliability as well as the dramatically increased speed of is now applied almost exclusively[lower-alpha 1] to micropro- the switching elements (which were almost exclusively cessors. Several CPUs (denoted 'cores’) can be combined transistors by this time), CPU clock rates in the tens of in a single processing chip. megahertz were obtained during this period. Addition- Previous generations of CPUs were implemented as ally while discrete transistor and IC CPUs were in heavy discrete components and numerous small integrated cir- usage, new high-performance designs like SIMD (Single cuits (ICs) on one or more circuit boards. Microproces- Instruction Multiple Data) vector processors began to ap- sors, on the other hand, are CPUs manufactured on a very pear. These early experimental designs later gave rise to small number of ICs; usually just one. The overall smaller 8 CHAPTER 2. CENTRAL PROCESSING UNIT

CPU size, as a result of being implemented on a single functions.[lower-alpha 3] In some processors, some other in- die, means faster switching time because of physical fac- structions change the state of bits in a “flags” register. tors like decreased gate parasitic capacitance. This has These flags can be used to influence how a program be- allowed synchronous microprocessors to have clock rates haves, since they often indicate the outcome of various ranging from tens of megahertz to several gigahertz. Ad- operations. For example, in such processors a “compare” ditionally, as the ability to construct exceedingly small instruction evaluates two values and sets or clears bits transistors on an IC has increased, the complexity and in the flags register to indicate which one is greater or number of transistors in a single CPU has increased many whether they are equal; one of these flags could then be fold. This widely observed trend is described by Moore’s used by a later jump instruction to determine program law, which has proven to be a fairly accurate predictor of flow. the growth of CPU (and other IC) complexity.[9] While the complexity, size, construction, and general form of CPUs have changed enormously since 1950, it is notable that the basic design and function has not 2.2.1 Fetch changed much at all. Almost all common CPUs today can be very accurately described as von Neumann stored-program machines.[lower-alpha 2] As the aforemen- The first step, fetch, involves retrieving an instruction tioned Moore’s law continues to hold true,[9] concerns (which is represented by a number or sequence of num- have arisen about the limits of integrated circuit transistor bers) from program memory. The instruction’s location technology. Extreme miniaturization of electronic gates (address) in program memory is determined by a program is causing the effects of phenomena like electromigration counter (PC), which stores a number that identifies the and subthreshold leakage to become much more signifi- address of the next instruction to be fetched. After an in- cant. These newer concerns are among the many factors struction is fetched, the PC is incremented by the length causing researchers to investigate new methods of com- of the instruction so that it will contain the address of the [lower-alpha 4] puting such as the quantum computer, as well as to ex- next instruction in the sequence. Often, the in- pand the usage of parallelism and other methods that ex- struction to be fetched must be retrieved from relatively tend the usefulness of the classical von Neumann model. slow memory, causing the CPU to stall while waiting for the instruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below). 2.2 Operation

The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of 2.2.2 Decode stored instructions called a program. The instructions are kept in some kind of computer memory. There are three The instruction that the CPU fetches from memory de- steps that nearly all CPUs use in their operation: fetch, termines what the CPU has to do. In the decode step, the decode, and execute. instruction is broken up into parts that have significance After the execution of an instruction, the entire process to other portions of the CPU. The way in which the nu- repeats, with the next instruction cycle normally fetch- merical instruction value is interpreted is defined by the ing the next-in-sequence instruction because of the in- CPU’s instruction set architecture (ISA).[lower-alpha 5] Of- cremented value in the program counter. If a jump in- ten, one group of numbers in the instruction, called the struction was executed, the program counter will be mod- opcode, indicates which operation to perform. The re- ified to contain the address of the instruction that was maining parts of the number usually provide information jumped to and program execution continues normally. required for that instruction, such as operands for an addi- In more complex CPUs, multiple instructions can be tion operation. Such operands may be given as a constant fetched, decoded, and executed simultaneously. This sec- value (called an immediate value), or as a place to locate tion describes what is generally referred to as the "classic a value: a register or a memory address, as determined RISC pipeline", which is quite common among the sim- by some addressing mode. ple CPUs used in many electronic devices (often called In some CPU designs the instruction decoder is imple- microcontroller). It largely ignores the important role of mented as a hardwired, unchangeable circuit. In others, CPU cache, and therefore the access stage of the pipeline. a microprogram is used to translate instructions into sets Some instructions manipulate the program counter rather of CPU configuration signals that are applied sequentially than producing result data directly; such instructions are over multiple clock pulses. In some cases the memory generally called “jumps” and facilitate program behav- that stores the microprogram is rewritable, making it pos- ior like loops, conditional program execution (through sible to change the way in which the CPU decodes in- the use of a conditional jump), and existence of structions. 2.3. DESIGN AND IMPLEMENTATION 9

2.2.3 Execute A complete machine language instruction consists of an opcode and, in many cases, additional bits that specify ar- After the fetch and decode steps, the execute step is per- guments for the operation (for example, the numbers to formed. Depending on the CPU architecture, this may be summed in the case of an addition operation). Going consist of a single action or a sequence of actions. Dur- up the complexity scale, a machine language program is a ing each action, various parts of the CPU are electrically collection of machine language instructions that the CPU connected so they can perform all or part of the desired executes. operation and then the action is completed, typically in The actual mathematical operation for each instruction response to a clock pulse. Very often the results are writ- is performed by a combinational logic circuit within the ten to an internal CPU register for quick access by subse- CPU’s processor known as the arithmetic logic unit or quent instructions. In other cases results may be written ALU. In general, a CPU executes an instruction by fetch- to slower, but less expensive and higher capacity main ing it from memory, using its ALU to perform an op- memory. eration, and then storing the result to memory. Beside For example, if an addition instruction is to be executed, the instructions for integer mathematics and logic oper- the arithmetic logic unit (ALU) inputs are connected to ations, various other machine instructions exists, such as a pair of operand sources (numbers to be summed), the those for loading data from memory and storing it back, ALU is configured to perform an addition operation so branching operations, and mathematical operations on that the sum of its operand inputs will appear at its out- floating-point numbers performed by the CPU’s floating- put, and the ALU output is connected to storage (e.g., a point unit (FPU).[10] register or memory) that will receive the sum. When the clock pulse occurs, the sum will be transferred to storage and, if the resulting sum is too large (i.e., it is larger than 2.3.1 Control unit the ALU’s output word size), an arithmetic overflow flag will be set. Main article: Control unit

The control unit of the CPU contains circuitry that uses 2.3 Design and implementation electrical signals to direct the entire computer system to carry out stored program instructions. The control unit Main article: CPU design does not execute program instructions; rather, it directs Hardwired into a CPU’s circuitry is a set of basic oper- other parts of the system to do so. The control unit com- municates with both the ALU and memory.

2.3.2 Arithmetic logic unit

Main article: Arithmetic logic unit The arithmetic logic unit (ALU) is a digital circuit within

Block diagram of a basic uniprocessor-CPU computer. Black lines indicate data flow, whereas red lines indicate control flow; arrows indicate flow directions. Symbolic representation of an ALU and its input and output sig- ations it can perform, called an instruction set. Such op- nals erations may involve, for example, adding or subtracting two numbers, comparing two numbers, or jumping to a the processor that performs integer arithmetic and bitwise different part of a program. Each basic operation is rep- logic operations. The inputs to the ALU are the data resented by a particular combination of bits, known as words to be operated on (called operands), status infor- the machine language opcode; while executing instruc- mation from previous operations, and a code from the tions in a machine language program, the CPU decides control unit indicating which operation to perform. De- which operation to perform by “decoding” the opcode. pending on the instruction being executed, the operands 10 CHAPTER 2. CENTRAL PROCESSING UNIT

may come from internal CPU registers or external mem- quired, however, the benefits of a larger word size (larger ory, or they may be constants generated by the ALU itself. data ranges and address spaces) may outweigh the disad- When all input signals have settled and propagated vantages. through the ALU circuitry, the result of the performed To gain some of the advantages afforded by both lower operation appears at the ALU’s outputs. The result con- and higher bit lengths, many CPUs are designed with sists of both a data word, which may be stored in a reg- different bit widths for different portions of the device. ister or memory, and status information that is typically For example, the IBM System/370 used a CPU that was stored in a special, internal CPU register reserved for this primarily 32 bit, but it used 128-bit precision inside its purpose. floating point units to facilitate greater accuracy and range in floating point numbers.[7] Many later CPU designs use similar mixed bit width, especially when the processor is 2.3.3 Integer range meant for general-purpose usage where a reasonable bal- ance of integer and floating point capability is required. Every CPU represents numerical values in a specific way. For example, some early digital computers represented numbers as familiar decimal (base 10) numeral system 2.3.4 Clock rate values, and others have employed more unusual repre- sentations such as ternary (base three). Nearly all modern Main article: Clock rate CPUs represent numbers in binary form, with each digit being represented by some two-valued physical quantity [lower-alpha 6] Most CPUs are synchronous circuits, which means they such as a “high” or “low” voltage. employ a clock signal to pace their sequential operations. The clock signal is produced by an external oscillator circuit that generates a consistent number of pulses each second in the form of a periodic square wave. The frequency of the clock pulses determines the rate at which a CPU executes instructions and, consequently, the faster the clock, the more instructions the CPU will execute each second. A six-bit word containing the binary encoded representation of To ensure proper operation of the CPU, the clock period decimal value 40. Most modern CPUs employ word sizes that are is longer than the maximum time needed for all signals to a power of two, for example eight, 16, 32 or 64 bits. propagate (move) through the CPU. In setting the clock period to a value well above the worst-case propagation Related to numeric representation is the size and preci- delay, it is possible to design the entire CPU and the way sion of integer numbers that a CPU can represent. In it moves data around the “edges” of the rising and falling the case of a binary CPU, this is measured by the num- clock signal. This has the advantage of simplifying the ber of bits (significant digits of a binary encoded inte- CPU significantly, both from a design perspective and ger) that the CPU can process in one operation, which a component-count perspective. However, it also car- is commonly called "word size", “bit width”, “data path ries the disadvantage that the entire CPU must wait on width”, “integer precision”, or “integer size”. A CPU’s in- its slowest elements, even though some portions of it are teger size determines the range of integer values it can di- [lower-alpha 7] much faster. This limitation has largely been compen- rectly operate on. For example, an 8-bit CPU sated for by various methods of increasing CPU paral- can directly manipulate integers represented by eight bits, lelism (see below). which have a range of 256 (28) discrete integer values. However, architectural improvements alone do not solve Integer range can also affect the number of memory lo- all of the drawbacks of globally synchronous CPUs. For cations the CPU can directly address (an address is an example, a clock signal is subject to the delays of any integer value representing a specific memory location). other electrical signal. Higher clock rates in increasingly For example, if a binary CPU uses 32 bits to represent a 32 complex CPUs make it more difficult to keep the clock memory address then it can directly address 2 memory signal in phase (synchronized) throughout the entire unit. locations. To circumvent this limitation and for various This has led many modern CPUs to require multiple iden- other reasons, some CPUs use mechanisms (such as bank tical clock signals to be provided to avoid delaying a single switching) that allow additional memory to be addressed. signal significantly enough to cause the CPU to malfunc- CPUs with larger word sizes require more circuitry and tion. Another major issue, as clock rates increase dramat- consequently are physically larger, cost more, and con- ically, is the amount of heat that is dissipated by the CPU. sume more power (and therefore generate more heat). The constantly changing clock causes many components As a result, smaller 4- or 8-bit microcontrollers are com- to switch regardless of whether they are being used at that monly used in modern applications even though CPUs time. In general, a component that is switching uses more with much larger word sizes (such as 16, 32, 64, even energy than an element in a static state. Therefore, as 128-bit) are available. When higher performance is re- clock rate increases, so does energy consumption, caus- 2.3. DESIGN AND IMPLEMENTATION 11

ing the CPU to require more heat dissipation in the form which take more than one clock cycle to complete execu- of CPU cooling solutions. tion. Even adding a second execution unit (see below) One method of dealing with the switching of unneeded does not improve performance much; rather than one components is called clock gating, which involves turn- pathway being hung up, now two pathways are hung up ing off the clock signal to unneeded components (effec- and the number of unused transistors is increased. This tively disabling them). However, this is often regarded design, wherein the CPU’s execution resources can op- as difficult to implement and therefore does not see com- erate on only one instruction at a time, can only possi- mon usage outside of very low-power designs. One no- bly reach scalar performance (one instruction per clock). However, the performance is nearly always subscalar (less table recent CPU design that uses extensive clock gating is the IBM PowerPC-based Xenon used in the Xbox 360; than one instruction per cycle). that way, power requirements of the Xbox 360 are greatly Attempts to achieve scalar and better performance have reduced.[11] Another method of addressing some of the resulted in a variety of design methodologies that cause problems with a global clock signal is the removal of the the CPU to behave less linearly and more in paral- clock signal altogether. While removing the global clock lel. When referring to parallelism in CPUs, two terms signal makes the design process considerably more com- are generally used to classify these design techniques. plex in many ways, asynchronous (or clockless) designs Instruction level parallelism (ILP) seeks to increase the carry marked advantages in power consumption and heat rate at which instructions are executed within a CPU dissipation in comparison with similar synchronous de- (that is, to increase the utilization of on-die execution signs. While somewhat uncommon, entire asynchronous resources), and thread level parallelism (TLP) purposes CPUs have been built without utilizing a global clock sig- to increase the number of threads (effectively individ- nal. Two notable examples of this are the ARM com- ual programs) that a CPU can execute simultaneously. pliant AMULET and the MIPS R3000 compatible Min- Each methodology differs both in the ways in which they iMIPS. are implemented, as well as the relative effectiveness they afford in increasing the CPU’s performance for an Rather than totally removing the clock signal, some CPU [lower-alpha 8] designs allow certain portions of the device to be asyn- application. chronous, such as using asynchronous ALUs in conjunc- tion with superscalar pipelining to achieve some arith- Instruction-level parallelism metic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a Main articles: Instruction pipelining and Superscalar comparable or better level than their synchronous coun- One of the simplest methods used to accomplish in- terparts, it is evident that they do at least excel in simpler math operations. This, combined with their excel- lent power consumption and heat dissipation properties, makes them very suitable for embedded computers.[12]

2.3.5 Parallelism Basic five-stage pipeline. In the best case scenario, this pipeline Main article: Parallel computing can sustain a completion rate of one instruction per cycle. The description of the basic operation of a CPU offered creased parallelism is to begin the first steps of instruction fetching and decoding before the prior instruction finishes executing. This is the simplest form of a technique known as instruction pipelining, and is utilized in almost all modern general-purpose CPUs. Pipelining allows more than Model of a subscalar CPU. Notice that it takes fifteen cycles to one instruction to be executed at any given time by break- complete three instructions. ing down the execution pathway into discrete stages. This separation can be compared to an assembly line, in which in the previous section describes the simplest form that an instruction is made more complete at each stage until a CPU can take. This type of CPU, usually referred to it exits the execution pipeline and is retired. as subscalar, operates on and executes one instruction on Pipelining does, however, introduce the possibility for one or two pieces of data at a time. a situation where the result of the previous operation is This process gives rise to an inherent inefficiency in sub- needed to complete the next operation; a condition often scalar CPUs. Since only one instruction is executed at termed data dependency conflict. To cope with this, addi- a time, the entire CPU must wait for that instruction to tional care must be taken to check for these sorts of con- complete before proceeding to the next instruction. As a ditions and delay a portion of the instruction pipeline if result, the subscalar CPU gets “hung up” on instructions this occurs. Naturally, accomplishing this requires addi- 12 CHAPTER 2. CENTRAL PROCESSING UNIT tional circuitry, so pipelined processors are more complex disable parts of the pipeline so that when a single instruc- than subscalar ones (though not very significantly so). A tion is executed many times, the CPU skips the fetch and pipelined processor can become very nearly scalar, inhib- decode phases and thus greatly increases performance on ited only by pipeline stalls (an instruction spending more certain occasions, especially in highly monotonous pro- than one clock cycle in a stage). gram engines such as video creation software and photo processing. In the case where a portion of the CPU is superscalar and part is not, the part which is not suffers a performance penalty due to scheduling stalls. The Intel P5 Pentium had two superscalar ALUs which could accept one instruction per clock each, but its FPU could not accept one instruction per clock. Thus the P5 was integer superscalar but not floating point superscalar. Intel’s successor to the P5 architecture, P6, added superscalar capabilities to its floating point features, and therefore afforded a significant increase in floating point instruction performance. Both simple pipelining and superscalar design increase a A simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per cycle CPU’s ILP by allowing a single processor to complete ex- can be completed. ecution of instructions at rates surpassing one instruction per cycle (IPC).[lower-alpha 9] Most modern CPU designs Further improvement upon the idea of instruction are at least somewhat superscalar, and nearly all general pipelining led to the development of a method that de- purpose CPUs designed in the last decade are superscalar. creases the idle time of CPU components even fur- In later years some of the emphasis in designing high-ILP ther. Designs that are said to be superscalar include a computers has been moved out of the CPU’s hardware long instruction pipeline and multiple identical execu- and into its software interface, or ISA. The strategy of tion units.[13] In a superscalar pipeline, multiple instruc- the very long instruction word (VLIW) causes some ILP tions are read and passed to a dispatcher, which decides to become implied directly by the software, reducing the whether or not the instructions can be executed in paral- amount of work the CPU must perform to boost ILP and lel (simultaneously). If so they are dispatched to available thereby reducing the design’s complexity. execution units, resulting in the ability for several instructions to be executed simultaneously. In general, the more instructions a superscalar CPU is able to dispatch simulta- Thread-level parallelism neously to waiting execution units, the more instructions will be completed in a given cycle. Another strategy of achieving performance is to execute multiple programs or threads in parallel. This area of re- Most of the difficulty in the design of a superscalar CPU architecture lies in creating an effective dispatcher. The search is known as parallel computing. In Flynn’s tax- dispatcher needs to be able to quickly and correctly de- onomy, this strategy is known as Multiple Instructions- termine whether instructions can be executed in paral- Multiple Data or MIMD. lel, as well as dispatch them in such a way as to keep as One technology used for this purpose was many execution units busy as possible. This requires that multiprocessing (MP). The initial flavor of this tech- the instruction pipeline is filled as often as possible and nology is known as symmetric multiprocessing (SMP), gives rise to the need in superscalar architectures for sig- where a small number of CPUs share a coherent view nificant amounts of CPU cache. It also makes hazard- of their memory system. In this scheme, each CPU has avoiding techniques like branch prediction, speculative additional hardware to maintain a constantly up-to-date execution, and out-of-order execution crucial to main- view of memory. By avoiding stale views of memory, the taining high levels of performance. By attempting to pre- CPUs can cooperate on the same program and programs dict which branch (or path) a conditional instruction will can migrate from one CPU to another. To increase the take, the CPU can minimize the number of times that the number of cooperating CPUs beyond a handful, schemes entire pipeline must wait until a conditional instruction is such as non-uniform memory access (NUMA) and completed. Speculative execution often provides mod- directory-based coherence protocols were introduced in est performance increases by executing portions of code the 1990s. SMP systems are limited to a small number that may not be needed after a conditional operation com- of CPUs while NUMA systems have been built with pletes. Out-of-order execution somewhat rearranges the thousands of processors. Initially, multiprocessing was order in which instructions are executed to reduce delays built using multiple discrete CPUs and boards to imple- due to data dependencies. Also in case of Single Instruc- ment the interconnect between the processors. When the tions Multiple Data — a case when a lot of data from the processors and their interconnect are all implemented same type has to be processed, modern processors can on a single silicon chip, the technology is known as a 2.4. PERFORMANCE 13

multi-core processor. microprocessor. It was later recognized that finer-grain parallelism existed with a single program. A single program might have sev- Data parallelism eral threads (or functions) that could be executed separately or in parallel. Some of the earliest examples of this Main articles: Vector processor and SIMD technology implemented input/output processing such as direct memory access as a separate thread from the computation thread. A more general approach to this tech- A less common but increasingly important paradigm of nology was introduced in the 1970s when systems were CPUs (and indeed, computing in general) deals with data designed to run multiple computation threads in parallel. parallelism. The processors discussed earlier are all re- This technology is known as multi-threading (MT). This ferred to as some type of scalar device.[lower-alpha 10] As approach is considered more cost-effective than multipro- the name implies, vector processors deal with multiple cessing, as only a small number of components within a pieces of data in the context of one instruction. This con- CPU is replicated to support MT as opposed to the en- trasts with scalar processors, which deal with one piece tire CPU in the case of MP. In MT, the execution units of data for every instruction. Using Flynn’s taxonomy, and the memory system including the caches are shared these two schemes of dealing with data are generally re- among multiple threads. The downside of MT is that the ferred to as SIMD (single instruction, multiple data) and hardware support for multithreading is more visible to SISD (single instruction, single data), respectively. The software than that of MP and thus supervisor software great utility in creating CPUs that deal with vectors of like operating systems have to undergo larger changes to data lies in optimizing tasks that tend to require the same support MT. One type of MT that was implemented is operation (for example, a sum or a dot product) to be per- known as block multithreading, where one thread is ex- formed on a large set of data. Some classic examples of ecuted until it is stalled waiting for data to return from these types of tasks are multimedia applications (images, external memory. In this scheme, the CPU would then video, and sound), as well as many types of scientific and quickly switch to another thread which is ready to run, engineering tasks. Whereas a scalar CPU must complete the switch often done in one CPU clock cycle, such as the entire process of fetching, decoding, and executing the UltraSPARC Technology. Another type of MT is each instruction and value in a set of data, a vector CPU known as simultaneous multithreading, where instruc- can perform a single operation on a comparatively large tions of multiple threads are executed in parallel within set of data with one instruction. Of course, this is only one CPU clock cycle. possible when the application tends to require many steps which apply one operation to a large set of data. For several decades from the 1970s to early 2000s, the focus in designing high performance general purpose CPUs Most early vector CPUs, such as the Cray-1, were as- was largely on achieving high ILP through technologies sociated almost exclusively with scientific research and such as pipelining, caches, superscalar execution, out- cryptography applications. However, as multimedia has of-order execution, etc. This trend culminated in large, largely shifted to digital media, the need for some form of power-hungry CPUs such as the Intel Pentium 4. By the SIMD in general-purpose CPUs has become significant. early 2000s, CPU designers were thwarted from achiev- Shortly after inclusion of floating point execution units ing higher performance from ILP techniques due to the started to become commonplace in general-purpose pro- growing disparity between CPU operating frequencies cessors, specifications for and implementations of SIMD and main memory operating frequencies as well as esca- execution units also began to appear for general-purpose lating CPU power dissipation owing to more esoteric ILP CPUs. Some of these early SIMD specifications like HP’s techniques. Multimedia Acceleration eXtensions (MAX) and Intel’s MMX were integer-only. This proved to be a significant CPU designers then borrowed ideas from commercial impediment for some software developers, since many of computing markets such as transaction processing, where the applications that benefit from SIMD primarily deal the aggregate performance of multiple programs, also with floating point numbers. Progressively, these early known as throughput computing, was more important designs were refined and remade into some of the com- than the performance of a single thread or program. mon, modern SIMD specifications, which are usually as- This reversal of emphasis is evidenced by the prolifer- sociated with one ISA. Some notable modern examples ation of dual and multiple core CMP (chip-level multi- are Intel’s SSE and the PowerPC-related AltiVec (also processing) designs and notably, Intel’s newer designs re- known as VMX).[lower-alpha 11] sembling its less superscalar P6 architecture. Late designs in several processor families exhibit CMP, including the x86-64 Opteron and Athlon 64 X2, the SPARC UltraSPARC T1, IBM POWER4 and POWER5, as well 2.4 Performance as several video game console CPUs like the Xbox 360's triple-core PowerPC design, and the PS3's 7-core Cell Further information: Computer performance and Benchmark (computing) 14 CHAPTER 2. CENTRAL PROCESSING UNIT

• CPU socket

The performance or speed of a processor depends on, • Digital signal processor among many other factors, the clock rate (generally given in multiples of hertz) and the instructions per clock (IPC), • Hyper-threading which together are the factors for the instructions per second (IPS) that the CPU can perform.[14] Many reported • List of CPU architectures IPS values have represented “peak” execution rates on ar- • Microprocessor tificial instruction sequences with few branches, whereas realistic workloads consist of a mix of instructions and • Multi-core processor applications, some of which take longer to execute than others. The performance of the memory hierar- • Protection ring chy also greatly affects processor performance, an is- • sue barely considered in MIPS calculations. Because of RISC these problems, various standardized tests, often called • Stream processing “benchmarks” for this purpose—such as SPECint – have been developed to attempt to measure the real effective • True Performance Index performance in commonly used applications. • Wait state Processing performance of computers is increased by using multi-core processors, which essentially is plugging two or more individual processors (called cores in this sense) into one integrated circuit.[15] Ideally, a dual core 2.6 Notes processor would be nearly twice as powerful as a single core processor. In practice, the performance gain is [1] Integrated circuits are now used to implement all CPUs, far smaller, only about 50%, due to imperfect software except for a few machines designed to withstand large algorithms and implementation.[16] Increasing the num- electromagnetic pulses, say from a nuclear weapon. ber of cores in a processor (i.e. dual-core, quad-core, [2] The so-called “von Neumann” memo expounded the idea etc.) increases the workload that can be handled. This of stored programs, which for example may be stored on means that the processor can now handle numerous asyn- punched cards, paper tape, or magnetic tape. chronous events, interrupts, etc. which can take a toll on the CPU when overwhelmed. These cores can be thought [3] Some early computers like the Harvard Mark I did not of as different floors in a processing plant, with each floor support any kind of “jump” instruction, effectively limit- handling a different task. Sometimes, these cores will ing the complexity of the programs they could run. It is handle the same tasks as cores adjacent to them if a sin- largely for this reason that these computers are often not considered to contain a proper CPU, despite their close gle core is not enough to handle the information. similarity to stored-program computers. Due to specific capabilities of modern CPUs, such as hyper-threading and uncore, which involve sharing of ac- [4] Since the program counter counts memory addresses and tual CPU resources while aiming at increased utiliza- not instructions, it is incremented by the number of memory units that the instruction word contains. In the case of tion, monitoring performance levels and hardware uti- simple fixed-length instruction word ISAs, this is always lization gradually became a more complex task. As a the same number. For example, a fixed-length 32-bit in- response, some CPUs implement additional hardware struction word ISA that uses 8-bit memory words would logic that monitors actual utilization of various parts of always increment the PC by four (except in the case of a CPU and provides various counters accessible to soft- jumps). ISAs that use variable-length instruction words ware; an example is Intel’s Performance Counter Monitor increment the PC by the number of memory words corre- technology.[3] sponding to the last instruction’s length.

[5] Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a 2.5 See also classification of the “type” of CPU. For example, a “Pow- erPC CPU” uses some variant of the PowerPC ISA. A • Accelerated processing unit system can execute a different ISA by running an emula- tor. • Addressing mode [6] The physical concept of voltage is an analog one by nature, • CISC practically having an infinite range of possible values. For the purpose of physical representation of binary numbers, • Computer bus two specific ranges of voltages are defined, one for logic • Computer engineering '0' and another for logic '1'. These ranges are dictated by design considerations such as noise margins and charac- • CPU core voltage teristics of the devices used to create the CPU. 2.8. EXTERNAL LINKS 15

[7] While a CPU’s integer size sets a limit on integer ranges, [5] “First Draft of a Report on the EDVAC”. Moore School this can (and often is) overcome using a combination of of Electrical Engineering, University of Pennsylvania. software and hardware techniques. By using additional 1945. memory, software can represent integers many magni- tudes larger than the CPU can. Sometimes the CPU’s ISA [6] Enticknap, Nicholas (Summer 1998), “Computing’s will even facilitate operations on integers larger than it Golden Jubilee”, Resurrection (The Computer Conserva- can natively represent by providing instructions to make tion Society) (20), ISSN 0958-7403, retrieved 19 April large integer arithmetic relatively quick. This method 2008 of dealing with large integers is slower than utilizing a [7] Amdahl, G. M., Blaauw, G. A., & Brooks, F. P. Jr. CPU with higher integer size, but is a reasonable trade- (1964). “Architecture of the IBM System/360”. IBM Re- off in cases where natively supporting the full integer search. range needed would be cost-prohibitive. See Arbitrary- precision arithmetic for more details on purely software- [8] “LSI-11 Module Descriptions”. LSI-11, PDP-11/03 user’s supported arbitrary-sized integers. manual (2nd ed.). Maynard, Massachusetts: Digital Equipment Corporation. November 1975. pp. 4–3. [8] Neither ILP nor TLP is inherently superior over the other; they are simply different means by which to increase CPU [9] “Excerpts from A Conversation with Gordon Moore: parallelism. As such, they both have advantages and dis- Moore’s Law” (PDF). Intel. 2005. Retrieved 2012-07- advantages, which are often determined by the type of 25. software that the processor is intended to run. High-TLP CPUs are often used in applications that lend themselves [10] Ian Wienand (September 3, 2013). “Computer Science well to being split up into numerous smaller applications, from the Bottom Up, Chapter 3. Computer Architecture” so-called "embarrassingly parallel problems”. Frequently, (PDF). bottomupcs.com. Retrieved January 7, 2015. a computational problem that can be solved quickly with [11] Brown, Jeffery (2005). “Application-customized CPU high TLP design strategies like SMP take significantly design”. IBM developerWorks. Retrieved 2005-12-17. more time on high ILP devices like superscalar CPUs, and vice versa. [12] Garside, J. D., Furber, S. B., & Chung, S-H (1999). “AMULET3 Revealed”. University of Manchester Com- [9] Best-case scenario (or peak) IPC rates in very superscalar puter Science Department. Archived from the original on architectures are difficult to maintain since it is impossible December 10, 2005. to keep the instruction pipeline filled all the time. There- fore, in highly superscalar CPUs, average sustained IPC [13] Huynh, Jack (2003). “The AMD Athlon XP Processor is often discussed rather than peak IPC. with 512KB L2 Cache”. University of Illinois — Urbana- Champaign. pp. 6–11. Retrieved 2007-10-06. [10] Earlier the term scalar was used to compare the IPC (instructions per cycle) count afforded by various ILP meth- [14] “CPU Frequency”. CPU World Glossary. CPU World. 25 ods. Here the term is used in the strictly mathematical March 2008. Retrieved 1 January 2010. sense to contrast with vectors. See scalar (mathematics) and Vector (geometric). [15] “What is (a) multi-core processor?". Data Center Defini- tions. SearchDataCenter.com. 27 March 2007. Retrieved [11] Although SSE/SSE2/SSE3 have superseded MMX in In- 1 January 2010. tel’s general purpose CPUs, later IA-32 designs still support MMX. This is usually accomplished by providing [16] “Quad Core Vs. Dual Core”. http://www.buzzle.com/''. most of the MMX functionality with the same hardware Retrieved 26 November 2014. that supports the much more expansive SSE instruction sets. 2.8 External links

2.7 References • How Microprocessors Work at HowStuﬀWorks. • 25 Microchips that shook the world – an article by [1] Weik, Martin H. (1961). “A Third Survey of Domes- the Institute of Electrical and Electronics Engineers. tic Electronic Digital Computing Systems”. Ballistic Re- search Laboratory.

[2] Kuck, David (1978). Computers and Computations, Vol 1. John Wiley & Sons, Inc. p. 12. ISBN 0471027162.

[3] Thomas Willhalm; Roman Dementiev; Patrick Fay (De- cember 18, 2014). “Intel Performance Counter Moni- tor – A better way to measure CPU utilization”. software.intel.com. Retrieved February 17, 2015.

[4] Regan, Gerard. A Brief History of Computing. p. 66. ISBN 1848000839. Retrieved 26 November 2014. Chapter 3

Chipset

In a computer system, a chipset is a set of electronic components in an integrated circuit that manages the data ﬂow between the processor, memory and peripherals. It is usually found on the motherboard. Chipsets are usually designed to work with a speciﬁc family of microprocessors. Because it controls communications between the processor and external devices, the chipset plays a crucial role in determining system performance.

Diagram of Commodore Amiga's Original Chip Set

Intel ICH7 Southbridge on Intel D945GCPE Desktop Board

3.1 Computers

In computing, the term chipset commonly refers to a set of specialized chips on a computer's motherboard or an expansion card. In personal computers, the ﬁrst chipset for the IBM PC AT of 1984 was the NEAT chipset developed by Chips and Technologies for the Intel 80286 CPU. A part of an IBM T42 laptop motherboard. CPU: Central pro- In home computers, game consoles and arcade-game cessing unit. NB: Northbridge. GPU: Graphics processing unit. hardware of the 1980s and 1990s, the term chipset was SB: Southbridge. used for the custom audio and graphics chips. Exam- ples include the Commodore Amiga's Original Chip Set or SEGA's System 16 chipset. cially RAM and graphics controllers, and the southbridge Based on Intel Pentium-class microprocessors, the term connects to lower-speed peripheral buses (such as PCI or chipset often refers to a speciﬁc pair of chips on the moth- ISA). In many modern chipsets, the southbridge contains erboard: the northbridge and the southbridge. The north- some on-chip integrated peripherals, such as Ethernet, bridge links the CPU to very high-speed devices, espe- USB, and audio devices.

16 3.3. SEE ALSO 17

Motherboards and their chipsets often come from dif- has further increased, primarily inclusion of the system’s ferent manufacturers. As of 2015, manufacturers of primary PCIe controller and integrated graphics directly chipsets for x86 motherboards include AMD, Broadcom, on the CPU itself. As fewer functions are left un-handled Intel, NVIDIA, SiS and VIA Technologies. Apple com- by the processor, chipset vendors have condensed the re- puters and Unix workstations have traditionally used maining northbridge and southbridge functions into a sin- custom-designed chipsets. Some server manufacturers gle chip. Intel’s version of this is the "Platform Controller also develop custom chipsets for their products. Hub" (PCH), eﬀectively an enhanced southbridge for the In the 1980s Chips and Technologies pioneered the remaining peripherals as traditional northbridge duties, such as memory controller, expansion bus (PCIe) inter- manufacturing of chipsets for PC-compatible computers. Computer systems produced since then often share com- face, and even on-board video controller, are integrated into the CPU itself. monly used chipsets, even across widely disparate computing specialties. For example, the NCR 53C9x, a low- cost chipset implementing a SCSI interface to storage devices, could be found in Unix machines such as the MIPS 3.3 See also Magnum, embedded devices, and personal computers. • Very-large-scale integration or VLSI

• List of Intel chipsets 3.2 Move toward processor inte- • Comparison of AMD chipsets gration in PCs • Comparison of ATI chipsets

Traditionally in x86 computers, the processor’s primary • Comparison of Nvidia chipsets connection to the rest of the machine is through the moth- • erboard chipset’s northbridge. The northbridge is directly VIA chipsets responsible for communications with high-speed devices • Silicon Integrated Systems (system memory and primary expansion buses, such as PCIe, AGP and PCI cards, being common examples) • Acer Laboratories Incorporated and conversely any system communication back to the • processor. This connection between the processor and Southbridge northbridge is traditionally known as the front side bus • Northbridge (FSB). Requests to resources not directly controlled by the northbridge are oﬄoaded to the southbridge, with the northbridge being an intermediary between the processor and the southbridge. The southbridge traditionally han- 3.4 Notes dles “everything else”, generally lower-speed peripherals and board functions (the largest being hard disk and stor- [1] “AMD Ushers in Era of Cinematic Computing with the AMD Athlon 64 FX Processor”. 2003-09-23. Retrieved age connectivity) such as USB, parallel and serial commu- 2006-07-04. nications. The connection between the northbridge and southbridge does not have a common name, but is usually a high-speed interconnect proprietary to the chipset vendor. Before 2003, any interaction between a CPU and main memory or an expansion device such as a graphics card(s) — whether AGP, PCI or integrated into the motherboard — was directly controlled by the northbridge IC on be- half of the processor. This made processor performance highly dependent on the system chipset, especially the northbridge’s memory performance and ability to shuttle this information back to the processor. In 2003, however, AMD’s introduction of the Athlon 64-bit series of processors[1] changed this. The Athlon64 marked the introduction of an integrated memory controller being incorporated into the processor itself thus allowing the processor to directly access and handle memory, negating the need for a traditional northbridge to do so. Intel followed suit in 2008 with the release of its Core i series CPUs and the X58 platform. In newer processors integration Chapter 4

Graphics processing unit

Not to be confused with Graphics card. VPU with the release of the Radeon 9700 in 2002. “GPU” redirects here. For other uses, see GPU (disambiguation). A graphics processor unit (GPU), also occasionally 4.1 History

Arcade system boards have been using specialized graphics chips since the 1970s. Fujitsu's MB14241 video shifter was used to accelerate the drawing of sprite graphics for various 1970s arcade games from Taito and Midway, such as Gun Fight (1975), Sea Wolf (1976) and Space Invaders (1978).[2][3][4] The Namco Galax- ian arcade system in 1979 used specialized graphics hardware supporting RGB color, multi-colored sprites and tilemap backgrounds.[5] The Galaxian hardware was widely used during the golden age of arcade video games, by game companies such as Namco, Centuri, Gremlin, Irem, Konami, Midway, Nichibutsu, Sega and Taito.[6][7] In the home video game console market, the Atari 2600 in 1977 used a video shifter called the Television Inter- face Adaptor.

GeForce 6600GT (NV43) GPU 4.1.1 1980s called visual processor unit (VPU), is a specialized See also: Video Display Controller, List of home com- electronic circuit designed to rapidly manipulate and alter memory to accelerate the creation of images in a frame puters by video hardware and Sprite (computer graphics) buffer intended for output to a display. GPUs are used in embedded systems, mobile phones, personal computers, In 1985, the Commodore Amiga featured a GPU ad- workstations, and game consoles. Modern GPUs are very vanced for a personal computer at the time. It supported efficient at manipulating computer graphics and image line draw, area fill, and included a type of stream proces- processing, and their highly parallel structure makes them sor called a blitter which accelerated the movement, ma- more effective than general-purpose CPUs for algorithms nipulation and combination of multiple arbitrary bitmaps. where processing of large blocks of data is done in par- Also included was a coprocessor with its own (primitive) allel. In a personal computer, a GPU can be present on a instruction set capable of directly invoking a sequence video card, or it can be on the motherboard or—in certain of graphics operations without CPU intervention. Prior CPUs—on the CPU die.[1] to this and for quite some time after, many other per- The term GPU was popularized by Nvidia in 1999, who sonal computer systems instead used their main, general- marketed the GeForce 256 as “the world’s first 'GPU', or purpose CPU to handle almost every aspect of drawing Graphics Processing Unit, a single-chip processor with the display, short of generating the final video signal. integrated transform, lighting, triangle setup/clipping, In 1986, Texas Instruments released the TMS34010, the and rendering engines that are capable of processing a first microprocessor with on-chip graphics capabilities. minimum of 10 million polygons per second”. Rival ATI It could run general-purpose code, but it had a very Technologies coined the term visual processing unit or graphics-oriented instruction set. In 1990-1991, this chip

18 4.1. HISTORY 19

would become the basis of the Texas Instruments Graph- ics Architecture (“TIGA”) Windows accelerator cards. In 1987, the IBM 8514 graphics system was released as one of the first video cards for IBM PC compatibles to implement fixed-function 2D primitives in electronic hardware. The same year, Sharp released the X68000, which used a custom graphics chipset[8] that was powerful for a home computer at the time, with a 65,536 color palette and hardware support for sprites, scrolling and multiple playfields,[9] eventually serving as a development machine for Capcom's CP System arcade board. Fujitsu later competed with the FM Towns computer, released in 1989 with support for a full 16,777,216 color [10] palette. Voodoo3 2000 AGP card In 1988, the first dedicated polygonal 3D graphics boards were introduced in arcades with the Namco System 21[11] and Taito Air System.[12] Throughout the 1990s, 2D GUI acceleration continued to evolve. As manufacturing capabilities improved, so did the level of integration of graphics chips. Additional 4.1.2 1990s application programming interfaces (APIs) arrived for a variety of tasks, such as Microsoft’s WinG graphics library for Windows 3.x, and their later DirectDraw interface for hardware acceleration of 2D games within Windows 95 and later. In the early- and mid-1990s, CPU-assisted real-time 3D graphics were becoming increasingly common in arcade, computer and console games, which led to an increasing public demand for hardware-accelerated 3D graphics. Early examples of mass-marketed 3D graphics hardware can be found in arcade system boards such as the Sega Model 1, Namco System 22, and Sega Model 2, and the Tseng Labs ET4000/W32p fifth-generation video game consoles such as the Saturn, PlayStation and Nintendo 64. Arcade systems such as the Sega Model 2 and Namco Magic Edge Hornet Simula- tor were capable of hardware T&L (transform, clipping, and lighting) years before appearing in consumer graphics cards.[13][14] Fujitsu, which worked on the Sega Model 2 arcade system,[15] began working on integrating T&L into a single LSI solution for use in home computers in 1995.[16][17][18] In the PC world, notable failed first tries for low- cost 3D graphics chips were the S3 ViRGE, ATI Rage, and Matrox Mystique. These chips were essentially previous-generation 2D accelerators with 3D features bolted on. Many were even pin-compatible with the earlier-generation chips for ease of implementation and S3 Graphics ViRGE minimal cost. Initially, performance 3D graphics were possible only with discrete boards dedicated to acceler- In 1991, S3 Graphics introduced the S3 86C911, which ating 3D functions (and lacking 2D GUI acceleration en- its designers named after the Porsche 911 as an impli- tirely) such as the PowerVR and the 3dfx Voodoo. How- cation of the performance increase it promised. The ever, as manufacturing technology continued to progress, 86C911 spawned a host of imitators: by 1995, all ma- video, 2D GUI acceleration and 3D functionality were jor PC graphics chip makers had added 2D accelera- all integrated into one chip. Rendition’s Verite chipsets tion support to their chips. By this time, fixed-function were among the first to do this well enough to be worthy Windows accelerators had surpassed expensive general- of note. In 1997, Rendition went a step further by col- purpose graphics coprocessors in Windows performance, laborating with Hercules and Fujitsu on a “Thriller Con- and these coprocessors faded away from the PC market. spiracy” project which combined a Fujitsu FXG-1 Pino- 20 CHAPTER 4. GRAPHICS PROCESSING UNIT lite geometry processor with a Vérité V2200 core to cre- NV20). By October 2002, with the introduction of the ate a graphics card with a full T&L engine years before ATI Radeon 9700 (also known as R300), the world’s first Nvidia’s GeForce 256. This card, designed to reduce the Direct3D 9.0 accelerator, pixel and vertex shaders could load placed upon the system’s CPU, never made it to mar- implement looping and lengthy floating point math, and in ket. general were quickly becoming as flexible as CPUs, and OpenGL appeared in the early '90s as a professional orders of magnitude faster for image-array operations. graphics API, but originally suffered from performance Pixel shading is often used for things like bump mapping, issues which allowed the Glide API to step in and become which adds texture, to make an object look shiny, dull, rough, or even round or extruded.[20] a dominant force on the PC in the late '90s.[19] How- ever, these issues were quickly overcome and the Glide API fell by the wayside. Software implementations of OpenGL were common during this time, although the in- 4.1.4 2006 to present fluence of OpenGL eventually led to widespread hardware support. Over time, a parity emerged between fea- With the introduction of the GeForce 8 series, which was tures offered in hardware and those offered in OpenGL. produced by Nvidia, and then new generic stream pro- DirectX became popular among Windows game devel- cessing unit GPUs became a more generalized computing opers during the late 90s. Unlike OpenGL, Microsoft device. Today, parallel GPUs have begun making com- insisted on providing strict one-to-one support of hard- putational inroads against the CPU, and a subfield of re- ware. The approach made DirectX less popular as a stan- search, dubbed GPU Computing or GPGPU for General dalone graphics API initially, since many GPUs provided Purpose Computing on GPU, has found its way into fields as diverse as machine learning,[21] oil exploration, scien- their own specific features, which existing OpenGL ap- [22] [23] plications were already able to benefit from, leaving Di- tific image processing, linear algebra, statistics, 3D rectX often one generation behind. (See: Comparison of reconstruction and even stock options pricing determina- OpenGL and Direct3D.) tion. Over the years, the energy consumption of GPUs has increased and to manage it, several techniques have Over time, Microsoft began to work more closely with been proposed.[24] hardware developers, and started to target the releases of DirectX to coincide with those of the supporting Nvidia’s CUDA platform was the earliest widely adopted graphics hardware. Direct3D 5.0 was the first ver- programming model for GPU computing. More recently sion of the burgeoning API to gain widespread adop- OpenCL has become broadly supported. OpenCL is an tion in the gaming market, and it competed directly with open standard defined by the Khronos Group which allows for the development of code for both GPUs and many more-hardware-specific, often proprietary graph- [25] ics libraries, while OpenGL maintained a strong fol- CPUs with an emphasis on portability. OpenCL so- lowing. Direct3D 7.0 introduced support for hardware- lutions are supported by Intel, AMD, Nvidia, and ARM, accelerated transform and lighting (T&L) for Direct3D, and according to a recent report by Evan’s Data, OpenCL while OpenGL had this capability already exposed from is the GPGPU development platform most widely used by its inception. 3D accelerator cards moved beyond being developers in both the US and Asia Pacific. just simple rasterizers to add another significant hardware stage to the 3D rendering pipeline. The Nvidia GeForce 256 (also known as NV10) was the first consumer-level 4.1.5 GPU companies card released on the market with hardware-accelerated T&L, while professional 3D cards already had this capability. Hardware transform and lighting, both already existing features of OpenGL, came to consumer-level hardware in the '90s and set the precedent for later pixel shader and vertex shader units which were far more flexible and programmable.

4.1.3 2000 to 2006

With the advent of the OpenGL API and similar functionality in DirectX, GPUs added shading to their capabilities. Each pixel could now be processed by a short program that could include additional image textures as GPU manufacturers market share inputs, and each geometric vertex could likewise be processed by a short program before it was projected onto Many companies have produced GPUs under a number the screen. Nvidia was ﬁrst to produce a chip capable of brand names. In 2009, Intel, Nvidia and AMD/ATI of programmable shading, the GeForce 3 (code named were the market share leaders, with 49.4%, 27.8% and 4.3. GPU FORMS 21

20.6% market share respectively. However, those num- video post-processing are offloaded to the GPU hard- bers include Intel’s integrated graphics solutions as GPUs. ware, is commonly referred to as “GPU accelerated video Not counting those numbers, Nvidia and ATI control decoding”, “GPU assisted video decoding”, “GPU hard- nearly 100% of the market as of 2008.[26] In addi- ware accelerated video decoding” or “GPU hardware as- tion, S3 Graphics[27] (owned by VIA Technologies) and sisted video decoding”. [28] Matrox produce GPUs. More recent graphics cards even decode high-definition video on the card, offloading the central processing unit. The most common APIs for GPU accelerated 4.2 Computational functions video decoding are DxVA for Microsoft Windows operating system and VDPAU, VAAPI, XvMC, and XvBA Modern GPUs use most of their transistors to do calcula- for Linux-based and UNIX-like operating systems. All tions related to 3D computer graphics. They were initially except XvMC are capable of decoding videos en- used to accelerate the memory-intensive work of texture coded with MPEG-1, MPEG-2, MPEG-4 ASP (MPEG- mapping and rendering polygons, later adding units to 4 Part 2), MPEG-4 AVC (H.264 / DivX 6), VC-1, accelerate geometric calculations such as the rotation WMV3/WMV9, Xvid / OpenDivX (DivX 4), and DivX 5 and translation of vertices into different coordinate sys- codecs, while XvMC is only capable of decoding MPEG- tems. Recent developments in GPUs include support for 1 and MPEG-2. programmable shaders which can manipulate vertices and textures with many of the same operations supported by Video decoding processes that can be accelerated CPUs, oversampling and interpolation techniques to reduce aliasing, and very high-precision color spaces. Be- The video decoding processes that can be accelerated by cause most of these computations involve matrix and today’s modern GPU hardware are: vector operations, engineers and scientists have increasingly studied the use of GPUs for non-graphical calculations. • Motion compensation (mocomp) In addition to the 3D hardware, today’s GPUs include • Inverse discrete cosine transform (iDCT) basic 2D acceleration and framebuffer capabilities (usually with a VGA compatibility mode). Newer cards like • Inverse telecine 3:2 and 2:2 pull-down correc- AMD/ATI HD5000-HD7000 even lack 2D acceleration; tion it has to be emulated by 3D hardware. • Inverse modified discrete cosine transform (iMDCT) 4.2.1 GPU accelerated video decoding • In-loop deblocking filter

• Intra-frame prediction

• Inverse quantization (IQ)

• Variable-length decoding (VLD), more commonly known as slice-level acceleration

• Spatial-temporal deinterlacing and automatic interlace/progressive source detection

• Bitstream processing (Context-adaptive variable- length coding/Context-adaptive binary arithmetic coding) and perfect pixel positioning.

The ATI HD5470 GPU (above) features UVD 2.1 which enables 4.3 GPU forms it to decode AVC and VC-1 video formats

Most GPUs made since 1995 support the YUV color 4.3.1 Dedicated graphics cards space and hardware overlays, important for digital video playback, and many GPUs made since 2000 also sup- Main article: Video card port MPEG primitives such as motion compensation and iDCT. This process of hardware accelerated video decod- The GPUs of the most powerful class typically inter- ing, where portions of the video decoding process and face with the motherboard by means of an expansion 22 CHAPTER 4. GRAPHICS PROCESSING UNIT slot such as PCI Express (PCIe) or Accelerated Graph- ics Port (AGP) and can usually be replaced or upgraded with relative ease, assuming the motherboard is capable of supporting the upgrade. A few graphics cards still use Peripheral Component Interconnect (PCI) slots, but their bandwidth is so limited that they are generally used only when a PCIe or AGP slot is not available. A dedicated GPU is not necessarily removable, nor does it necessarily interface with the motherboard in a standard fashion. The term “dedicated” refers to the fact that dedicated graphics cards have RAM that is dedicated to the card’s use, not to the fact that most dedicated GPUs are A motherboard with integrated graphics, which has HDMI, VGA and DVI outs. removable. Dedicated GPUs for portable computers are most commonly interfaced through a non-standard and often proprietary slot due to size and weight constraints. integrated graphics processors (IGP) utilize a portion of Such ports may still be considered PCIe or AGP in terms a computer’s system RAM rather than dedicated graph- of their logical host interface, even if they are not physi- ics memory. IGPs can be integrated onto the mother- cally interchangeable with their counterparts. board as part of the chipset, or within the same die as Technologies such as SLI by Nvidia and CrossFire by CPU (like AMD APU or Intel HD Graphics). Some of AMD allow multiple GPUs to draw images simultane- AMD’s IGPs use dedicated sideport memory on certain ously for a single screen, increasing the processing power motherboards. Computers with integrated graphics ac- [29] available for graphics. count for 90% of all PC shipments. These solutions are less costly to implement than dedicated graphics solutions, but tend to be less capable. Historically, integrated 4.3.2 Integrated graphics solutions solutions were often considered unfit to play 3D games or run graphically intensive programs but could run less intensive programs such as Adobe Flash. Examples of such IGPs would be offerings from SiS and VIA circa 2004.[30] However, modern integrated graphics processors such as CPU AMD Accelerated Processing Unit and Intel HD Graph- ics are more than capable of handling 2D graphics or low Clock Front-side Graphics Generator bus card slot stress 3D graphics. Chipset As a GPU is extremely memory intensive, an integrated Memory Slots High-speed solution may find itself competing for the already rela- graphics bus tively slow system RAM with the CPU, as it has mini- (AGP or PCI Northbridge Memory Express) bus mal or no dedicated video memory. IGPs can have up to (memory 29.856 GB/s of memory bandwidth from system RAM, controller hub) however graphics cards can enjoy up to 264 GB/s of bandwidth between its RAM and GPU core. This band- Internal widh is what is referred to as the memory bus and can be Bus PCI performance limiting. Older integrated graphics chipsets Bus Onboard lacked hardware transform and lighting, but newer ones graphics Southbridge include it.[31][32] PCI (I/O controller controller Bus hub) IDE SATA USB Cables and Ethernet ports leading 4.3.3 Hybrid solutions Audio Codec CMOS Memory off-board

PCI Slots This newer class of GPUs competes with integrated

LPC graphics in the low-end desktop and notebook markets. Bus Super I/O The most common implementations of this are ATI’s Serial Port Parallel Port HyperMemory and Nvidia’s TurboCache. Flash ROM Floppy Disk Keyboard Hybrid graphics cards are somewhat more expensive than (BIOS) Mouse integrated graphics, but much less expensive than dedicated graphics cards. These share memory with the sys- Layout tem and have a small dedicated memory cache, to make up for the high latency of the system RAM. Technologies Integrated graphics solutions, shared graphics solutions, or within PCI Express can make this possible. While these 4.4. SALES 23 solutions are sometimes advertised as having as much as proaches compile linear or tree programs on the host PC 768MB of RAM, this refers to how much can be shared and transfer the executable to the GPU to be run. Typi- with the system memory. cally the performance advantage is only obtained by running the single active program simultaneously on many example problems in parallel, using the GPU’s SIMD 4.3.4 Stream Processing and General Pur- architecture.[36][37] However, substantial acceleration can pose GPUs (GPGPU) also be obtained by not compiling the programs, and instead transferring them to the GPU, to be interpreted there.[38][39] Acceleration can then be obtained by either Main articles: GPGPU and Stream processing interpreting multiple programs simultaneously, simultaneously running multiple example problems, or combi- It is becoming increasingly common to use a general nations of both. A modern GPU (e.g. 8800 GTX or purpose graphics processing unit as a modified form of later) can readily simultaneously interpret hundreds of stream processor. This concept turns the massive compu- thousands of very small programs. tational power of a modern graphics accelerator’s shader pipeline into general-purpose computing power, as opposed to being hard wired solely to do graphical operations. In certain applications requiring massive vector 4.3.5 External GPU (eGPU) operations, this can yield several orders of magnitude higher performance than a conventional CPU. The two An external GPU is a graphics processor located outside largest discrete (see "Dedicated graphics cards" above) of the housing of the computer. External Graphics Pro- GPU designers, ATI and Nvidia, are beginning to pursue cessors are often used with laptop computers. Laptops this approach with an array of applications. Both Nvidia might have a substantial amount of RAM and a suffi- and ATI have teamed with Stanford University to create ciently powerful Central Processing Unit(CPU), but of- a GPU-based client for the Folding@home distributed ten lack a powerful graphics processor (and instead have computing project, for protein folding calculations. In a less powerful, but energy efficient on-board graphics certain circumstances the GPU calculates forty times chip). On-board graphics chips are often not powerful faster than the conventional CPUs traditionally used by enough for playing the latest games, or for other tasks such applications.[33][34] (video editing, ...). GPGPU can be used for many types of embarrassingly Therefore it is desirable to be able to attach to some parallel tasks including ray tracing. They are generally external PCIe bus of a notebook. That may be an suited to high-throughput type computations that exhibit x1 2.0 5Gbit/s expresscard or mPCIe (wifi) port or data-parallelism to exploit the wide vector width SIMD a 10Gbit/s/16Gbit/s Thunderbolt1/Thunderbolt2 port. architecture of the GPU. Those ports being only available on certain candidate notebook systems.[40][41] Furthermore, GPU-based high performance computers are starting to play a significant role in large-scale mod- External GPU’s have had little official vendor support. elling. Three of the 10 most powerful supercomputers in Promising solutions such as Silverstone T004 (aka ASUS the world take advantage of GPU acceleration.[35] XG2)[42] and MSI GUS-II[43] were never released to the general public. MSI’s Gamedock [44] promising to de- NVIDIA cards support API extensions to the C program- liver a full x16 external PCIe bus to a purpose built com- ming language such as CUDA (“Compute Unified De- pact 13” MSI GS30 notebook. Lenovo and Magma part- vice Architecture”) and OpenCL. CUDA is specifically nering in Sep-2014 to deliver official Thunderbolt eGPU for NVIDIA GPUs whilst OpenCL is designed to work support.[45] across a multitude of architectures including GPU, CPU and DSP (using vendor specific SDKs). These tech- This has not stopped enthusiasts from creating their own nologies allow specified functions (kernels) from a nor- DIY eGPU solutions.[46][47] expresscard/mPCIe eGPU mal C program to run on the GPU’s stream processors. adapters/enclosures are usually acquired from BPlus This makes C programs capable of taking advantage of (PE4C, PE4L, PE4C),[48] or EXP GDC.[49] native Thun- a GPU’s ability to operate on large matrices in paral- derbolt eGPU adaptere/enclosures acquired from One lel, while still making use of the CPU when appropriate. Stop Systems,[50] AKiTiO,[51] Sonnet (often rebadge as CUDA is also the first API to allow CPU-based applica- Other World Computing — OWC) and FirmTek. tions to directly access the resources of a GPU for more general purpose computing without the limitations of using a graphics API. Since 2005 there has been interest in using the per- 4.4 Sales formance offered by GPUs for evolutionary computation in general, and for accelerating the fitness evalu- In 2013, 438.3 million GPUs were shipped globally and ation in genetic programming in particular. Most ap- the forecast for 2014 was 414.2 million.[52] 24 CHAPTER 4. GRAPHICS PROCESSING UNIT

4.5 See also 4.5.3 Applications

• Brute force attack • GPU cluster • Computer graphics • Mathematica includes built-in support for CUDA and OpenCL GPU execution • Computer hardware • MATLAB acceleration using the Parallel Comput- • Computer monitor ing Toolbox and MATLAB Distributed Computing [53] • Central processing unit Server, as well as 3rd party packages like Jacket. • GPU cache • Molecular modeling on GPU • Physics processing unit (PPU) • Deeplearning4j, open-source, distributed deep learning for Java. Machine vision and textual topic • Ray tracing hardware modelling toolkit. • Video card • Video Display Controller 4.6 References • Video game console [1] Denny Atkin. “Computer Shopper: The Right GPU for • Virtualized GPU You”. Retrieved 2007-05-15.

[2] “mame/8080bw.c at master mamedev/mame 4.5.1 Hardware GitHub”. GitHub.

• Comparison of AMD graphics processing units [3] “mame/mw8080bw.c at master mamedev/mame GitHub”. GitHub. • Comparison of Nvidia graphics processing units [4] “Arcade/SpaceInvaders – Computer Archeology”. com- • Comparison of Intel graphics processing units puterarcheology.com.

• Intel GMA [5] “mame/galaxian.c at master mamedev/mame GitHub”. GitHub. • Larrabee • [6] “mame/galaxian.c at master mamedev/mame Nvidia PureVideo - the bit-stream technology from GitHub”. GitHub. Nvidia used in their graphics chips to accelerate video decoding on hardware GPU with DXVA. [7] “MAME - src/mame/drivers/galdrvr.c”. archive.org. Archived from the original on 3 January 2014. • UVD (Uniﬁed Video Decoder) - is the video decoding bit-stream technology from ATI Technologies to [8] http://nfggames.com/games/x68k/ support hardware (GPU) decode with DXVA. [9] “musem ~ Sharp X68000”. Old-computers.com. Re- trieved 2015-01-28.

4.5.2 APIs [10] “Hardcore Gaming 101: Retro Japanese Computers: Gaming’s Final Frontier”. hardcoregaming101.net. • OpenGL API [11] “System 16 - Namco System 21 Hardware (Namco)". sys- • DirectX Video Acceleration (DxVA) API for tem16.com. Microsoft Windows operating-system. [12] “System 16 - Taito Air System Hardware (Taito)". sys- • Mantle (API) tem16.com. • Video Acceleration API (VA API) [13] “System 16 - Namco Magic Edge Hornet Simulator Hard- • VDPAU (Video Decode and Presentation API for ware (Namco)". system16.com. Unix) [14] “MAME - src/mame/video/model2.c”. archive.org. Archived from the original on 4 January 2013. • X-Video Bitstream Acceleration (XvBA), the X11 equivalent of DXVA for MPEG-2, H.264, and VC- [15] “System 16 - Sega Model 2 Hardware (Sega)". sys- 1 tem16.com.

• X-Video Motion Compensation, the X11 equivalent [16] http://www.hotchips.org/wp-content/uploads/hc_ for MPEG-2 video codec only archives/hc07/3_Tue/HC7.S5/HC7.5.1.pdf 4.7. EXTERNAL LINKS 25

[17] http://www.fujitsu.com/downloads/MAG/vol33-2/ [39] V. Garcia and E. Debreuve and M. Barlaud. Fast k near- paper08.pdf est neighbor search using GPU. In Proceedings of the CVPR Workshop on Computer Vision on GPU, Anchor- [18] “Fujitsu Develops World’s First Three Dimensional Ge- age, Alaska, USA, June 2008. ometry Processor”. fujitsu.com. [40] “eGPU candidate system list”. Tech-Inferno Forums. [19] 3dfx Glide API [41] Neil Mohr. “How to make an external laptop graphics [20] Søren Dreijer. “Bump Mapping Using CG (3rd Edition)". adaptor”. TechRadar. Retrieved 2007-05-30. [42] "[THUNDERBOLT NEWS] Silverstone T004... Now the [21] “Large-scale deep unsupervised learning using ASUS XG2”. Tech-Inferno Forums. graphics processors”. Dl.acm.org. 2009-06-14. doi:10.1145/1553374.1553486. Retrieved 2014-01-21. [43] “MSI’s GUS II: External Thunderbolt GPU”. notebookre- view.com. [22] “Linear algebra operators for GPU implementation of numerical algorithms”, Kruger and Westermann, Interna- [44] “MSI eGPU dock in the works for GS30?". Tech-Inferno tional Conf. on Computer Graphics and Interactive Tech- Forums. niques, 2005 [45] “Lenovo + Magma partnership delivers oﬃcial Thunder- [23] “ABC-SysBio—approximate Bayesian computation in bolt eGPU support”. Tech-Inferno Forums. Python with GPU support”, Liepe et al., Bioinformatics, (2010), 26:1797-1799 [46] “DIY eGPU on Tablet PC’s: experiences, benchmarks, setup, ect...”. tabletpcreview.com. [24] "A Survey of Methods for Analyzing and Improving GPU Energy Eﬃciency", Mittal et al., ACM Computing Sur- [47] “Implementations Hub: TB, EC, mPCIe”. Tech-Inferno veys, 2014. Forums.

[25] “OpenCL - The open standard for parallel programming [48] BPlus eGPU adapters of heterogeneous systems”. khronos.org. [49] "--". taobao.com. [26] “GPU sales strong as AMD gains market share”. techre- port.com. [50] Jim Galbraith (28 March 2014). “Expo Notes: Thunder- bolt takes over”. Macworld. [27] “Products”. S3 Graphics. Retrieved 2014-01-21. [51] “US$200 AKiTiO Thunder2 PCIe Box (16Gbps-TB2)". [28] “Matrox Graphics - Products - Graphics Cards”. Ma- Tech-Inferno Forums. trox.com. Retrieved 2014-01-21. [52] “Graphics chips market is showing some life”. TG Daily. [29] Gary Key. “AnandTech - µATX Part 2: Intel G33 Perfor- August 20, 2014. Retrieved August 22, 2014. mance Review”. anandtech.com. [53] “MATLAB Adds GPGPU Support”. 2010-09-20. [30] Tim Tscheblockov. “Xbit Labs: Roundup of 7 Contem- porary Integrated Graphics Chipsets for Socket 478 and Socket A Platforms”. Retrieved 2007-06-03. 4.7 External links [31] Bradley Sanford. “Integrated Graphics Solutions for Graphics-Intensive Applications”. Retrieved 2007-09-02. • NVIDIA - What is GPU computing?

[32] Bradley Sanford. “Integrated Graphics Solutions for • The GPU Gems book series Graphics-Intensive Applications”. Retrieved 2007-09-02. • - a Graphics Hardware History [33] Darren Murph. “Stanford University tailors Fold- ing@home to GPUs”. Retrieved 2007-10-04. • General-Purpose Computation Using Graphics [34] Mike Houston. “Folding@Home - GPGPU”. Retrieved Hardware 2007-10-04. • How GPUs work [35] “Top500 List - June 2012 | TOP500 Supercomputer • Sites”. Top500.org. Retrieved 2014-01-21. GPU Caps Viewer - Video card information utility • [36] John Nickolls. “Stanford Lecture: Scalable Parallel Pro- OpenGPU-GPU Architecture(In Chinese) gramming with CUDA on Manycore GPUs”. • ARM Mali GPUs Overview [37] S Harding and W Banzhaf. “Fast genetic programming on • GPUs”. Retrieved 2008-05-01. GPU Rendering Magazine

[38] W Langdon and W Banzhaf. “A SIMD interpreter for Ge- netic Programming on GPU Graphics Cards”. Retrieved 2008-05-01. Chapter 5

Random-access memory

“RAM” redirects here. For the Daft Punk album, see Integrated-circuit RAM chips came into the market in the Random Access Memories. For other uses of the word, late 1960s, with the ﬁrst commercially available DRAM see Ram (disambiguation). chip, the Intel 1103, introduced in October 1970.[3] Random-access memory (RAM /ræm/) is a form of 5.1 History

Example of writable volatile random-access memory: Syn- chronous Dynamic RAM modules, primarily used as main memory in personal computers, workstations, and servers.

computer data storage. A random-access memory device allows data items to be read and written in roughly the same amount of time regardless of the order in which data items are accessed.[1] In contrast, with other direct-access data storage media such as hard disks, CD-RWs, DVD- RWs and the older drum memory, the time required to read and write data items varies significantly depending These IBM tabulating machines from the 1930s used mechanical counters to store information on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds Early computers used relays, mechanical counters[4] or and arm movement delays. delay lines for main memory functions. Ultrasonic delay Today, random-access memory takes the form of lines could only reproduce data in the order it was written. integrated circuits. RAM is normally associated with Drum memory could be expanded at relatively low cost volatile types of memory (such as DRAM memory mod- but efficient retrieval of memory items required knowl- ules), where stored information is lost if power is re- edge of the physical layout of the drum to optimize speed. moved, although many efforts have been made to develop Latches built out of vacuum tube triodes, and later, out non-volatile RAM chips.[2] Other types of non-volatile of discrete transistors, were used for smaller and faster memory exist that allow random access for read oper- memories such as registers. Such registers were relatively ations, but either do not allow write operations or have large and too costly to use for large amounts of data; gen- limitations on them. These include most types of ROM erally only a few dozen or few hundred bits of such mem- and a type of flash memory called NOR-Flash. ory could be provided.

26 5.2. TYPES OF RAM 27

location in any sequence was possible. Magnetic core memory was the standard form of memory system until displaced by solid-state memory in integrated circuits, starting in the early 1970s. Robert H. Dennard invented dynamic random-access memory (DRAM) in 1968; this allowed replacement of a 4 or 6- transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor, and had to be periodically refreshed every few milliseconds before the charge could leak away. Prior to the development of integrated read-only memory (ROM) circuits, permanent (or read-only) random- A portion of a core memory with a modern ﬂash RAM SD card access memory was often constructed using diode matri- on top ces driven by address decoders, or specially wound core rope memory planes.

5.2 Types of RAM

The two main forms of modern RAM are static RAM (SRAM) and dynamic RAM (DRAM). In SRAM, a bit of data is stored using the state of a six transistor memory cell. This form of RAM is more expensive to produce, but is generally faster and requires less power than DRAM and, in modern computers, is often used as cache memory for the CPU. DRAM stores a bit of data using a transistor and capacitor pair, which together comprise a DRAM memory cell. The capacitor holds a high or low 1 Megabit chip – one of the last models developed by VEB Carl charge (1 or 0, respectively), and the transistor acts as a Zeiss Jena in 1989 switch that lets the control circuitry on the chip read the capacitor’s state of charge or change it. As this form of The first practical form of random-access memory was memory is less expensive to produce than static RAM, the Williams tube starting in 1947. It stored data as elec- it is the predominant form of computer memory used in trically charged spots on the face of a cathode ray tube. modern computers. Since the electron beam of the CRT could read and write Both static and dynamic RAM are considered volatile, as the spots on the tube in any order, memory was random their state is lost or reset when power is removed from access. The capacity of the Williams tube was a few hun- the system. By contrast, read-only memory (ROM) stores dred to around a thousand bits, but it was much smaller, data by permanently enabling or disabling selected tran- faster, and more power-efficient than using individual sistors, such that the memory cannot be altered. Write- vacuum tube latches. Developed at the University of able variants of ROM (such as EEPROM and flash mem- Manchester in England, the Williams tube provided the ory) share properties of both ROM and RAM, enabling medium on which the first electronically stored-memory data to persist without power and to be updated with- program was implemented in the Manchester Small-Scale out requiring special equipment. These persistent forms Experimental Machine (SSEM) computer, which first of semiconductor ROM include USB flash drives, mem- successfully ran a program on 21 June 1948.[5] In fact, ory cards for cameras and portable devices, etc. ECC rather than the Williams tube memory being designed for memory (which can be either SRAM or DRAM) includes the SSEM, the SSEM was a testbed to demonstrate the special circuitry to detect and/or correct random faults reliability of the memory.[6][7] (memory errors) in the stored data, using parity bits or Magnetic-core memory was invented in 1947 and devel- error correction code. oped up until the mid-1970s. It became a widespread In general, the term RAM refers solely to solid-state form of random-access memory, relying on an array of memory devices (either DRAM or SRAM), and more magnetized rings. By changing the sense of each ring’s specifically the main memory in most computers. In op- magnetization, data could be stored with one bit stored tical storage, the term DVD-RAM is somewhat of a mis- per ring. Since every ring had a combination of address nomer since, unlike CD-RW or DVD-RW it does not wires to select and read or write it, access to any memory need to be erased before reuse. Nevertheless a DVD- 28 CHAPTER 5. RANDOM-ACCESS MEMORY

RAM behaves much like a hard disc drive if somewhat memory available to it.) When the system runs low on slower. physical memory, it can "swap" portions of RAM to the paging ﬁle to make room for new data, as well as to read previously swapped information back into RAM. Exces- 5.3 Memory hierarchy sive use of this mechanism results in thrashing and generally hampers overall system performance, mainly because hard drives are far slower than RAM. Main article: Memory hierarchy

One can read and over-write data in RAM. Many com- 5.4.2 RAM disk puter systems have a memory hierarchy consisting of CPU registers, on-die SRAM caches, external caches, Main article: RAM disk DRAM, paging systems and virtual memory or swap space on a hard drive. This entire pool of memory may be Software can “partition” a portion of a computer’s RAM, referred to as “RAM” by many developers, even though allowing it to act as a much faster hard drive that is called the various subsystems can have very different access a RAM disk. A RAM disk loses the stored data when times, violating the original concept behind the random the computer is shut down, unless memory is arranged to access term in RAM. Even within a hierarchy level such have a standby battery source. as DRAM, the specific row, column, bank, rank, channel, or interleave organization of the components make the access time variable, although not to the extent that rotating 5.4.3 Shadow RAM storage media or a tape is variable. The overall goal of using a memory hierarchy is to obtain the higher possible Sometimes, the contents of a relatively slow ROM chip average access performance while minimizing the total are copied to read/write memory to allow for shorter ac- cost of the entire memory system (generally, the mem- cess times. The ROM chip is then disabled while the ini- ory hierarchy follows the access time with the fast CPU tialized memory locations are switched in on the same registers at the top and the slow hard drive at the bottom). block of addresses (often write-protected). This process, In many modern personal computers, the RAM comes in sometimes called shadowing, is fairly common in both an easily upgraded form of modules called memory mod- computers and embedded systems. ules or DRAM modules about the size of a few sticks of As a common example, the BIOS in typical personal chewing gum. These can quickly be replaced should they computers often has an option called “use shadow BIOS” become damaged or when changing needs demand more or similar. When enabled, functions relying on data from storage capacity. As suggested above, smaller amounts of the BIOS’s ROM will instead use DRAM locations (most RAM (mostly SRAM) are also integrated in the CPU and can also toggle shadowing of video card ROM or other other ICs on the motherboard, as well as in hard-drives, ROM sections). Depending on the system, this may not CD-ROMs, and several other parts of the computer sys- result in increased performance, and may cause incom- tem. patibilities. For example, some hardware may be inac- cessible to the operating system if shadow RAM is used. On some systems the benefit may be hypothetical because 5.4 Other uses of RAM the BIOS is not used after booting in favor of direct hardware access. Free memory is reduced by the size of the [8] In addition to serving as temporary storage and working shadowed ROMs. space for the operating system and applications, RAM is used in numerous other ways. 5.5 Recent developments

5.4.1 Virtual memory Several new types of non-volatile RAM, which will pre- serve data while powered down, are under development. Main article: virtual memory The technologies used include carbon nanotubes and approaches utilizing the magnetic tunnel effect. Amongst Most modern operating systems employ a method of ex- the 1st generation MRAM, a 128 KiB (128 × 210 bytes) tending RAM capacity, known as “virtual memory”. A magnetic RAM (MRAM) chip was manufactured with portion of the computer’s hard drive is set aside for a 0.18 µm technology in the summer of 2003. In June paging file or a scratch partition, and the combination of 2004, Infineon Technologies unveiled a 16 MiB (16 × physical RAM and the paging file form the system’s total 220 bytes) prototype again based on 0.18 µm technology. memory. (For example, if a computer has 2 GB of RAM There are two 2nd generation techniques currently in de- and a 1 GB page file, the operating system has 3 GB total velopment: Thermal Assisted Switching (TAS)[9] which 5.7. SEE ALSO 29

is being developed by Crocus Technology, and Spin tional Microarchitectures which projects a maximum of Torque Transfer (STT) on which Crocus, Hynix, IBM, 12.5% average annual CPU performance improvement and several other companies are working.[10] Nantero between 2000 and 2014. built a functioning carbon nanotube memory prototype 30 A different concept is the processor-memory perfor- 10 GiB (10 × 2 bytes) array in 2004. Whether some of mance gap, which can be addressed by 3D computer these technologies will be able to eventually take a signif- chips that reduce the distance between the logic and icant market share from either DRAM, SRAM, or flash- memory aspects that are further apart in a 2D chip.[14] memory technology, however, remains to be seen. Memory subsystem design requires a focus on the gap, Since 2006, "solid-state drives" (based on flash mem- which is widening over time.[15] The main method of ory) with capacities exceeding 256 gigabytes and perfor- bridging the gap is the use of caches; small amounts mance far exceeding traditional disks have become avail- of high-speed memory that houses recent operations able. This development has started to blur the definition and instructions nearby the processor, speeding up the between traditional random-access memory and “disks”, execution of those operations or instructions in cases dramatically reducing the difference in performance. where they are called upon frequently. Multiple levels Some kinds of random-access memory, such as “Eco- of caching have been developed in order to deal with RAM”, are specifically designed for server farms, where the widening of the gap, and the performance of high- low power consumption is more important than speed.[11] speed modern computers are reliant on evolving caching techniques.[16] These can prevent the loss of performance that the processor has, as it takes less time to perform the computation it has been initiated to complete.[17] There 5.6 Memory wall can be up to a 53% difference between the growth in speed of processor speeds and the lagging speed of main The “memory wall” is the growing disparity of speed memory access.[18] between CPU and memory outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries. From 5.7 See also 1986 to 2000, CPU speed improved at an annual rate of 55% while memory speed only improved at 10%. • CAS latency (CL) Given these trends, it was expected that memory latency would become an overwhelming bottleneck in computer • Hybrid Memory Cube performance.[12] • Multi-channel memory architecture CPU speed improvements slowed significantly partly due to major physical barriers and partly because current CPU • Registered/buffered memory designs have already hit the memory wall in some sense. • RAM parity Intel summarized these causes in a 2005 document.[13] • Memory Interconnect/RAM buses “First of all, as chip geometries shrink and • clock frequencies rise, the transistor leakage Memory geometry current increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by 5.8 Notes and references memory latency, since memory access times have not been able to keep pace with increas- [1] “RAM, ROM, and Flash Memory”. For Dummies. Re- ing clock frequencies. Third, for certain appli- trieved March 1, 2015. cations, traditional serial architectures are be- [2] Gallagher, Sean. “Memory that never forgets: non- coming less efficient as processors get faster volatile DIMMs hit the market”. Ars Technica. (due to the so-called Von Neumann bottleneck), further undercutting any gains that fre- [3] Bellis, Mary. “The Invention of the Intel 1103”. quency increases might otherwise buy. In ad- [4] “IBM Archives -- FAQ’s for Products and Services”. dition, partly due to limitations in the means ibm.com. of producing inductance within solid state devices, resistance-capacitance (RC) delays in [5] Napper, Brian, Computer 50: The University of Manch- signal transmission are growing as feature sizes ester Celebrates the Birth of the Modern Computer, re- shrink, imposing an additional bottleneck that trieved 26 May 2012 frequency increases don't address.” [6] Williams, F.C.; Kilburn, T. (Sep 1948), “Elec- tronic Digital Computers”, Nature 162 (4117): 487, The RC delays in signal transmission were also noted in doi:10.1038/162487a0. Reprinted in The Origins of Clock Rate versus IPC: The End of the Road for Conven- Digital Computers 30 CHAPTER 5. RANDOM-ACCESS MEMORY

[7] Williams, F.C.; Kilburn, T.; Tootill, G.C. (Feb 1951), “Universal High-Speed Digital Computers: A Small- Scale Experimental Machine”, Proc. IEE 98 (61): 13–28, doi:10.1049/pi-2.1951.0004.

[8] “Shadow Ram”. Retrieved 2007-07-24.

[9] The Emergence of Practical MRAM http: //www.crocus-technology.com/pdf/BH%20GSA% 20Article.pdf

[10] “Tower invests in Crocus, tips MRAM foundry deal”. EE- Times.

[11] “EcoRAM held up as less power-hungry option than DRAM for server farms” by Heather Clancy 2008

[12] The term was coined in .

[13] “Platform 2015: Intel® Processor and Platform Evolution for the Next Decade”. March 2, 2005.

[14] Rainer Waser (2012). Nanoelectronics and Information Technology. John Wiley & Sons. p. 790. Retrieved March 31, 2014.

[15] Chris Jesshope and Colin Egan (2006). Advances in Com- puter Systems Architecture: 11th Asia-Paciﬁc Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Pro- ceedings. Springer. p. 109. Retrieved March 31, 2014.

[16] Ahmed Amine Jerraya and Wayne Wolf (2005). Multiprocessor Systems-on-chips. Morgan Kaufmann. p. 90-91. Retrieved March 31, 2014.

[17] Impact of Advances in Computing and Communications Technologies on Chemical Science and Technology. Na- tional Academy Press. 1999. p. 110. Retrieved March 31, 2014.

[18] Celso C. Ribeiro and Simone L. Martins (2004). Experimental and Eﬃcient Algorithms: Third Interna- tional Workshop, WEA 2004, Angra Dos Reis, Brazil, May 25-28, 2004, Proceedings, Volume 3. Springer. p. 529. Retrieved March 31, 2014.

5.9 External links

• Media related to RAM at Wikimedia Commons

• Memory Prices (1957–2014) Chapter 6

Read-only memory

“Read Only Memory” redirects here. For the EP by a non-volatile memory which serves functions typically Chrome, see Read Only Memory (EP). provided by mask ROM, such as storage of program code The notion of read-only data can also refer to ﬁle system and nonvolatile data. permissions. Read-only memory (ROM) is a class of storage 6.1 History

an EPROM medium used in computers and other electronic devices. Data stored in ROM can only be modified slowly, with difficulty, or not at all, so it is mainly used to distribute firmware (software that is very closely tied to specific hardware, and unlikely to need frequent updates). Strictly, read-only memory refers to memory that is hardwired, such as diode matrix and the later mask ROM. Many game consoles use interchangeable ROM cartridges, allow- Although discrete circuits can be altered (in principle), ing for one system to play multiple games.

Integrated Circuits (ICs) cannot and are useless if the data [2] is bad. The fact that such memory can never be changed is Read-only memory was used for Jacquard looms. a large drawback; more recently, ROM commonly refers The simplest type of solid state ROM is as old as to memory that is read-only in normal operation, while semiconductor technology itself. Combinational logic reserving the fact of some possible way to change it. gates can be joined manually to map n-bit address in- Other types of non-volatile memory such as erasable pro- put onto arbitrary values of m-bit data output (a look-up grammable read only memory (EPROM) and electrically table). With the invention of the integrated circuit came erasable programmable read-only memory (EEPROM or mask ROM. Mask ROM consists of a grid of word lines Flash ROM) are sometimes referred to, in an abbrevi- (the address input) and bit lines (the data output), selec- ated way, as “read-only memory” (ROM); although these tively joined together with transistor switches, and can types of memory can be erased and re-programmed mul- represent an arbitrary look-up table with a regular physi- tiple times, writing to this memory takes longer and may cal layout and predictable propagation delay. require diﬀerent procedures than reading the memory.[1] In mask ROM, the data is physically encoded in the cir- When used in this less precise way, “ROM” indicates cuit, so it can only be programmed during fabrication.

31 32 CHAPTER 6. READ-ONLY MEMORY

This leads to a number of serious disadvantages: 6.1.1 Use for storing programs

Every stored-program computer may use a form of non- 1. It is only economical to buy mask ROM in large volatile storage (that is, storage that retains its data when quantities, since users must contract with a foundry power is removed) to store the initial program that runs to produce a custom design. when the computer is powered on or otherwise begins execution (a process known as bootstrapping, often ab- 2. The turnaround time between completing the design breviated to "booting" or “booting up”). Likewise, every for a mask ROM and receiving the finished product non-trivial computer needs some form of mutable mem- is long, for the same reason. ory to record changes in its state as it executes. Forms of read-only memory were employed as non- 3. Mask ROM is impractical for R&D work since de- volatile storage for programs in most early stored- signers frequently need to modify the contents of program computers, such as ENIAC after 1948. (Un- memory as they refine a design. til then it was not a stored-program computer as every program had to be manually wired into the machine, 4. If a product is shipped with faulty mask ROM, the which could take days to weeks.) Read-only memory was only way to fix it is to recall the product and physi- simpler to implement since it needed only a mechanism cally replace the ROM in every unit shipped. to read stored values, and not to change them in-place, and thus could be implemented with very crude elec- tromechanical devices (see historical examples below). Subsequent developments have addressed these short- With the advent of integrated circuits in the 1960s, both comings. PROM, invented in 1956, allowed users to ROM and its mutable counterpart static RAM were im- program its contents exactly once by physically altering plemented as arrays of transistors in silicon chips; how- its structure with the application of high-voltage pulses. ever, a ROM memory cell could be implemented using This addressed problems 1 and 2 above, since a company fewer transistors than an SRAM memory cell, since the can simply order a large batch of fresh PROM chips and latter needs a latch (comprising 5-20 transistors) to reprogram them with the desired contents at its designers’ tain its contents, while a ROM cell might consist of the convenience. The 1971 invention of EPROM essentially absence (logical 0) or presence (logical 1) of one transis- solved problem 3, since EPROM (unlike PROM) can be tor connecting a bit line to a word line.[4] Consequently, repeatedly reset to its unprogrammed state by exposure ROM could be implemented at a lower cost-per-bit than to strong ultraviolet light. EEPROM, invented in 1983, RAM for many years. went a long way to solving problem 4, since an EEPROM Most home computers of the 1980s stored a BASIC in- can be programmed in-place if the containing device pro- terpreter or operating system in ROM as other forms of vides a means to receive the program contents from an non-volatile storage such as magnetic disk drives were too external source (for example, a personal computer via a costly. For example, the Commodore 64 included 64 KB serial cable). Flash memory, invented at Toshiba in the of RAM and 20 KB of ROM contained a BASIC inter- mid-1980s, and commercialized in the early 1990s, is a preter and the "KERNAL" of its operating system. Later form of EEPROM that makes very efficient use of chip home or office computers such as the IBM PC XT of- area and can be erased and reprogrammed thousands of ten included magnetic disk drives, and larger amounts of times without damage. RAM, allowing them to load their operating systems from All of these technologies improved the flexibility of disk into RAM, with only a minimal hardware initializa- ROM, but at a significant cost-per-chip, so that in tion core and bootloader remaining in ROM (known as large quantities mask ROM would remain an econom- the BIOS in IBM-compatible computers). This arrange- ical choice for many years. (Decreasing cost of repro- ment allowed for a more complex and easily upgradeable grammable devices had almost eliminated the market for operating system. mask ROM by the year 2000.) Rewriteable technologies In modern PCs, “ROM” (or flash) is used to store the were envisioned as replacements for mask ROM. basic bootstrapping firmware for the main processor, as The most recent development is NAND flash, also in- well as the various firmware needed to internally con- vented at Toshiba. Its designers explicitly broke from past trol self-contained devices such as graphic cards, hard practice, stating plainly that “the aim of NAND Flash is disks, DVD drives, TFT screens, etc., in the system. To- to replace hard disks,”[3] rather than the traditional use day, many of these “read-only” memories – especially the of ROM as a form of non-volatile primary storage. As of BIOS – are often replaced with Flash memory (see be- 2007, NAND has partially achieved this goal by offering low), to permit in-place reprogramming should the need throughput comparable to hard disks, higher tolerance of for a firmware upgrade arise. However, simple and ma- physical shock, extreme miniaturization (in the form of ture sub-systems (such as the keyboard or some commu- USB flash drives and tiny microSD memory cards, for nication controllers in the integrated circuits on the main example), and much lower power consumption. board, for example) may employ mask ROM or OTP 6.2. TYPES 33

(one-time programmable). ROM and successor technologies such as flash are preva- lent in embedded systems. These are in everything from industrial robots to home appliances and consumer electronics (MP3 players, set-top boxes, etc.) all of which are designed for specific functions, but are based on general- purpose microprocessors. With software usually tightly coupled to hardware, program changes are rarely needed in such devices (which typically lack hard disks for reasons of cost, size, or power consumption). As of 2008, most products use Flash rather than mask ROM, and The first EPROM, an Intel 1702, with the die and wire bonds many provide some means for connecting to a PC for clearly visible through the erase window. firmware updates; for example, a digital audio player might be updated to support a new file format. Some • Programmable read-only memory (PROM), or one- hobbyists have taken advantage of this flexibility to re- time programmable ROM (OTP), can be written to program consumer products for new purposes; for ex- or programmed via a special device called a PROM ample, the iPodLinux and OpenWrt projects have en- programmer. Typically, this device uses high volt- abled users to run full-featured Linux distributions on ages to permanently destroy or create internal links their MP3 players and wireless routers, respectively. (fuses or antifuses) within the chip. Consequently, ROM is also useful for binary storage of cryptographic a PROM can only be programmed once. data, as it makes them difficult to replace, which may be • Erasable programmable read-only memory desirable in order to enhance information security. (EPROM) can be erased by exposure to strong ultraviolet light (typically for 10 minutes or longer), then rewritten with a process that again needs higher 6.1.2 Use for storing data than usual voltage applied. Repeated exposure to UV light will eventually wear out an EPROM, but Since ROM (at least in hard-wired mask form) cannot be the endurance of most EPROM chips exceeds 1000 modified, it is really only suitable for storing data which cycles of erasing and reprogramming. EPROM is not expected to need modification for the life of the de- chip packages can often be identified by the promi- vice. To that end, ROM has been used in many computers nent quartz “window” which allows UV light to to store look-up tables for the evaluation of mathematical enter. After programming, the window is typically and logical functions (for example, a floating-point unit covered with a label to prevent accidental erasure. might tabulate the sine function in order to facilitate faster Some EPROM chips are factory-erased before they computation). This was especially effective when CPUs are packaged, and include no window; these are were slow and ROM was cheap compared to RAM. effectively PROM. Notably, the display adapters of early personal comput- • ers stored tables of bitmapped font characters in ROM. Electrically erasable programmable read-only mem- This usually meant that the text display font could not ory (EEPROM) is based on a similar semiconductor be changed interactively. This was the case for both the structure to EPROM, but allows its entire contents CGA and MDA adapters available with the IBM PC XT. (or selected banks) to be electrically erased, then rewritten electrically, so that they need not be re- The use of ROM to store such small amounts of data moved from the computer (or camera, MP3 player, has disappeared almost completely in modern general- etc.). Writing or flashing an EEPROM is much purpose computers. However, Flash ROM has taken over slower (milliseconds per bit) than reading from a a new role as a medium for mass storage or secondary ROM or writing to a RAM (nanoseconds in both storage of files. cases). • Electrically alterable read-only memory 6.2 Types (EAROM) is a type of EEPROM that can be modified one bit at a time. Writing is a very slow process and again needs higher 6.2.1 Semiconductor based voltage (usually around 12 V) than is used for read access. EAROMs are intended for Classic mask-programmed ROM chips are integrated cir- applications that require infrequent and only cuits that physically encode the data to be stored, and partial rewriting. EAROM may be used as thus it is impossible to change their contents after fab- non-volatile storage for critical system setup rication. Other types of non-volatile solid-state memory information; in many applications, EAROM permit some degree of modification: has been supplanted by CMOS RAM supplied 34 CHAPTER 6. READ-ONLY MEMORY

by mains power and backed-up with a lithium calculators and keyboard encoders for terminals. battery. This ROM was programmed by installing discrete • Flash memory (or simply flash) is a mod- semiconductor diodes at selected locations between ern type of EEPROM invented in 1984. a matrix of word line traces and bit line traces on a Flash memory can be erased and rewritten printed circuit board. faster than ordinary EEPROM, and newer de- • Resistor, capacitor, or transformer matrix ROM, signs feature very high endurance (exceed- used in many computers until the 1970s. Like diode ing 1,000,000 cycles). Modern NAND flash matrix ROM, it was programmed by placing com- makes efficient use of silicon chip area, re- ponents at selected locations between a matrix of sulting in individual ICs with a capacity as word lines and bit lines. ENIAC's Function Tables high as 32 GB as of 2007; this feature, along were resistor matrix ROM, programmed by manu- with its endurance and physical durability, has ally setting rotary switches. Various models of the allowed NAND flash to replace magnetic in IBM System/360 and complex peripheral devices some applications (such as USB flash drives). stored their microcode in either capacitor (called Flash memory is sometimes called flash ROM BCROS for balanced capacitor read-only storage on or flash EEPROM when used as a replacement the 360/50 and 360/65, or CCROS for charged ca- for older ROM types, but not in applications pacitor read-only storage on the 360/30) or trans- that take advantage of its ability to be modi- former (called TROS for transformer read-only stor- fied quickly and frequently. age on the 360/20, 360/40 and others) matrix ROM.

By applying write protection, some types of repro- • Core rope, a form of transformer matrix ROM tech- grammable ROMs may temporarily become read-only nology used where size and weight were critical. memory. This was used in NASA/MIT's Apollo Spacecraft Computers, DEC's PDP-8 computers, and other places. This type of ROM was programmed by hand 6.2.2 Other technologies by weaving “word line wires” inside or outside of ferrite transformer cores. There are other types of non-volatile memory which are not based on solid-state IC technology, including: • Dimond Ring stores, in which wires are threaded through a sequence of large ferrite rings that func- • Optical storage media, such CD-ROM which tion only as sensing devices. These were used in is read-only (analogous to masked ROM). CD- TXE telephone exchanges. R is Write Once Read Many (analogous to • PROM), while CD-RW supports erase-rewrite cy- The perforated metal character mask ("stencil") in cles (analogous to EEPROM); both are designed for Charactron cathode ray tubes, which was used as backwards-compatibility with CD-ROM. ROM to shape a wide electron beam to form a selected character shape on the screen either for display or a scanned electron beam to form a selected Historical examples character shape as an overlay on a video signal.

6.3 Speed

6.3.1 Reading

Although the relative speed of RAM vs. ROM has varied over time, as of 2007 large RAM chips can be read faster than most ROMs. For this reason (and to allow uniform access), ROM content is sometimes copied to RAM or shadowed before its ﬁrst use, and subsequently read from RAM.

Transformer matrix ROM (TROS), from the IBM System 360/20 6.3.2 Writing For those types of ROM that can be electrically modiﬁed, • Diode matrix ROM, used in small amounts in many writing speed is always much slower than reading speed, computers in the 1960s as well as electronic desk and it may need unusually high voltage, the movement 6.6. SEE ALSO 35 of jumper plugs to apply write-enable signals, and spe- with "warez". cial lock/unlock command codes. Modern NAND Flash achieves the highest write speeds of any rewritable ROM technology, with speeds as high as 15 MB/s (or 70 ns/bit), 6.6 See also by allowing (needing) large blocks of memory cells to be written simultaneously. • EEPROM • EPROM

6.4 Endurance and data retention • Flash memory

Because they are written by forcing electrons through a • PROM layer of electrical insulation onto a floating transistor gate, • Random access memory rewriteable ROMs can withstand only a limited number of write and erase cycles before the insulation is perma- • Write-only memory nently damaged. In the earliest EAROMs, this might occur after as few as 1,000 write cycles, while in modern Flash EEPROM the endurance may exceed 1,000,000, 6.7 Terminology but it is by no means infinite. This limited endurance, as well as the higher cost per bit, means that Flash-based • EEPROM: electrically erasable programmable storage is unlikely to completely supplant magnetic disk read-only memory drives in the near future. The timespan over which a ROM remains accurately • EPROM: erasable programmable read-only mem- readable is not limited by write cycling. The data re- ory tention of EPROM, EAROM, EEPROM, and Flash • PROM: programmable read-only memory may be limited by charge leaking from the floating gates of the memory cell transistors. Leakage is accelerated by high temperatures or radiation. Masked ROM and fuse/antifuse PROM do not suffer from this effect, as 6.8 References their data retention depends on physical rather than electrical permanence of the integrated circuit (although fuse [1] Definition of: flash ROM, PC Magazine. re-growth was once a problem in some systems). [2] “History of Computation - Babbage, Boole, Hollerith”. Paul E. Dunne.

[3] See page 6 of Toshiba’s 1993 NAND Flash Applications 6.5 Content images Design Guide.

Main article: ROM image [4] See chapters on “Combinatorial Digital Circuits” and “Se- quential Digital Circuits” in Millman & Grable, Micro- electronics, 2nd ed. The contents of ROM chips in video game console cartridges can be extracted with special software or hardware devices. The resultant memory dump ﬁles are known as ROM images, and can be used to produce duplicate cartridges, or in console emulators. The term originated when most console games were distributed on cartridges containing ROM chips, but achieved such widespread usage that it is still applied to images of newer games distributed on CD-ROMs or other optical media. ROM images of commercial games usually contain copyrighted software. The unauthorized copying and distribution of copyrighted software is usually a violation of copyright laws (in some jurisdictions, duplication of ROM cartridges for backup purposes may be considered fair use). Nevertheless, there is a thriving community en- gaged in the illegal distribution and trading of such software and abandonware. In such circles, the term “ROM images” is sometimes shortened simply to “ROMs” or sometimes changed to “romz” to highlight the connection Chapter 7

BIOS

This article is about the BIOS as found in IBM PC computer to become infected with BIOS rootkits. compatibles. For the general concept, see firmware. For Unified Extensible Firmware Interface (UEFI) was de- similar programs on non-PC systems, see booting. For signed as a successor to BIOS, aiming to address its tech- other uses, see Bios (disambiguation). nical shortcomings.[4] As of 2014, new PC hardware pre- dominantly ships with UEFI firmware. The BIOS (/ˈbaɪ.ɒs/, an acronym for Basic In- put/Output System and also known as the System BIOS, ROM BIOS or PC BIOS) is a type of firmware 7.1 History used during the booting process (power-on startup) on IBM PC compatible computers.[1] The BIOS firmware is built into PCs, and it is the first software they run when The term BIOS (Basic Input/Output System) was in- [5] powered on. The name itself originates from the Basic vented by Gary Kildall and first appeared in the [2][3][6][7] Input/Output System used in the CP/M operating system CP/M operating system in 1975, describing the in 1975.[2][3] Originally proprietary to the IBM PC, the machine-specific part of CP/M loaded during boot time [3] BIOS was reverse engineered by companies looking to that interfaces directly with the hardware. (A CP/M create compatible systems and the interface of that orig- machine usually has only a simple boot loader in its inal system serves as a de facto standard. ROM.) The fundamental purposes of the BIOS are to initialize Versions of MS-DOS, PC DOS or DR-DOS contain a and test the system hardware components, and to load a file called variously "IO.SYS", "IBMBIO.COM", “IBM- boot loader or an operating system from a mass memory BIO.SYS”, or "DRBIOS.SYS"; this file is known as device. The BIOS additionally provides an abstraction the "DOS BIOS" (also known as "DOS I/O System") layer for the hardware, i.e. a consistent way for applica- and contains the lower-level hardware-specific part of tion programs and operating systems to interact with the the operating system. Together with the underly- keyboard, display, and other input/output devices. Vari- ing hardware-specific, but operating system-independent ations in the system hardware are hidden by the BIOS “System BIOS”, which resides in ROM, it represents the from programs that use BIOS services instead of directly analogous to the "CP/M BIOS". accessing the hardware. MS-DOS (PC DOS), which was With the introduction of PS/2 machines, IBM divided the dominant PC operating system from the early 1980s the System BIOS into real-mode and protected mode until the mid 1990s, relied on BIOS services for disk, portions. The real-mode portion was meant to provide keyboard, and text display functions. MS Windows NT, backward-compatibility with existing operating systems Linux, and other protected mode operating systems in such as DOS, and therefore was named “CBIOS” (for general ignore the abstraction layer provided by the BIOS Compatibility BIOS), whereas the “ABIOS” (for Ad- and do not use it after loading, instead accessing the hard- vanced BIOS) provided new interfaces specifically suited ware components directly. for multitasking operating systems such as OS/2. Every BIOS implementation is specifically designed to work with a particular computer or motherboard model, by interfacing with various devices that make up the com- 7.2 User interface plementary system chipset. Originally, BIOS firmware was stored in a ROM chip on the PC motherboard; in The BIOS of the original IBM PC XT had no interac- modern computer systems, the BIOS contents are stored tive user interface. Error codes or messages were dis- on flash memory so it can be rewritten without removing played on the screen, or coded series of sounds were the chip from the motherboard. This allows easy updates generated to signal errors (when the POST had not pro- to the BIOS firmware so new features can be added or ceeded to the point of successfully initializing a video bugs can be fixed, but it also creates a possibility for the display adapter). Options on the PC and XT were set

36 7.3. OPERATION 37 by switches and jumpers on the main board and on pe- RAM through the keyboard port. (Note that no serial or ripheral cards. Starting around the mid-1990s, it became parallel ports were standard on early IBM PCs, but a key- typical for the BIOS ROM to include a “BIOS configu- board port of either the XT or AT / PS/2 type has been ration utility” (BCU[8]) or “BIOS setup utility”, accessed standard on practically every PC and clone.) If the down- at system power-up by a particular key sequence. This load was apparently successful, the BIOS would verify a program allowed the user to set system configuration op- checksum on it and then run it.[10] This feature was in- tions, of the type formerly set using DIP switches, through tended for factory test or diagnostic purposes. While it an interactive menu system controlled through the key- was of limited utility outside of factory or repair facili- board. In the interim period, IBM-compatible PCs— ties, it could be used in a proprietary way to boot the PC including the IBM AT— held configuration settings in as a satellite system to a host machine (which is essen- battery-backed RAM and used a bootable configuration tially the same technical way it was used, if it was used, program on disk, not in the ROM, to set the configuration in the manufacturing environment). options contained in this memory. The disk was supplied with the computer, and if it was lost the system settings could not be changed. 7.3.2 Boot process A modern Wintel-compatible computer provides a setup routine essentially unchanged in nature from the ROM- After the option ROM scan is completed and all detected resident BIOS setup utilities of the late 1990s; the user ROM modules with valid checksums have been called, can configure hardware options using the keyboard and or immediately after POST in a BIOS version that does video display. Also, when errors occur at boot time, a not scan for option ROMs, the BIOS calls INT 19h to modern BIOS usually displays user-friendly error mes- start boot processing. Post-boot, Programs loaded can sages, often presented as pop-up boxes in a TUI style, also call INT 19h to reboot the system, but they must be and offers to enter the BIOS setup utility or to ignore the careful to disable interrupts and other asynchronous hard- error and proceed if possible. Instead of battery-backed ware processes that may interfere with the BIOS reboot- RAM, the modern Wintel machine may store the BIOS ing process, or else the system may hang or crash while it configuration settings in flash ROM, perhaps the same is rebooting. Unique to the original IBM BIOS was that flash ROM that holds the BIOS itself. it would attempt to load a maintenance program through the keyboard port before performing any other elements of the boot process, such as before scanning for option [11] 7.3 Operation ROMs or executing a boot loader. When INT 19h is called, the BIOS attempts to locate boot loader software held on a storage device designated as a 7.3.1 System startup “boot device”, such as a hard disk, a floppy disk, CD, or DVD. It loads and executes the first boot software it finds, Early Intel processors started at physical address giving it control of the PC.[12] This is the process that is 000FFFF0h. When a modern x86 microprocessor is re- known as booting (sometimes informally called “booting set, it starts in pseudo 16-bit real mode, initializing most up”), which is short for “bootstrapping”. registers to zero. The code segment register is initialized with selector F000h, base FFFF0000h, and limit The BIOS selects candidate boot devices using informa- FFFFh, so that execution starts at 4 GB minus 16 bytes tion collected by POST and configuration information (FFFFFFF0h).[9] The platform logic maps this address from EEPROM, CMOS RAM or, in the earliest PCs, into the system ROM, mirroring address 000FFFF0h. DIP switches. Following the boot priority sequence in effect, BIOS checks each device in order to see if it is If the system has just been powered up or the reset but- bootable. For a disk drive or a device that logically em- ton was pressed (“cold boot”), the full power-on self-test ulates a disk drive, such as a USB Flash drive or perhaps (POST) is run. If Ctrl+Alt+Delete was pressed (“warm a tape drive, to perform this check the BIOS attempts to boot”), a special flag value is stored in nonvolatile BIOS load the first sector (boot sector) from the disk into RAM memory (“CMOS”) before the processor is reset, and af- at memory address 0x0000:0x7C00. If the sector cannot ter the reset the BIOS startup code detects this flag and be read (due to a missing or unformatted disk, or due to does not run the POST. This saves the time otherwise a hardware failure), the BIOS considers the device unused to detect and test all memory. bootable and proceeds to check the next device. If the The POST checks, identifies, and initializes system de- sector is read successfully, some BIOSes will also check vices such as the CPU, RAM, interrupt and DMA con- for the boot sector signature 0x55 0xAA in the last two trollers and other parts of the chipset, video display card, bytes of the (512 byte long) sector, before accepting a keyboard, hard disk drive, optical disc drive and other boot sector and considering the device bootable.[nb 1] basic hardware. The BIOS proceeds to test each device sequentially until Early IBM PCs had a little-known routine in the POST a bootable device is found, at which time the BIOS trans- that would attempt to download a program from into fers control to the loaded sector with a jump instruction 38 CHAPTER 7. BIOS

to its first byte at address 0x0000:0x7C00 (exactly 1 KiB boot purposes. Optical disks are a special case, because below the 32 KiB mark); see MBR invocation and VBR their lowest level of data organization is typically a fairly invocation. (This location is one reason that an IBM PC high-level file system (e.g. ISO 9660 for CD-ROM). requires at least 32 KiB of RAM in order to be equipped Reading the “first sector” of a CD-ROM or DVD-ROM is with a disk system; with 31 KiB or less, it would be im- not a simply defined operation like it is on a floppy disk or possible to boot from any disk, removable or fixed, using a hard disk. Furthermore, the complexity of the medium the BIOS boot protocol.) Most, but not all, BIOSes load makes it difficult to write a useful boot program in one the drive number (as used by INT 13h) of the boot drive sector, even though optical media sectors are typically into CPU register DL before jumping to the first byte of 2048 bytes each, four times the standard 512-byte size the loaded boot sector. of floppy and legacy hard disk sectors. Therefore, optical Note well that the BIOS does not interpret or process the media booting uses the El Torito standard, which speci- contents of the boot sector other than to possibly check fies a way for an optical disk to contain an image of a high- for the boot sector signature in the last two bytes; all density (1.44 MB) floppy disk and for the drive to provide interpretation of data structures like MBR partition ta- access to this disk image in a simple manner that emulates bles and so-called BIOS Parameter Blocks is done by the floppy disk drive operations. Therefore, CD-ROM drives boot program in the boot sector itself or by other pro- boot as emulated floppy disk drives; the bootable virtual grams loaded through the boot process and is beyond the floppy disk can contain software that provides access to scope of BIOS. Nothing about BIOS predicates these data the optical medium in its native format. structures or impedes their replacement or improvement.

A non-disk device such as a network adapter attempts Boot failure booting by a procedure that is defined by its option ROM or the equivalent integrated into the motherboard BIOS The behavior if the BIOS does not find a bootable device ROM. As such, option ROMs may also influence or sup- has varied as personal computers developed. The origi- plant the boot process defined by the motherboard BIOS nal IBM PC and XT had Microsoft Cassette BASIC in ROM. ROM, and if no bootable device was found, ROM BA- SIC was started by calling INT 18h. Therefore, barring a hardware failure, an original IBM PC or XT would never Boot priority fail to boot, either into BASIC or from disk (or through an option ROM). One model of the original IBM PC was The user can control the boot process, to cause one available with no disk drive; a cassette recorder could be medium to be booted instead of another when two or attached via the cassette port on the rear, for loading and more bootable media are present, by taking advantage of saving BASIC programs to tape. Since few programs the boot priority implemented by the BIOS. For exam- used BASIC in ROM, clone PC makers left it out; then ple, most computers have a hard disk that is bootable, but a computer that failed to boot from a disk would display usually there is a removable-media drive that has higher “No ROM BASIC” and halt (in response to INT 18h). boot priority, so the user can cause a removable disk to be booted, simply by inserting it, without removing the hard Later computers would display a message like “No disk drive or altering its contents to make it unbootable. bootable disk found"; some would prompt for a disk to be inserted and a key to be pressed, and when a key In most modern BIOSes, the boot priority order of all was pressed they would restart the boot process. A mod- potentially bootable devices can be freely configured by ern BIOS may display nothing or may automatically en- the user through the BIOS configuration utility. In older ter the BIOS configuration utility when the boot process BIOSes, limited boot priority options are selectable; in fails. Unlike earlier BIOSes, modern versions are often the earliest BIOSes, a fixed priority scheme was imple- written with the assumption that if the computer cannot mented, with floppy disk drives first, fixed disks (i.e. hard be booted from a hard disk, the user will not have soft- disks) second, and typically no other boot devices sup- ware that they want to boot from removable media in- ported, subject to modification of these rules by installed stead. (Lately, typically it will only be a specialist com- option ROMs. The BIOS in an early PC also usually puter technician who does that, only to get the computer would only boot from the first floppy disk drive or the back into a condition where it can be booted from the first hard disk drive, even if there were two drives of ei- hard disk.) ther type installed. All more advanced boot priority sequences evolved as incremental improvements on this basic system. 7.3.3 Boot environment Historically the BIOS would try to boot from a floppy drive first and a hard disk second. The default for CD or The environment for the boot program is very simple: the DVD booting is an extension of this. With the El Torito CPU is in real mode and the general-purpose and segment optical media boot standard, the optical drive actually registers are undefined, except CS, SS, SP, and DL. CS emulates a 3.5” high-density floppy disk to the BIOS for is always zero and IP is initially 0x7C00. Because boot 7.4. EXTENSIONS (OPTION ROMS) 39 programs are always loaded at this fixed address, there is troller. Some video cards have extension ROMs that re- no need or motivation for a boot program to be relocat- place the video services of the motherboard BIOS with able. DL contains the drive number, as used with INT their own video services. BIOS extension ROMs gain to- 13h, of the boot device, unless the BIOS is one that does tal control of the machine, so they can in fact do anything, not set the drive number in DL – and then DL is unde- and they may never return control to the BIOS that in- fined. SS:SP points to a valid stack that is presumably voked them. An extension ROM could in principle con- large enough to support hardware interrupts, but other- tain an entire operating system or an application program, wise SS and SP are undefined. (A stack must be already or it could implement an entirely different boot process set up in order for interrupts to be serviced, and inter- such as booting from a network. Operation of an IBM- rupts must be enabled in order for the system timer-tick compatible computer system can be completely changed interrupt, which BIOS always uses at least to maintain the by removing or inserting an adapter card (or a ROM chip) time-of-day count and which it initializes during POST, that contains a BIOS extension ROM. to be active and for the keyboard to work. The keyboard The motherboard BIOS typically contains code to ac- works even if the BIOS keyboard service is not called; cess hardware components necessary for bootstrapping keystrokes are received and placed in the 15-character the system, such as the keyboard, display, and storage. type-ahead buffer maintained by BIOS.) The boot pro- In addition, plug-in adapter cards such as SCSI, RAID, gram must set up its own stack (or at least MS-DOS 6 network interface cards, and video boards often include acts like it must), because the size of the stack set up by their own BIOS (e.g. Video BIOS), complementing or re- BIOS is unknown and its location is likewise variable; al- placing the system BIOS code for the given component. though the boot program can investigate the default stack Even devices built into the motherboard can behave in by examining SS:SP, it is easier and shorter to just un- this way; their option ROMs can be stored as separate conditionally set up a new stack. code on the main BIOS flash chip, and upgraded either in At boot time, all BIOS services are available, and the tandem with, or separately from, the main BIOS. memory below address 0x00400 contains the interrupt An add-in card requires an option ROM if the card is not vector table. BIOS POST has initialized the system supported by the main BIOS and the card needs to be ini- timers (8253 or 8254 IC), interrupt controller(s), DMA tialized or made accessible through BIOS services before controller(s), and other motherboard/chipset hardware the operating system can be loaded (usually this means it as necessary to bring all BIOS services to ready status. is required in the bootstrapping process). Even when it is DRAM refresh for all system DRAM in conventional not required, an option ROM can allow an adapter card memory and extended memory, but not necessarily ex- to be used without loading driver software from a storage panded memory, has been set up and is running. The device after booting begins – with an option ROM, no interrupt vectors corresponding to the BIOS interrupts time is taken to load the driver, the driver does not take have been set to point at the appropriate entry points in up space in RAM nor on hard disk, and the driver soft- the BIOS, hardware interrupt vectors for devices initial- ware on the ROM always stays with the device so the two ized by the BIOS have been set to point to the BIOS- cannot be accidentally separated. Also, if the ROM is on provided ISRs, and some other interrupts, including ones the card, both the peripheral hardware and the driver soft- that BIOS generates for programs to hook, have been set ware provided by the ROM are installed together with no to a default dummy ISR that immediately returns. The extra effort to install the software. An additional advan- BIOS maintains a reserved block of system RAM at ad- tage of ROM on some early PC systems (notably includ- dresses 0x00400–0x004FF with various parameters ini- ing the IBM PCjr) was that ROM was faster than main tialized during the POST. All memory at and above ad- system RAM. (On modern systems, the case is very much dress 0x00500 can be used by the boot program; it may the reverse of this, and BIOS ROM code is usually copied even overwrite itself. (“shadowed”) into RAM so it will run faster.) There are many methods and utilities for examining the contents of various motherboard BIOS and expansion 7.4 Extensions (option ROMs) ROMs, such as Microsoft DEBUG or the Unix dd.

Peripheral cards such as some hard disk drive controllers and some video display adapters have their own BIOS ex- 7.4.1 Boot procedure tension option ROMs, which provide additional functionality to BIOS. Code in these extensions runs before the If an expansion ROM wishes to change the way the sys- BIOS boots the system from mass storage. These ROMs tem boots (such as from a network device or a SCSI typically test and initialize hardware, add new BIOS ser- adapter for which the BIOS has no driver code) in a coop- vices, and augment or replace existing BIOS services with erative way, it can use the BIOS Boot Speciﬁcation (BBS) their own versions of those services. For example, a API to register its ability to do so. Once the expansion SCSI controller usually has a BIOS extension ROM that ROMs have registered using the BBS APIs, the user can adds support for hard drives connected through that con- select among the available boot options from within the 40 CHAPTER 7. BIOS

BIOS’s user interface. This is why most BBS compliant An option ROM should normally return to the BIOS af- PC BIOS implementations will not allow the user to enter completing its initialization process. Once (and if) an ter the BIOS’s user interface until the expansion ROMs option ROM returns, the BIOS continues searching for have finished executing and registering themselves with more option ROMs, calling each as it is found, until the the BBS API. The specification can be downloaded from entire option ROM area in the memory space has been the ACPICA website. The official title is BIOS Boot scanned. Specification (Version 1.01, 11 January 1996).[13] Also, if an expansion ROM wishes to change the way the system boots unilaterally, it can simply hook INT 19h or 7.4.3 Physical placement other interrupts normally called from interrupt 19h, such Option ROMs normally reside on adapter cards. How- as INT 13h, the BIOS disk service, to intercept the BIOS ever, the original PC, and perhaps also the PC XT, have boot process. Then it can replace the BIOS boot pro- a spare ROM socket on the motherboard (the “system cess with one of its own, or it can merely modify the board” in IBM’s terms) into which an option ROM can boot sequence by inserting its own boot actions into it, be inserted, and the four ROMs that contain the BASIC by preventing the BIOS from detecting certain devices interpreter can also be removed and replaced with cus- as bootable, or both. Before the BIOS Boot Specifica- tom ROMs which can be option ROMs. The IBM PCjr tion was promulgated, this was the only way for expan- is unique among PCs in having two ROM cartridge slots sion ROMs to implement boot capability for devices not on the front. Cartridges in these slots map into the same supported for booting by the native BIOS of the mother- region of the upper memory area used for option ROMs, board. and the cartridges can contain option ROM modules that the BIOS would recognize. The cartridges can also contain other types of ROM modules, such as BASIC pro- 7.4.2 Initialization grams, that are handled differently. One PCjr cartridge can contain several ROM modules of different types, pos- After the motherboard BIOS completes its POST, most sibly stored together in one ROM chip. BIOS versions search for option ROM modules, also called BIOS extension ROMs, and execute them. The motherboard BIOS scans for extension ROMs in a por- 7.5 Operating system services tion of the "upper memory area" (the part of the x86 real- mode address space at and above address 0xA0000) and runs each ROM found, in order. To discover memory- The BIOS ROM is customized to the particular manu- mapped ISA option ROMs, a BIOS implementation facturer’s hardware, allowing low-level services (such as scans the real-mode address space from 0x0C0000 to reading a keystroke or writing a sector of data to diskette) 0x0F0000 on 2 KiB boundaries, looking for a two-byte to be provided in a standardized way to programs, includ- ROM signature: 0x55 followed by 0xAA. In a valid ex- ing operating systems. For example, an IBM PC might pansion ROM, this signature is followed by a single byte have either a monochrome or a color display adapter (using different display memory addresses and hardware), indicating the number of 512-byte blocks the expansion ROM occupies in real memory, and the next byte is the but a single, standard, BIOS system call may be invoked to display a character at a specified position on the screen option ROM’s entry point (also known as its “entry offset”). A checksum of the specified number of 512-byte in text mode or graphics mode. blocks is calculated, and if the ROM has a valid check- The BIOS provides a small library of basic input/output sum, the BIOS transfers control to the entry address, functions to operate peripherals (such as the keyboard, which in a normal BIOS extension ROM should be the rudimentary text and graphics display functions and so beginning of the extension’s initialization routine. forth). When using MS-DOS, BIOS services could be At this point, the extension ROM code takes over, typi- accessed by an application program (or by MS-DOS) by cally testing and initializing the hardware it controls and executing an INT 13h interrupt instruction to access disk registering interrupt vectors for use by post-boot appli- functions, or by executing one of a number of other docu- cations. It may use BIOS services (including those pro- mented BIOS interrupt calls to access video display, key- vided by previously initialized option ROMs) to provide board, cassette, and other device functions. a user configuration interface, to display diagnostic infor- Operating systems and executive software that are de- mation, or to do anything else that it requires. While the signed to supersede this basic firmware functionality pro- actions mentioned are typical behaviors of BIOS exten- vide replacement software interfaces to application soft- sion ROMs, each option ROM receives total control of ware. Applications can also provide these services to the computer and may do anything at all, as noted with themselves. This began even in the 1980s under MS- more detail in the Extensions section below; it is possible DOS, when programmers observed that using the BIOS that an option ROM will not return to BIOS, pre-empting video services for graphics display was very slow. To in- the BIOS’s boot sequence altogether. crease the speed of screen output, many programs by- 7.6. CONFIGURATION 41 passed the BIOS and programmed the video display hard- OEM key (either SLP or COA) and the digital certifi- ware directly. Other graphics programmers, particularly cate for their SLIC in order to bypass activation.[17] This but not exclusively in the demoscene, observed that there can be achieved if the user performs a restore using a pre- were technical capabilities of the PC display adapters that customised image provided by the OEM. Power users can were not supported by the IBM BIOS and could not be copy the necessary certificate files from the OEM image, taken advantage of without circumventing it. Since the decode the SLP product key, then perform SLP activa- AT-compatible BIOS ran in Intel real mode, operating tion manually. Cracks for non-genuine Windows distri- systems that ran in protected mode on 286 and later pro- butions usually edit the SLIC or emulate it in order to cessors required hardware device drivers compatible with bypass Windows activation. protected mode operation to replace BIOS services. In modern personal computers running modern operating 7.5.3 Overclocking systems the BIOS is used only during booting and initial loading of system software. Before the operating system’s Some BIOS implementations allow overclocking, an ac- first graphical screen is displayed, input and output are tion in which the CPU is adjusted to a higher clock typically handled through BIOS. A boot menu such as the rate than its manufacturer rating for guaranteed capa- textual menu of Windows, which allows users to choose bility. Overclocking may, however, seriously compro- an operating system to boot, to boot into the safe mode, mise system reliability in insufficiently cooled computers or to use the last known good configuration, is displayed and generally shorten component lifespan. Overclock- through BIOS and receives keyboard input through BIOS. ing, when incorrectly performed, may also cause com- However, it is also important to note that modern PCs ponents to overheat so quickly that they mechanically de- can still boot and run legacy operating systems such as stroy themselves.[19] MS-DOS or DR-DOS that rely heavily on BIOS for their console and disk I/O. Thus, while not as central as they once were, the BIOS services are still important. 7.5.4 Modern use

Some operating systems, for example MS-DOS, rely on 7.5.1 Processor microcode updates the BIOS to carry out most input/output tasks within the PC.[20] Intel processors have reprogrammable microcode since Because the BIOS still runs in 16-bit real mode, calling [14][15] the P6 microarchitecture. The BIOS may contain BIOS services directly is inefficient for protected-mode patches to the processor microcode that fix errors in operating systems. BIOS services are not used by mod- the initial processor microcode; reprogramming is not ern multitasking GUI operating systems after they ini- persistent, thus loading of microcode updates is per- tially load, so the importance of the primary part of BIOS formed each time the system is powered up. Without reis greatly reduced from what it was initially. programmable microcode, an expensive processor swap would be required;[16] for example, the Pentium FDIV Later BIOS implementations took on more complex bug became an expensive fiasco for Intel as it required a functions, by including interfaces such as Advanced Con- product recall because the original Pentium processor’s figuration and Power Interface (ACPI); these functions defective microcode could not be reprogrammed. include power management, hot swapping, and thermal management. At the same time, since 2010 BIOS technology is in a transitional process toward the UEFI.[4] 7.5.2 Identification

Some BIOSes contain a software licensing description ta- 7.6 Configuration ble (SLIC), a digital signature placed inside the BIOS by the manufacturer, for example Dell. The SLIC is inserted 7.6.1 Setup utility into the ACPI table and contains no active code.[17][18] Computer manufacturers that distribute OEM versions of Historically, the BIOS in the IBM PC and XT had no Microsoft Windows and Microsoft application software built-in user interface. The BIOS versions in earlier PCs can use the SLIC to authenticate licensing to the OEM (XT-class) were not software configurable; instead, users Windows Installation disk and system recovery disc con- set the options via DIP switches on the motherboard. taining Windows software. Systems having a SLIC can be Later computers, including all IBM-compatibles with preactivated with an OEM product key, and they verify an 80286 CPUs, had a battery-backed nonvolatile BIOS XML formatted OEM certificate against the SLIC in the memory (CMOS RAM chip) that held BIOS settings.[21] BIOS as a means of self-activating (see System Locked These settings, such as video-adapter type, memory size, Preinstallation, SLP). If a user performs a fresh install of and hard-disk parameters, could only be configured by Windows, they will need to have possession of both the running a configuration program from a disk, not built 42 CHAPTER 7. BIOS into the ROM. A special “reference diskette” was inserted 7.6.2 Reprogramming in an IBM AT to configure settings such as memory size. Early BIOS versions did not have passwords or boot- In modern PCs the BIOS is stored in rewritable memory, device selection options. The BIOS was hard-coded to allowing the contents to be replaced or “rewritten”. This boot from the first floppy drive, or, if that failed, the first rewriting of the contents is sometimes termed flashing, hard disk. Access control in early AT-class machines was based on the common use of a kind of EEPROM known by a physical keylock switch (which was not hard to de- technically as “flash EEPROM” and colloquially as “flash feat if the computer case could be opened). Anyone who memory”. It can be done by a special program, usually could switch on the computer could boot it. provided by the system’s manufacturer, or at POST, with a BIOS image in a hard drive or USB flash drive. A file Later, 386-class computers started integrating the BIOS containing such contents is sometimes termed “a BIOS setup utility in the ROM itself, alongside the BIOS code; image”. A BIOS might be reflashed in order to upgrade these computers usually boot into the BIOS setup utility to a newer version to fix bugs or provide improved per- if a certain key or key combination is pressed, otherwise formance or to support newer hardware, or a reflashing the BIOS POST and boot process are executed. operation might be needed to fix a damaged BIOS.

7.7 Hardware

Award BIOS setup utility on a standard PC

A modern BIOS setup utility has a menu-based user interface (UI) accessed by pressing a certain key on the keyboard when the PC starts. Usually the key is advertised for short time during the early startup, for example “Press F1 to enter CMOS setup”. The actual key depends on specific hardware. Features present in the BIOS setup utility typically include: PhoenixBIOS D686. This BIOS chip is housed in a PLCC package • Configuring the hardware components, including in a socket. setting their various operating modes and frequencies (for example, selecting how the storage con- The original IBM PC BIOS (and cassette BASIC) trollers are visible to the operating system, or over- was stored on mask-programmed read-only memory locking the CPU) (ROM) chips in sockets on the motherboard. ROMs could be replaced, but not altered, by users. To al- • Setting the system clock low for updates, many compatible computers used re- • Enabling or disabling system components programmable memory devices such as EPROM and later flash memory devices. According to Robert • Selecting which devices are potential boot devices, Braver, the president of the BIOS manufacturer Micro and in which order booting from them will be at- Firmware, Flash BIOS chips became common around tempted 1995 because the electrically erasable PROM (EEP- • Setting various passwords, such as a password for ROM) chips are cheaper and easier to program than stan- securing access to the BIOS user interface functions dard ultraviolet erasable PROM (EPROM) chips. Flash itself and preventing malicious users from booting chips are programmed (and re-programmed) in-circuit, while EPROM chips need to be removed from the moth- the system from unauthorized portable storage de- [22] vices, a password for booting the system, or a hard erboard for re-programming. BIOS versions are upgraded to take advantage of newer versions of hardware disk drive password that limits access to it and stays [23] assigned even if the hard disk drive is moved to an- and to correct bugs in previous revisions of BIOSes. other computer. Beginning with the IBM AT, PCs supported a hardware 7.9. SECURITY 43

clock settable through BIOS. It had a century bit which New standards grafted onto the BIOS are usually without allowed for manually changing the century when the year complete public documentation or any BIOS listings. As 2000 happened. Most BIOS revisions created in 1995 a result, it is not as easy to learn the intimate details about and nearly all BIOS revisions in 1997 supported the year the many non-IBM additions to BIOS as about the core 2000 by setting the century bit automatically when the BIOS services. [24] clock rolled past midnight, December 31, 1999. Most PC motherboard suppliers license a BIOS “core” The first flash chips were attached to the ISA bus. Starting and toolkit from a commercial third-party, known as an in 1997, the BIOS flash moved to the LPC bus, a func- “independent BIOS vendor” or IBV. The motherboard tional replacement for ISA, following a new standard im- manufacturer then customizes this BIOS to suit its own plementation known as “firmware hub” (FWH). In 2006, hardware. For this reason, updated BIOSes are nor- the first systems supporting a Serial Peripheral Interface mally obtained directly from the motherboard manufac- (SPI) appeared, and the BIOS flash memory moved again. turer. Major BIOS vendors include American Mega- The size of the BIOS, and the capacity of the ROM, EEP- trends (AMI), Insyde Software, Phoenix Technologies ROM, or other media it may be stored on, has increased and Byosoft. Former vendors include Award Software over time as new features have been added to the code; and Microid Research which were acquired by Phoenix BIOS versions now exist with sizes up to 16 megabytes. Technologies in 1998; Phoenix later phased out the For contrast, the original IBM PC BIOS was contained Award Brand name. General Software, which was also in an 8 KiB mask ROM. Some modern motherboards acquired by Phoenix in 2007, sold BIOS for Intel proces- are including even bigger NAND flash memory ICs on sor based embedded systems. board which are capable of storing whole compact op- The open source community increased their effort to de- erating systems, such as some Linux distributions. For velop a replacement for proprietary BIOSes and their example, some ASUS motherboards included SplashTop future incarnations with an open sourced counterpart Linux embedded into their NAND flash memory ICs.[25] through the coreboot and OpenBIOS/Open Firmware However, the idea of including an operating system along projects. AMD provided product specifications for with BIOS in the ROM of a PC is not new; in the 1980s, some chipsets, and Google is sponsoring the project. Microsoft offered a ROM option for MS-DOS, and it Motherboard manufacturer Tyan offers coreboot next to was included in the ROMs of some PC clones such as the standard BIOS with their Opteron line of mother- the Tandy 1000 HX. boards. MSI and Gigabyte Technology have followed suit Another type of firmware chip was found on the IBM PC with the MSI K9ND MS-9282 and MSI K9SD MS-9185 AT and early compatibles. In the AT, the keyboard in- resp. the M57SLI-S4 models. terface was controlled by a microcontroller with its own programmable memory. On the IBM AT, that was a 40-pin socketed device, while some manufacturers used 7.9 Security an EPROM version of this chip which resembled an EPROM. This controller was also assigned the A20 gate function to manage memory above the one-megabyte range; occasionally an upgrade of this “keyboard BIOS” was necessary to take advantage of software that could use upper memory. The BIOS may contain components such as the Memory Reference Code (MRC), which is responsible for handling memory timings and related hardware settings.[26]:8[27]

7.8 Vendors and products

IBM published the entire listings of the BIOS for its orig- An American Megatrends BIOS showing a "Intel CPU uCode inal PC, PC XT, PC AT, and other contemporary PC Loading Error” after a failed attempt to upload microcode models, in an appendix of the Technical Reference man- patches into the CPU. ual for each machine type. The effect of the publication of the BIOS listings is that anyone can see exactly what a EEPROM chips are advantageous because they can be definitive BIOS does and how it does it. Phoenix Tech- easily updated by the user; hardware manufacturers fre- nologies was the first company to write a fully compatible quently issue BIOS updates to upgrade their products, and completely legal BIOS through clean-room reverse improve compatibility and remove bugs. However, this engineering. advantage had the risk that an improperly executed or 44 CHAPTER 7. BIOS

cess. As a result, as of 2008, CIH has become essentially harmless, at worst causing annoyance by infecting executable files and triggering antivirus software. Other BIOS viruses remain possible, however;[28] since most Windows home users without Windows Vista/7’s UAC run all applications with administrative privileges, a modern CIH-like virus could in principle still gain access to hardware without first using an exploit. The operating system OpenBSD prevents all users from having this access and the grsecurity patch for the linux kernel also prevents this direct hardware access by default, the difference being an attacker requiring a much more difficult kernel level exploit or reboot of the machine. Detached BIOS Chip The second BIOS virus was a technique presented by John Heasman, principal security consultant for UK- based Next-Generation Security Software. In 2006, at aborted BIOS update could render the computer or device the Black Hat Security Conference, he showed how to unusable. To avoid these situations, more recent BIOSes elevate privileges and read physical memory, using ma- use a “boot block"; a portion of the BIOS which runs first licious procedures that replaced normal ACPI functions and must be updated separately. This code verifies if the stored in flash memory. rest of the BIOS is intact (using hash checksums or other methods) before transferring control to it. If the boot The third BIOS virus was a technique called “Persistent block detects any corruption in the main BIOS, it will BIOS infection.” It appeared in 2009 at the CanSecWest typically warn the user that a recovery process must be Security Conference in Vancouver, and at the SyScan initiated by booting from removable media (floppy, CD Security Conference in Singapore. Researchers Anibal or USB memory) so the user can try flashing the BIOS Sacco[29] and Alfredo Ortega, from Core Security Tech- again. Some motherboards have a backup BIOS (some- nologies, demonstrated how to insert malicious code into times referred to as DualBIOS boards) to recover from the decompression routines in the BIOS, allowing for BIOS corruptions. nearly full control of the PC at start-up, even before the operating system is booted. The proof-of-concept does There are at least four known BIOS attack viruses, two not exploit a flaw in the BIOS implementation, but only of which were for demonstration purposes. The first one involves the normal BIOS flashing procedures. Thus, it found in the wild was Mebromi, targeting Chinese users. requires physical access to the machine, or for the user to The first BIOS virus was CIH, whose name matches be root. Despite these requirements, Ortega underlined the initials of its creator, Chen Ing Hau. CIH was also the profound implications of his and Sacco’s discovery: called the “Chernobyl Virus”, because its payload date “We can patch a driver to drop a fully working rootkit. was 1999-04-26, the 13th anniversary of the Chernobyl We even have a little code that can remove or disable accident. CIH appeared in mid-1998 and became active antivirus.”[30] in April 1999. It was able to erase flash ROM BIOS con- Mebromi is a trojan which targets computers with tent. Often, infected computers could no longer boot, AwardBIOS, Microsoft Windows, and antivirus soft- and people had to remove the flash ROM IC from the ware from two Chinese companies: Rising Antivirus motherboard and reprogram it. CIH targeted the then- and Jiangmin KV Antivirus.[31][32][33] Mebromi installs widespread Intel i430TX motherboard chipset and took a rootkit which infects the master boot record. advantage of the fact that the Windows 9x operating systems, also widespread at the time, allowed direct hard- In a December 2013 interview with CBS 60 Minutes, ware access to all programs. Deborah Plunkett, Information Assurance Director for the US National Security Agency claimed that NSA an- Modern systems are not vulnerable to CIH because of alysts had uncovered and thwarted a possible BIOS at- a variety of chipsets being used which are incompatible tack by a foreign nation state. The attack on the world’s with the Intel i430TX chipset, and also other flash ROM computers could have allegedly “literally taken down the IC types. There is also extra protection from accidental US economy.” The segment further cites anonymous cy- BIOS rewrites in the form of boot blocks which are pro- ber security experts briefed on the operation as alleging tected from accidental overwrite or dual and quad BIOS the plot was conceived in China.[34] A later article in The equipped systems which may, in the event of a crash, use Guardian cast doubt on the likelihood of such a threat, a backup BIOS. Also, all modern operating systems such quoting Berkeley computer-science researcher Nicholas as FreeBSD, Linux, OS X, Windows NT-based Windows Weaver, Matt Blaze, a computer and information sciences OS like Windows 2000, Windows XP and newer, do not professor at the University of Pennsylvania, and cyberse- allow user-mode programs to have direct hardware ac- 7.13. REFERENCES 45 curity expert Robert David Graham in an analysis of the have to be written as 0x55AA in programs for other CPU NSA’s claims.[35] architectures using a big-endian representation. Since this has been mixed up numerous times in books and even in original Microsoft reference documents, this article uses the offset-based byte-wise on-disk representation to avoid 7.10 Alternatives and successors any possible misinterpretation.

For comparable software on other computer systems, see booting. 7.13 References

As of 2011, the BIOS is being replaced by the more com- [1] “Ref — System BIOS”. PCGuide. Retrieved 6 December plex Extensible Firmware Interface (EFI) in many new 2014. machines. EFI is a specification which replaces the runtime interface of the legacy BIOS. Initially written for the [2] Kildall, Gary A. (June 1975), CP/M 1.1 or 1.2 BIOS and Itanium architecture, EFI is now available for x86 and BDOS for Lawrence Livermore Laboratories x86-64 platforms; the specification development is driven [3] Kildall, Gary A. (January 1980). “The History of CP/M, by The Unified EFI Forum, an industry Special Interest THE EVOLUTION OF AN INDUSTRY: ONE PER- Group. EFI booting has been supported in only Microsoft SON'S VIEWPOINT” (Vol. 5, No. 1, Number 41 ed.). [36] Windows versions supporting GPT, the Linux kernel Dr. Dobb’s Journal of Computer Calisthenics & Or- 2.6.1 and later, and Mac OS X on Intel-based Macs.[37] thodontia. pp. 6–7. Retrieved 2013-06-03.

Other alternatives to the functionality of the “Legacy [4] Bradley, Tony. “R.I.P. BIOS: A UEFI Primer”. PC- BIOS” in the x86 world include coreboot. World. Retrieved 2014-01-27. A number of larger, more powerful servers and worksta- [5] Swaine, Michael (1997-04-01). “Gary Kildall and Col- tions use a platform-independent Open Firmware (IEEE- legial Entrepreneurship”. Dr. Dobb’s Journal. Retrieved 1275) based on the Forth programming language; it is 2006-11-20. included with Sun’s SPARC computers, IBM’s RS/6000 line, and other PowerPC systems such as the CHRP [6] Killian, A. Joseph “Joe” (2001). “Gary Kildall’s CP/M: motherboards, along with the x86-based OLPC XO-1. Some early CP/M history - 1976-1977”. Thomas “Todd” Later x86-based personal computer operating systems, Fischer, IMSAI. Retrieved 2013-06-03. like Windows NT, use their own, native drivers; this makes it much easier to extend support to new hardware. [7] Fraley, Bob; Spicer, Dag (2007-01-26). “Oral His- tory of Joseph Killian, Interviewed by: Bob Fraley, Edited by: Dag Spicer, Recorded: January 26, 2007, Mountain View, California, CHM Reference number: 7.11 See also X3879.2007,”. Computer History Museum. Retrieved 2013-06-03. • e820 [8] “HP BIOS Configuration Utility”. Hewlett-Packard. • Extended System Configuration Data 2013. Retrieved 2015-01-12. • Double boot [9] See Intel® 64 and IA-32 Architectures Software Devel- oper’s Manual, volume 3, section 9.1.2 • Plug and play [10] page 5-27 IBM Personal Computer Hardware Reference • Ralf Brown’s Interrupt List Library Technical Reference, 1984, publication number 6361459 • System Management BIOS [11] “IBM 5162 PC XT286 TechRef 68X2537 Technical Ref- • VESA BIOS Extensions erence manual” (PDF). August 1986. p. 35 (System BIOS A-5). Retrieved 2014-12-11. • XDK Debug BIOS [12] How StuffWorks: What BIOS Does. 7.12 Notes [13] BIOS Boot Specification (Version 1.01, 11 January 1996) [14] Mueller, Scott (2001-06-08). “Processor Update Feature [1] The signature at offset +0x1FE in boot sectors is 0x55 | Microprocessor Types and Specifications”. InformIT. 0xAA, that is 0x55 at offset +0x1FE and 0xAA at off- Retrieved 2014-04-15. set +0x1FF. Since little-endian representation must be as- sumed in the context of IBM PC compatible machines, [15] “Linux* Processor Microcode Data File”. Download Cen- this can be written as 16-bit word 0xAA55 in programs for ter. Downloadcenter.intel.com. 2009-09-23. Retrieved x86 processors (note the swapped order), whereas it would 2014-04-15. 46 CHAPTER 7. BIOS

[16] Scott Mueller, Upgrading and repairing PCs 15th edition, [36] “Windows and GPT FAQ”. microsoft.com. Microsoft. Que Publishing, 2003 ISBN 0-7897-2974-1, pages 109- Retrieved 6 December 2014. 110 [37] “Extensible Firmware Interface (EFI) and Uniﬁed EFI [17] “How SLP and SLIC Works”. guytechie.com. 2010-02- (UEFI)". Intel. Retrieved 6 December 2014. 25. Retrieved 2015-02-03.

[18] “Create and add an OEM ACPI SLIC table module to a congatec BIOS” (PDF). congatec.com. 2011-06-16. Re- 7.14 Further reading trieved 2015-02-03. • IBM Personal Computer Technical Reference (Re- [19] Whitson Gordon. “A Beginner’s Introduction to Over- vised ed.). IBM Corporation. March 1983. clocking Your Intel Processor”. Lifehacker. Gawker Me- dia. Retrieved 6 December 2014. • IBM Personal Computer AT Technical Reference. [20] Smart Computing Article - What Is The BIOS? - Com- IBM Personal Computer Hardware Reference Li- puting Basics July 1994 • Vol.5 Issue 7 brary. 0, 1, 2 (Revised ed.). IBM Corpora- tion. March 1986 [1984-03]. 1502494, 6139362, [21] Torres, Gabriel (24 November 2004). “Introduction and 6183310, 6183312, 6183355, 6280070, 6280099. Lithium Battery”. Replacing the Motherboard Battery. hardwaresecrets.com. Retrieved June 20, 2013. • Phoenix Technologies, Ltd. (1989) [1987]. System BIOS for IBM PC/XT/AT Computers and Compati- [22] "Decoding RAM & ROM.” Smart Computing. June 1997. bles — The Complete Guide to ROM-Based System Volume 8, Issue 6. Software. Phoenix Technical Reference Series (1st [23] "Upgrading Your Flash BIOS For Plug And Play.” Smart ed.). Addison Wesley Publishing Company, Inc. Computing. March 1996. Volume 7, Issue 3. ISBN 0-201-51806-6. [24] "Time To Check BIOS.” Smart Computing. April 1999. • Phoenix Technologies, Ltd. (1989) [1987]. CBIOS Volume 7, Issue 4. for IBM PS/2 Computers and Compatibles — The [25] SplashTop’s Instant-On Linux Desktop | Geek.com Complete Guide to ROM-Based System Software for DOS. Phoenix Technical Reference Series (1st ed.). [26] Posted by Alex Watson, possibly repost from original con- Addison Wesley Publishing Company, Inc. ISBN tent on custompc.com [unclear]. “The life and times of 0-201-51804-X. the modern motherboard”. 2007-11-27. Retrieved 2 February 2013. • Phoenix Technologies, Ltd. (1989) [1987]. ABIOS for IBM PS/2 Computers and Compatibles — The [27] David Hilber, Jr. (August 2009). “Considerations for Complete Guide to ROM-Based System Software for Designing an Embedded Intel Architecture System with System Memory Down ®". Intel. Retrieved 2 February OS/2. Phoenix Technical Reference Series (1st ed.). 2013. Addison Wesley Publishing Company, Inc. ISBN 0- 201-51805-8. [28] New BIOS Virus Withstands HDD Wipes, March 27, 2009. Marcus Yam. Tom’s Hardware US • BIOS Disassembly Ninjutsu Uncovered, 1st edition (freely available book, PDF) [29] Sacco, Anibal; Alfredo Ortéga. “Persistent BIOS Infec- tion”. Exploiting Stuff. Retrieved 2010-02-06. [30] Fisher, Dennis. “Researchers unveil persistent BIOS at- 7.15 External links tack methods”. Threat Post. Archived from the original on 30 January 2010. Retrieved 2010-02-06. • List of BIOS options [31] Giuliani, Marco. “Mebromi: the first BIOS rootkit in the • How BIOS Works wild”. blog. Retrieved 2011-09-19. • [32] “360"BMW"". blog. Retrieved 2011-09- Persistent BIOS Infection - Phrack #66 19. • Preventing BIOS Failures Using Intel Boot Block [33] Yuan, Liang. “Trojan.Mebromi”. Threat Response. Re- Flash Memory (December 1998) trieved 2011-09-19. • BIOS Boot Specification 1.01 (January 1996) [34] “How did 60 Minutes get cameras into a spy agency?". • CBS News. Retrieved 2014-04-15. Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory (February 1995) [35] Spencer Ackerman in Washington (2013-12-16). “NSA goes on 60 Minutes: the definitive facts behind CBS’s flawed report | World news”. theguardian.com. Retrieved 2014-01-27. Chapter 8

Bootstrapping

“Bootstrap” redirects here. For a UI web design tool himself over the Cumberland river or a barn yard fence called “Bootstrap”, see Bootstrap (front-end framework). by the straps of his boots.”[4] In 1860 it appeared in For other uses, see Bootstrapping (disambiguation). a comment on metaphysical philosophy: “The attempt of the mind to analyze itself [is] an effort analogous to one who would lift himself by his own bootstraps.”[5] In general parlance, bootstrapping usually refers to the starting of a self-sustaining process that is supposed to Bootstrap as a metaphor, meaning to better oneself by one’s own unaided efforts, was in use in 1922.[6] This proceed without external input. In computer technology the term (usually shortened to booting) usually refers to metaphor spawned additional metaphors for a series of self-sustaining processes that proceed without external the process of loading the basic software into the memory [7] of a computer after power-on or general reset, especially help. the operating system which will then take care of loading The term is sometimes attributed to a story in Rudolf other software as needed. Erich Raspe's The Surprising Adventures of Baron Mun- The term appears to have originated in the early 19th cen- chausen, but in that story Baron Munchausen pulls him- tury United States (particularly in the phrase “pull oneself self (and his horse) out of a swamp by his hair (specifi- over a fence by one’s bootstraps”), to mean an absurdly cally, his pigtail), not by his bootstraps – and no explicit impossible action, an adynaton.[1][2][3] reference to bootstraps has been found elsewhere in the various versions of the Munchausen tales.[4]

8.1 Etymology 8.2 Applications

8.2.1 Computing

Software loading and execution

Main article: Booting

Booting is the process of starting a computer, specifically in regards to starting its software. The process involves a chain of stages, in which at each stage a smaller simpler program loads and then executes the larger more complicated program of the next stage. It is in this sense that the computer “pulls itself up by its bootstraps”, i.e. it improves itself by its own efforts. Booting is a chain A pair of boots with one bootstrap visible of events that starts with execution of hardware-based Tall boots may have a tab, loop or handle at the top procedures and may then hand-off to firmware and soft- known as a bootstrap, allowing one to use fingers or a ware which is loaded into main memory. Booting often boot hook tool to help pulling the boots on. The saying involves processes such as performing self-tests, loading “to pull oneself up by one’s bootstraps”[3] was already configuration settings, loading a BIOS, resident monitors, in use during the 19th century as an example of an im- a hypervisor, an operating system, or utility software. possible task. The idiom dates at least to 1834, when it The computer term bootstrap began as a metaphor in the appeared in the Workingman’s Advocate: “It is conjec- 1950s. In computers, pressing a bootstrap button caused tured that Mr. Murphee will now be enabled to hand a hardwired program to read a bootstrap program from

47 48 CHAPTER 8. BOOTSTRAPPING

an input unit. The computer would then execute the boot- Compilers strap program, which caused it to read more program instructions. It became a self-sustaining process that pro- Main article: Bootstrapping (compilers) ceeded without external help from manually entered instructions. As a computing term, bootstrap has been used [8] The development of compilers for new programming lan- since at least 1953. guages ﬁrst developed in an existing language but then rewritten in the new language and compiled by itself, is another example of the bootstrapping notion. Using an existing language to bootstrap a new language is one way to solve the "chicken or the egg" causality dilemma. Software development Installers

Bootstrapping can also refer to the development of suc- Main article: Installation (computer programs) cessively more complex, faster programming environ- ments. The simplest environment will be, perhaps, a very basic text editor (e.g., ed) and an assembler program. Us- During the installation of computer programs it is some- ing these tools, one can write a more complex text editor, times necessary to update the installer or package man- and a simple compiler for a higher-level language and so ager itself. The common pattern for this is to use a small on, until one can have a graphical IDE and an extremely executable bootstrapper file (e.g. setup.exe) which up- high-level programming language. dates the installer and starts the real installation after the update. Sometimes the bootstrapper also installs other Historically, bootstrapping also refers to an early tech- prerequisites for the software during the bootstrapping nique for computer program development on new hard- process. ware. The technique described in this paragraph has been replaced by the use of a cross compiler executed by a pre-existing computer. Bootstrapping in program devel- Overlay networks opment began during the 1950s when each program was constructed on paper in decimal code or in binary code, Main article: Bootstrapping node bit by bit (1s and 0s), because there was no high-level computer language, no compiler, no assembler, and no A bootstrapping node, also known as a rendezvous host,[9] linker. A tiny assembler program was hand-coded for a is a node in an overlay network that provides initial con- new computer (for example the IBM 650) which configuration information to newly joining nodes so that they verted a few instructions into binary or decimal code: may successfully join the overlay network.[10][11] A1. This simple assembler program was then rewritten in its just-defined assembly language but with extensions that would enable the use of some additional mnemon- Discrete event simulation ics for more complex operation codes. The enhanced assembler’s source program was then assembled by its pre- Main article: Discrete event simulation decessor’s executable (A1) into binary or decimal code to give A2, and the cycle repeated (now with those en- A type of computer simulation called discrete event sim- hancements available), until the entire instruction set was ulation represents the operation of a system as a chrono- coded, branch addresses were automatically calculated, logical sequence of events. A technique called bootstrap- and other conveniences (such as conditional assembly, ping the simulation model is used, which bootstraps initial macros, optimisations, etc.) established. This was how data points using a pseudorandom number generator to the early assembly program SOAP (Symbolic Optimal schedule an initial set of pending events, which schedule Assembly Program) was developed. Compilers, linkers, additional events, and with time, the distribution of event loaders, and utilities were then coded in assembly lan- times approaches its steady state—the bootstrapping be- guage, further continuing the bootstrapping process of havior is overwhelmed by steady-state behavior. developing complex software systems by using simpler software. The term was also championed by Doug Engelbart to re- Artificial intelligence and machine learning fer to his belief that organizations could better evolve by improving the process they use for improvement (thus ob- Main articles: Bootstrap aggregating and Recursive self taining a compounding effect over time). His SRI team improvement that developed the NLS hypertext system applied this strategy by using the tool they had developed to improve Bootstrapping is a technique used to iteratively improve the tool. a classifier's performance. Seed AI is a hypothesized 8.2. APPLICATIONS 49

type of artificial intelligence capable of recursive self- • Bootstrapping in finance refers to the method to cre- improvement. Having improved itself, it would become ate the spot rate curve better at improving itself, potentially leading to an expo- • Operation Bootstrap (Operación Manos a la Obra) nential increase in intelligence. No such AI is known to refers to the ambitious projects that industrialized exist, but it remains an active field of research. Puerto Rico in the mid-20th century Seed AI is a significant part of some theories about the technological singularity: proponents believe that the development of seed AI will rapidly yield ever-smarter in- 8.2.5 Biology telligence (via bootstrapping) and thus a new era. Richard Dawkins in his book River Out of Eden[16] used the computer bootstrapping concept to explain how bio- 8.2.2 Research logical cells differentiate: “Different cells receive different combinations of chemicals, which switch on different Main article: Information retrieval combinations of genes, and some genes work to switch other genes on or off. And so the bootstrapping contin- Bootstrapping is a database searching technique. One ues, until we have the full repertoire of different kinds of may perform an inexact search (using keywords, for in- cells.” stance) and retrieve numerous “hits”, some of which will be on-target. When the researcher looks at a relevant doc- Phylogenetics ument that comes through in the mix, subject headings will be located within the document. The researcher can Bootstrapping analysis gives a way to judge the strength then execute a new search using authorized subject head- of support for clades on phylogenetic trees. A number is ings that will yield more focused, pinpointed results. written by a node, which reflects the percentage of bootstrap trees which also resolve the clade at the endpoints [17] 8.2.3 Statistics of that branch.

Main articles: Bootstrapping (statistics) and 8.2.6 Law Bootstrapping populations Main article: Bootstrapping (law) Bootstrapping is a resampling technique used to obtain estimates of summary statistics. Bootstrapping is a rule preventing the admission of hearsay evidence in conspiracy cases. 8.2.4 Business 8.2.7 Linguistics Bootstrapping in business means starting a business without external help or capital. Such startups fund the devel- Main article: Bootstrapping (linguistics) opment of their company through internal cash ﬂow and are cautious with their expenses.[12] Generally at the start of a venture, a small amount of money will be set aside Bootstrapping is a theory of language acquisition. for the bootstrap process.[13] Bootstrapping can also be [14] a supplement for econometric models. Bootstrapping 8.2.8 Physics was also expanded upon in the book Bootstrap Business, by Richard Christiansen. Main article: Bootstrap model

• Startups can grow by reinvesting profits in its own Bootstrapping is using very general consistency criteria growth if bootstrapping costs are low and return on to determine the form of a quantum theory from some investment is high. This financing approach allows assumptions on the spectrum of particles. owners to maintain control of their business, enables them to focus on customers instead of investors, and forces them to spend with discipline. [15] 8.2.9 Electronics • Leveraged buyouts, or highly leveraged or “bootstrap” transactions, occur when an investor acquires Main article: Bootstrapping (electronics) a controlling interest in a company’s equity and where a significant percentage of the purchase price Bootstrapping is a form of positive feedback in analog is financed through leverage, i.e., borrowing circuit design. 50 CHAPTER 8. BOOTSTRAPPING

8.2.10 Electric power grid public ﬁgure. It is legitimate for these stories to be given coverage across all media platforms. What distinguishes Main article: Black start a bootstrap from a real story is the contrived and orga- nized manner in which the bootstrap appears to come out An electric power grid is almost never brought down in- of nowhere. A bootstrap commonly claims to be tapping tentionally. Generators and power stations are started and a hitherto unrecognized phenomenon within society. shut down as necessary. A typical power station requires As self-levitating by pulling on one’s bootstraps is phys- power for start up prior to being able to generate power. ically impossible, this is often used by the bootstrappers This power is obtained from the grid, so if the entire grid themselves to deny the possibility that the bootstrap cam- is down these stations cannot be started. paign is indeed concocted and artiﬁcial. They assert that Therefore to get a grid started, there must be at least a it has arisen via a groundswell of public opinion. Media small number of power stations that can start entirely on campaigns that are openly admitted as concocted (e.g. a their own. A black start is the process of restoring a power public service campaign titled “Let’s Clean Up Our City”) station to operation without relying on external power. In are usually ignored by other media organizations for rea- the absence of grid power, one or more black starts are sons related to competition. On the other hand the true used to bootstrap the grid. bootstrap welcomes the participation of other media organizations, indeed encourages it, as this participation gains the bootstrap notoriety and, most importantly, le- 8.2.11 Cellular networks gitimacy.

Main articles: Bootstrapping Server Function and Generic Bootstrapping Architecture 8.3 See also

A Bootstrapping Server Function (BSF) is an intermedi- • Bootstrap paradox ary element in cellular networks which provides application independent functions for mutual authentication of • Conceptual metaphor user equipment and servers unknown to each other and • for 'bootstrapping' the exchange of secret session keys af- Horatio Alger myth terwards. The term 'bootstrapping' is related to building • Münchhausen trilemma a security relation with a previously unknown device first and to allow installing security elements (keys) in the de- • Positive feedback vice and the BSF afterwards. • Robert A. Heinlein's short story "By His Bootstraps" 8.2.12 Media • The Bootstrap Alliance, an institute founded by Douglas Engelbart A media bootstrap is the process whereby a story or meme is deliberately (but artificially) produced by self and peer- referential journalism, originally within a tight circle of 8.4 References media content originators, often commencing with stories written within the same media organization. This story is [1] World Wide Words: Boot, Michael Quinion then expanded into a general media “accepted wisdom” with the aim of having it accepted as self-evident “com- [2] “bootstraps--speculation/questions” (Mailing list). 2005- mon knowledge” by the reading, listening and viewing 08-28. publics. The key feature of a media bootstrap is that as little hard, verifiable, external evidence as possible is used [3] “figurative 'bootstraps’" (Mailing list). 2005-08-11. to support the story, preference being given to the citation [4] Jan Freeman, Bootstraps and Baron Munchausen, (often unattributed) of other media stories, i.e. “journal- Boston.com, January 27, 2009 ists interviewing journalists”. Because the campaign is usually originated and at least [5] Jan Freeman, The unkindliest cut, Boston.com, January 25, 2009 initially concocted internally by a media organization with a particular agenda in mind, within a closed loop of [6] Ulysses cited in the Oxford English Dictionary reportage and opinionation, the campaign is said to have “pulled itself up by its own bootstraps”. [7] Phrase Finder

A bootstrap campaign should be distinguished from a [8] Buchholz, Werner (1953). “The System Design of the genuine news story of genuine interest, such as a natural IBM Type 701 Computer”. Proceedings of the I.R.E. 41 disaster that kills thousands, or the death of a respected (10): 1273. 8.5. EXTERNAL LINKS 51

[9] Francis, Paul (2000-04-02). “Yoid: Extending the Inter- net Multicast Architecture”. www.aciri.org. Retrieved 2008-12-24.

[10] Traversat et al. (2006-06-20). “US Patent 7,065,579”. Retrieved 2008-12-23.

[11] Saxena et al. (2003). “Admission Control in Peer-to-Peer: Design and Performance Evaluation”. In ACM Work- shop on Security of Ad Hoc and Sensor Networks (SASN) 2003. Retrieved 2008-12-24.

[12] The Art of the Bootstrap, Venture Beat

[13] Bootstrap

[14] J. Scott Armstrong (2001). “Judgmental Bootstrapping: Inferring Experts= Rules for Forecasting”. Principles of Forecasting: A Handbook for Researchers and Practition- ers (Kluwer Academic Publishers).

[15] Bootstrapping in Entrepreneurship

[16] Richard Dawkins, River Out of Eden, pages 23-25, 1995 (paper) ISBN 0-465-06990-8

[17] Bradley Efron, Elizabeth Halloran, and Susan Holmes (1996). “Bootstrap conﬁdence levels for phylogenetic trees”. PNAS 93 (23). Retrieved 11 June 2013.

8.5 External links

• Pull straps for boots • Dictionary.com entries for Bootstrap

• Freedictionary.com entries for Bootstrap • A video talk by Douglas Engelbart on Bootstrapping on YouTube • Engelbart Institute on Bootstrapping Strategies

• Bootstrap sampling distributions for radiocarbon dating Chapter 9

Firmware

Before integrated circuits, other ﬁrmware devices included a discrete semiconductor diode matrix. The Apollo guidance computer had ﬁrmware consisting of a specially manufactured core memory plane, called "core rope memory", where data were stored by physically threading wires through (1) or around (0) the core storing each data bit.[3]

9.1 Origin of the term

Ascher Opler coined the term “firmware” in a 1967 Datamation article.[4] Originally, it meant the contents of a writable control store (a small specialized high speed A typical firmware-controlled device: a television remote control. memory), containing microcode that defined and imple- Consumer products like this have been using firmware since the mented the computer’s instruction set, and that could be 1970s. reloaded to specialize or modify the instructions that the central processing unit (CPU) could execute. As origi- In electronic systems and computing, firmware is “the nally used, firmware contrasted with hardware (the CPU combination of a hardware device, e.g. an integrated cir- itself) and software (normal instructions executing on a cuit, and computer instructions and data that reside as CPU). It was not composed of CPU machine instruc- read only software on that device”. As a result, firmware tions, but of lower-level microcode involved in the im- usually cannot be modified during normal operation of plementation of machine instructions. It existed on the the device.[1] Typical examples of devices containing boundary between hardware and software; thus the name firmware are embedded systems (such as traffic lights, “firmware”. consumer appliances, and digital watches), computers, Still later, popular usage extended the word “firmware” computer peripherals, mobile phones, and digital cam- to denote anything ROM-resident, including processor eras. The firmware contained in these devices provides machine-instructions for BIOS, bootstrap loaders, or spe- the control program for the device. cialized applications. Firmware is held in non-volatile memory devices such Until the mid-1990s, updating firmware typically in- as ROM, EPROM, or flash memory. Changing the volved replacing a storage medium containing firmware, firmware of a device may rarely or never be done during usually a socketed ROM integrated circuit. Flash mem- its economic lifetime; some firmware memory devices are ory allows firmware to be updated without physically re- permanently installed and cannot be changed after manu- moving an integrated circuit from the system. An er- facture. Common reasons for updating firmware include ror during the update process may make the device non- fixing bugs or adding features to the device. This may re- functional, or “bricked”. quire ROM integrated circuits to be physically replaced, or flash memory to be reprogrammed through a special procedure.[2] Firmware such as the ROM BIOS of a personal computer may contain only elementary basic func- 9.2 Personal computers tions of a device and may only provide services to higher- level software. Firmware such as the program of an em- In some respects, the various firmware components are bedded system may be the only program that will run on as important as the operating system in a working com- the system and provide all of its functions. puter. However, unlike most modern operating systems,

52 9.5. EXAMPLES 53

readings. Local dealers can update most vehicle ﬁrmware.

9.5 Examples

Examples of ﬁrmware include:

• In consumer products: ROM BIOS firmware on a Baby AT motherboard • Timing and control systems for washing machines firmware rarely has a well-evolved automatic mechanism • Controlling sound and video attributes, as well of updating itself to fix any functionality issues detected as the channel list, in modern TVs after shipping the unit. • EPROM chips used in the Eventide H-3000 The BIOS may be “manually” updated by a user, using series of digital music processors a small utility program. In contrast, firmware in storage • devices (harddisks, DVD drives, flash storage) rarely gets In computers: updated, even when flash (rather than ROM) storage is • The BIOS found in IBM-compatible personal used for the firmware; there are no standardized mecha- computers nisms for detecting or updating firmware versions. • The (U)EFI-compliant firmware used on Most computer peripherals are themselves special- Itanium systems, Intel-based computers from purpose computers. Devices such as printers, scanners, Apple, and many Intel desktop computer cameras, USB drives, have firmware stored internally. motherboards Some devices may permit field replacement of firmware. • Open Firmware, used in SPARC-based com- Some low-cost peripherals no longer contain non-volatile puters from Sun Microsystems and Oracle memory for firmware, and instead rely on the host system Corporation, PowerPC-based computers from to transfer the device control program from a disk file or Apple, and computers from Genesi [5] CD. • ARCS, used in computers from Silicon Graph- ics • Kickstart, used in the Amiga line of computers 9.3 Consumer products (POST, hardware init + Plug and Play auto- configuration of peripherals, kernel, etc.) As of 2010 most portable music players support firmware • RTAS (Run-Time Abstraction Services), used upgrades. Some companies use firmware updates to add in computers from IBM new playable file formats (codecs); iriver added Vorbis • playback support this way, for instance. Other features The Common Firmware Environment (CFE) that may change with firmware updates include the GUI • In routers and firewalls: or even the battery life. Most mobile phones have a Firmware Over The Air firmware upgrade capability for • LibreWRT – a 100% free software router dis- much the same reasons; some may even be upgraded to tribution based on the Linux-libre kernel enhance reception or sound quality, illustrating the fact • IPFire – an open-source firewall/router distri- that firmware is used at more than one level in complex bution based on the Linux kernel products (in a CPU-like microcontroller versus in a digital • fli4l – an open-source firewall/router distribu- signal processor, in this particular case). tion based on the Linux kernel • OpenWrt – an open-source firewall/router dis- 9.4 Automobiles tribution based on the Linux kernel • m0n0wall – an embedded firewall distribution of FreeBSD Since 1996 most automobiles have employed an on- board computer and various sensors to detect mechan- • In NAS systems: ical problems. As of 2010 modern vehicles also em- • ploy computer-controlled ABS systems and computer- NAS4Free – an open-source NAS operating operated Transmission Control Units (TCU). The driver system based on FreeBSD 9.1 can also get in-dash information while driving in this • Openfiler – a open-source NAS operating sys- manner, such as real-time fuel-economy and tire-pressure tem based on the Linux kernel 54 CHAPTER 9. FIRMWARE

9.6 Flashing 9.7.1 HDD ﬁrmware hacks

[6] Flashing involves the overwriting of existing firmware The Moscow-based Kaspersky Lab discovered that a or data on EEPROM modules present in an electronic group of developers it refers to as the "Equation Group" device with new data.[6] This can be done to upgrade a [7] has developed hard disk drive firmware modifications for device or to change the provider of a service associated various drive models, containing a trojan horse that allows with the function of the device, such as changing from one data to be stored on the drive in locations that will not mobile phone service provider to another or installing a be erased even if the drive is formatted or wiped.[11] Al- new operating system. If firmware is upgradable, it is of- though the Kaspersky Lab report did not explicitly claim ten done via a program from the provider, and will often that this group is part of the United States National Secu- allow the old firmware to be saved before upgrading so rity Agency (NSA), evidence obtained from the code of it can be reverted to if the process fails, or if the newer various Equation Group software suggests that they are version performs worse. part of the NSA.[12][13] Researchers from the Kaspersky Lab categorized the undertakings by Equation Group as the most advanced 9.7 Firmware hacking hacking operation ever uncovered, also documenting around 500 infections caused by the Equation Group in Sometimes third parties create an unofficial new or mod- at least 42 countries. ified (“aftermarket”) version of firmware to provide new features or to unlock hidden functionality. Examples include:

• Rockbox for digital audio players.

• CHDK[8] and Magic Lantern[8] for Canon digital 9.8 Security risks cameras.

• Nikon Hacker project for Nikon EXPEED DSLRs. Mark Shuttleworth, founder of the Ubuntu Linux distribution, has described proprietary firmware as a security • LibreWRT project for Ben Nanonote, Buffalo risk,[14] saying that “firmware on your device is the NSA's WZR-HP-G300NH and other computers with min- best friend” and calling firmware “a trojan horse of monu- imal resources. [9] mental proportions”. He has pointed out that low-quality, nonfree firmware is a major threat to system security:[14] • Many third-party firmware projects for wireless “Your biggest mistake is to assume that the NSA is the routers, including: only institution abusing this position of trust – in fact, it’s • OpenWrt, and its derivatives such as DD- reasonable to assume that all firmware is a cesspool of WRT.[8] insecurity, courtesy of incompetence of the highest degree from manufacturers, and competence of the highest • RouterTech – for ADSL modem/routers based degree from a very wide range of such agencies”. on the Texas Instruments AR7 chipset (with the Pspboot or Adam2 bootloader). As a solution to this problem, he has called for declarative firmware. Declarative firmware would describe “hard- • Firmware that allows DVD drives to be region-free. ware linkage and dependencies” and “should not include executable code".[14] • SamyGO, modified firmware for Samsung Custom firmware hacks have also focused on injecting televisions.[10] malware into devices such as smartphones or USB de- • Many homebrew projects for gaming consoles. vices. One such smartphone injection was demonstrated [15][16] These often unlock general-purpose computing on the Symbian OS at MalCon, a hacker conven- functionality in previously limited devices (e.g., run- tion. A USB device firmware hack called BadUSB was [17] ning Doom on iPods). presented at Black Hat USA 2014 conference, demon- strating how a USB flash drive microcontroller can be reprogrammed to spoof various other device types in order Most firmware hacks are free software. to take control of a computer, exfiltrate data, or spy on the These hacks usually take advantage of the firmware up- user.[18][19] Other security researchers have worked fur- date facility on many devices to install or run themselves. ther on how to exploit the principles behind BadUSB,[20] Some, however, must resort to exploits in order to run, releasing at the same time the source code of hacking because the manufacturer has attempted to lock the hard- tools that can be used to modify the behavior of USB flash ware to stop it from running unlicensed code. drives.[21] 9.11. EXTERNAL LINKS 55

9.9 See also [16] “Hacker plants back door in Symbian firmware”. H- online.com. 2010-12-08. Archived from the original on • ROM image 21 May 2013. Retrieved 2013-06-14. • UEFI [17] “Why the Security of USB Is Fundamentally Broken”. Wired.com. 2014-07-31. Retrieved 2014-08-04. • Coreboot [18] “BadUSB - On Accessories that Turn Evil”. Black- • Microcode Hat.com. Retrieved 2014-08-06. • Binary blob [19] Karsten Nohl; Sascha Krißler; Jakob Lell (2014-08-07). “BadUSB – On accessories that turn evil” (PDF). sr- • Bootloader labs.de. Retrieved 2014-08-23. • Aftermarket firmware category [20] “BadUSB Malware Released - Infect millions of USB Drives”. The Hacking Post - Latest hacking News & Se- curity Updates. Retrieved 7 October 2014. 9.10 References [21] “The Unpatchable Malware That Infects USBs Is Now on the Loose”. WIRED. Retrieved 7 October 2014. [1] “Glossary of Computer System Software Development Terminology (8/95)". fda.gov. FDA. November 25, 2014. Retrieved March 1, 2015. 9.11 External links [2] “What is firmware?". incepator.pinzaru.ro. Retrieved 2013-06-14. • BadUSB - On Accessories that Turn Evil on YouTube, by Karsten Nohl and Jakob Lell [3] Dag Spicer (August 12, 2000). “One Giant Leap: The Apollo Guidance Computer”. Dr. Dobbs. Retrieved Au- • Phison 2251-03 (2303) Custom Firmware & Exist- gust 24, 2012. ing Firmware Patches (BadUSB)

[4] Opler, Ascher (January 1967). “Fourth-Generation Soft- • Hard disk hacking (includes an analysis of feasible ware”. Datamation 13 (1): 22–24. security exploits through firmware modifications, in [5] Corbet, Jonathan; Rubini, Alessandro; Kroah-Hartman, eight parts) Greg (2005). Linux Device Drivers. O'Reilly Media. p. • 405. ISBN 0596005903. Snake on a keyboard (firmware modifications, in seven parts) [6] “Flashing Firmware”. Tech-Faq.com. Retrieved July 8, 2011.

[7] “HTC Developer Center”. HTC. Archived from the original on April 26, 2011. Retrieved July 8, 2011.

[8] “Custom Firmware Rocks!". 2009-08-05. Retrieved 2009-08-13.

[9] http://librewrt.org/index.php?title=Hardware_Support. Missing or empty |title= (help)

[10] “SamyGO: replacing television ﬁrmware”. LWN.net. 2009-11-14. Retrieved 2009-12-11.

[11] “Equation Group: The Crown Creator of Cyber- Espionage”. Kaspersky Lab. February 16, 2015.

[12] Dan Goodin (February 2015). “How “omnipotent” hack- ers tied to NSA hid for 14 years—and were found at last”. Ars Technica.

[13] “Breaking: Kaspersky Exposes NSA’s Worldwide, Back- door Hacking of Virtually All Hard-Drive Firmware”. Daily Kos. February 17, 2015.

[14] Shuttleworth, Mark (March 17, 2014). “ACPI, ﬁrmware and your security”.

[15] “We will be back soon!". Malcon.org. Retrieved 2013- 06-14. Chapter 10

Uniﬁed Extensible Firmware Interface

Input/Output System (BIOS) firmware interface, originally present in all IBM PC-compatible personal computers.[2][3] In practice, most UEFI firmware images provide legacy support for BIOS services. UEFI can support remote diagnostics and repair of computers, even without another operating system.[4] Intel developed the original EFI (Extensible Firmware Interface) specification. Some of the EFI’s practices and data formats mirror those from Microsoft Windows.[5][6] In 2005, UEFI deprecated EFI 1.10 (the final release of EFI). The Unified EFI Forum manages the UEFI specification.

10.1 History

The original motivation for EFI came during early development of the first Intel–HP Itanium systems in the mid-1990s. BIOS limitations (such as 16-bit processor mode, 1 MB addressable space and PC AT hardware) UEFI Logo were unacceptable for the larger server platforms Itanium was targeting.[7] The effort to address these concerns began in 1998 and was initially called Intel Boot Initiative;[8] it was later renamed to EFI.[9][10] Operating system In July 2005, Intel ceased development of the EFI specification at version 1.10, and contributed it to the Unified EFI Forum, which has evolved the specification as the Unified Extensible Firmware Interface (UEFI). The orig- Extensible Firmware Interface inal EFI specification remains owned by Intel, which exclusively provides licenses for EFI-based products, but the UEFI specification is owned by the Forum.[7][11]

Firmware Version 2.1 of the UEFI (Unified Extensible Firmware In- terface) specification was released on 7 January 2007. It added cryptography, network authentication and the User Hardware Interface Architecture (Human Interface Infrastructure in UEFI). The current UEFI specification, version 2.4, Extensible Firmware Interface’s position in the software stack. was approved in July 2013.

The Unified Extensible Firmware Interface (UEFI, pronounced as an initialism U-E-F-I or like “unify” with- 10.2 Advantages out the n[lower-alpha 1]) is a specification that defines a software interface between an operating system and plat- The interface defined by the EFI specification includes form firmware. UEFI is meant to replace the Basic data tables that contain platform information, and boot

56 10.3. COMPATIBILITY 57

Operating system UEFI operating system boot loader or kernel. After the loader Boot services system transitions from “Boot Services” to “Runtime Ser- are terminated; operation handed over to vices”, the operating system kernel takes over. At this operating system loader point, the kernel can change processor modes if it de- Boot code sires, but this bars usage of the runtime services (unless Boot from ordered list of [19]:sections 2.3.2 and 2.3.4 EFI operating system the kernel switches back again). As Application loaders is executed of version 3.15, Linux kernel supports booting of 64-bit kernels on 32-bit UEFI ﬁrmware implementations run- Drivers and applications ning on x86-64 CPUs, with UEFI handover support from are loaded iteratively Driver a UEFI boot loader as the requirement.[20] UEFI han-

Standard firmware dover protocol deduplicates the UEFI initialization code Legend platform initialization between the kernel and UEFI boot loaders, leaving the EFI binaries initialization to be performed only by the Linux kernel’s Boot manager UEFI boot stub.[21][22] Value add implementation API-specified Upon encountering an error 10.3.2 Disk device compatibility Interaction between the EFI boot manager and EFI drivers See also: GPT § Operating systems support and Protective MBR and runtime services that are available to the OS loader and OS. UEFI firmware provides several technical advan- In addition to the standard PC disk partition scheme, tages over a traditional BIOS system:[12] which uses a master boot record (MBR), UEFI works with a new partitioning scheme: GUID Partition Table • Ability to boot from large disks (over 2 TB) with a (GPT). GPT is free from many of the limitations of MBR. GUID Partition Table (GPT)[13][lower-alpha 2] In particular, the MBR limits on the number and size of disk partitions (up to 4 primary partitions per disk, up to • CPU-independent architecture[lower-alpha 2] 2 TB (2 × 240 bytes) per disk) are relaxed.[23] GPT allows 70 • CPU-independent drivers[lower-alpha 2] for a maximum disk and partition size of 8 ZB (8 × 2 bytes).[23][24] • Flexible pre-OS environment, including network ca- The UEFI specification explicitly requires support for pability FAT32 for EFI System partitions (ESPs), and FAT16 or • Modular design FAT12 for removable media;[19]:section 12.3 specific implementations may support other file systems.

10.3 Compatibility Linux

10.3.1 Processor compatibility See also: EFI System partition and Linux

As of version 2.4, processor bindings exist for Ita- Support for GPT in Linux is enabled by turning on the op- nium, x86, x86-64, ARM (AArch32) and ARM64 [14] tion CONFIG_EFI_PARTITION (EFI GUID Partition (AArch64). Only little-endian processors can be [25] [15] Support) during kernel configuration. This option al- supported. lows Linux to recognize and use GPT disks after the sys- A normal PC BIOS is limited to a 16-bit processor mode tem firmware passes control over the system to Linux. and 1 MB of addressable space due to the design be- For reverse compatibility, Linux can use GPT disks in ing based on the IBM 5150, which used the 16-bit Intel [7][16] BIOS-based systems for both data storage and booting, 8088. In comparison, the processor mode in a UEFI as both GRUB 2 and Linux are GPT-aware. Such a environment can be either 32-bit (x86-32, AArch32) [26] [7][17] setup is usually referred to as BIOS-GPT. As GPT in- or 64-bit (x86-64, Itanium, and AArch64). 64-bit corporates the protective MBR, a BIOS-based computer UEFI firmware implementations understand long mode, can boot from a GPT disk using GPT-aware boot loader which allows applications in the pre-boot execution envi- stored in the protective MBR’s bootstrap code area.[24] ronment to have direct access to all of the memory using [18] In case of GRUB, such a configuration requires a BIOS 64-bit addressing. Boot partition for GRUB to embed its second-stage code UEFI requires the firmware and operating system loader due to absence of the post-MBR gap in GPT partitioned (or kernel) to be size-matched; for example, a 64-bit disks (which is taken over by the GPT’s Primary Header UEFI firmware implementation can only load a 64-bit and Primary Partition Table). Commonly 1 MiB in size, 58 CHAPTER 10. UNIFIED EXTENSIBLE FIRMWARE INTERFACE

this partition’s Globally Unique Identifier in GPT scheme UEFI applications. Variable namespaces are iden- is 21686148-6449-6E6F-744E-656564454649 and it is tified by GUIDs, and variables are key/value pairs. used by GRUB only in BIOS-GPT setups. From the For example, variables can be used to keep crash GRUB’s perspective, no such partition type exists in case messages in NVRAM after a crash for the operating of MBR partitioning. This partition is not required if the system to retrieve after a reboot.[33] system is UEFI based, as there is no such embedding of the second-stage code in that case.[13][24][26] Time services UEFI provides device-independent time UEFI systems can access GPT disks and directly boot services. Time services include support for time- from them, simplifying things and allowing UEFI boot zone and daylight saving fields, which allow the methods for Linux. Booting Linux from GPT disks hardware real-time clock to be set to local time on UEFI systems involves creation of an EFI System or UTC.[34] On machines using a PC-AT real-time partition (ESP), which contains UEFI applications such clock, the clock still has to be set to local time for as bootloaders, operating system kernels, and utility compatibility with BIOS-based Windows.[6] software.[27][28][29] Such a setup is usually referred to as UEFI-GPT, while ESP is recommended to be at least 512 MiB in size and formatted with a FAT32 filesystem for maximum compatibility.[24][26][30] 10.4.2 Applications For backwards compatibility, most of the UEFI implementations also support booting from MBR-partitioned Independently of loading an operating system, UEFI has disks, through the Compatibility Support Module (CSM) the ability to run standalone UEFI applications, which can which provides legacy BIOS compatibility.[31] In that be developed and installed independently of the system case, booting Linux on UEFI systems is the same as on manufacturer. UEFI applications reside as files on the legacy BIOS-based systems. ESP and can be started directly by the firmware’s boot manager, or by other UEFI applications. One class of the UEFI applications are the operating system loaders, Microsoft Windows such as rEFInd, Gummiboot, and Windows Boot Man- ager; they start a specific operating system and optionally The 64-bit versions of Microsoft Windows Vista[32] and provide a user interface for the selection of another UEFI later, 32-bit versions of Windows 8, and the Itanium ver- application to run. Utilities like the UEFI shell are also sions of Windows XP and Server 2003 can boot from UEFI applications. disks with a partition size larger than 2 TB.

10.4.3 Protocols 10.4 Features EFI defines protocols as a set of software interfaces used 10.4.1 Services for communication between two binary modules. All EFI drivers must provide services to others via protocols. EFI defines two types of services: boot services and runtime services. Boot services are only available while the firmware owns the platform (before the ExitBootServices 10.4.4 Device drivers call). Boot services include text and graphical consoles on various devices, and bus, block and file services. Run- In addition to standard architecture-specific device time services are still accessible while the operating sys- drivers, the EFI specification provides for a processor- tem is running; they include services such as date, time independent device driver environment, called EFI byte and NVRAM access. code or EBC. System firmware is required by the UEFI In addition, the Graphics Output Protocol (GOP) provides specification to carry an interpreter for any EBC im- limited runtime services support; see also Graphics fea- ages that reside in or are loaded into the environment. tures section below. The operating system is permitted to In that sense, EBC is similar to Open Firmware, the directly write to the framebuffer provided by GOP dur- hardware-independent firmware used in PowerPC-based ing runtime mode. However, the ability to change video Apple Macintosh and Sun Microsystems SPARC com- modes is lost after transitioning to runtime services mode puters, among others. until the OS graphics driver is loaded. Some architecture-specific (non-EBC) EFI device driver types can have interfaces for use from the operating sys- Variable services UEFI variables provide a way to store tem. This allows the OS to rely on EFI for basic graph- data, in particular non-volatile data, that is shared ics and network functions until OS specific drivers are between platform firmware and operating systems or loaded. 10.4. FEATURES 59

10.4.5 Graphics features USB flash drives. This automated detection relies on a standardized file path to the operating system The EFI specification defined a UGA (Universal Graphic loader, with the path depending on the computer Adapter) protocol as a way to support device-independent architecture. Format of the file path is defined as graphics. UEFI did not include UGA and replaced it with /BOOT/BOOT.EFI; GOP (Graphics Output Protocol), with the explicit goal for example, on an x86-64 computer the path is of removing VGA hardware dependencies. The two are /efi/BOOT/BOOTX64.EFI.[19] [35] similar. Booting UEFI systems from GPT-partitioned disks is UEFI 2.1 defined a “Human Interface Infrastructure” commonly called UEFI-GPT booting. Additionally, it is (HII) to manage user input, localized strings, fonts, and common for an UEFI implementation to include a user forms (in the HTML sense). These enable original equip- interface to the boot manager, allowing the user to manu- ment manufacturers (OEMs) or independent BIOS ven- ally select the desired operating system (or system utility) dors (IBVs) to design graphical interfaces for pre-boot from the list of available boot options and load it. configuration; UEFI itself does not define a user interface. CSM booting Most early UEFI firmware implementations were console-based, but as early as 2007 some implementa- For backwards compatibility, most of the UEFI firmware [36] tions featured a graphical user interface. implementations on PC-class machines also support booting in legacy BIOS mode from MBR-partitioned disks, through the Compatibility Support Module (CSM) 10.4.6 EFI System partition which provides legacy BIOS compatibility. In that scenario, booting is performed in the same way as on legacy Main article: EFI System partition BIOS-based systems, by ignoring the partition table and relying on the content of a boot sector.[31] EFI System partition, often abbreviated to ESP, is a data BIOS booting from MBR-partitioned disks is commonly storage device partition that is used in computers adher- called BIOS-MBR, regardless of it being performed on ing to the UEFI specification. Accessed by the UEFI UEFI or legacy BIOS-based systems. As a side note, firmware when a computer is powered up, it stores UEFI booting legacy BIOS-based systems from GPT disks is applications and the files these applications need to run, also possible, and it is commonly called BIOS-GPT. including operating system kernels. Supported partition table schemes include MBR and GPT, as well as El Torito Despite the fact MBR partition tables are required to be [19] volumes on optical disks.[19]:section 2.6.2 For the use on fully supported within the UEFI specification, some ESPs, UEFI defines a specific version of the FAT file sys- UEFI firmwares immediately switch to the BIOS-based tem, which encompasses FAT32 file systems on ESPs, CSM booting depending on the type of boot disk’s par- and FAT16 and FAT12 on removable media.[19]:section 12.3 tition table, thus preventing UEFI booting to be per- The ESP provides space for a boot sector as part of the formed from EFI System partitions on MBR-partitioned [31] BIOS backward compatibility.[31] disks. Such a scheme is commonly called UEFI-MBR.

Network booting 10.4.7 Booting UEFI specification includes support for booting over UEFI booting network through the Preboot eXecution Environment (PXE). Underlying network protocols include Internet Unlike BIOS, UEFI does not rely on a boot sector, defin- Protocol (IPv4 and IPv6), User Datagram Protocol ing instead a boot manager as part of the UEFI specifica- (UDP), Dynamic Host Configuration Protocol (DHCP) tion. When a computer is powered on, the boot manager and Trivial File Transfer Protocol (TFTP).[19][37] checks the boot configuration and, based on its settings, loads and executes the specified operating system loader Also included is support for boot images remotely stored or operating system kernel. The boot configuration is a on storage area networks (SANs), with Internet Small set of global-scope variables stored in NVRAM, includ- Computer System Interface (iSCSI) and Fibre Channel ing the boot variables that indicate the paths to operating over Ethernet (FCoE) as supported protocols for access- [19][38][39] system loaders or kernels, which as a component class ing the SANs. of UEFI applications are stored as files on the firmware- accessible EFI System partition (ESP). Secure boot Operating system loaders can also be automatically detected by an UEFI implementation, what en- See also: Secure boot criticism ables easy booting from removable devices such as 60 CHAPTER 10. UNIFIED EXTENSIBLE FIRMWARE INTERFACE

The UEFI 2.2 specification adds a protocol known as se- version of the shell needs to be made available as cure boot, which can secure the boot process by prevent- /SHELLX64.EFI. ing the loading of drivers or OS loaders that are not signed Some other systems have an already embedded UEFI with an acceptable digital signature. When secure boot shell which can be launched by appropriate key press is enabled, it is initially placed in “setup” mode, which combinations.[50][51] For other systems, the solution allows a public key known as the “Platform key” (PK) is either creating an appropriate USB flash drive or to be written to the firmware. Once the key is written, adding manually (bcfg) a boot option associated with the secure boot enters “User” mode, where only drivers and compiled version of shell.[46][50][52][53] loaders signed with the platform key can be loaded by the firmware. Additional “Key Exchange Keys” (KEK) can be added to a database stored in memory to allow other 10.4.10 Extensions certificates to be used, but they must still have a connection to the private portion of the Platform key.[40] Secure Extensions to EFI can be loaded from virtually any non- boot can also be placed in “Custom” mode, where addi- volatile storage device attached to the computer. For ex- tional public keys can be added to the system that do not ample, an original equipment manufacturer (OEM) can match the private key.[41] distribute systems with an EFI partition on the hard drive, which would add additional functions to the standard EFI Secure boot is supported by Windows 8, Windows Server firmware stored on the motherboard’s ROM. 2012, FreeBSD, and a number of Linux distributions including Fedora, OpenSuse, and Ubuntu.[42] 10.5 Implementation and adoption 10.4.8 Compatibility Support Module 10.5.1 Intel EFI The Compatibility Support Module (CSM) is a component of the UEFI firmware that provides legacy BIOS compat- Intel’s implementation of EFI is the Intel Platform Inno- ibility by emulating a BIOS environment, allowing legacy vation Framework, codenamed “Tiano.” Tiano runs on operating systems and some option ROMs that do not Intel’s XScale, Itanium and IA-32 processors, and is pro- support UEFI to still be used.[43] prietary software, although a portion of the code has been CSM also provides required legacy System Management released under the BSD license or Eclipse Public License Mode (SMM) functionality, called CompatibilitySmm, as (EPL) as TianoCore. TianoCore can be used as a payload [54] an addition to features provided by the UEFI SMM. This for coreboot. is optional, and highly chipset and platform specific. An Phoenix Technologies' implementations of UEFI in- example of such a legacy SMM functionality is providing clude its SecureCore and SecureCore Tiano products.[55] USB legacy support for keyboard and mouse, by emulat- American Megatrends offers its own UEFI firmware im- ing their classic PS/2 counterparts.[43] plementation known as Aptio,[56] while Insyde Software offers InsydeH2O, its own implementation of Tiano.[57] 10.4.9 UEFI shell 10.5.2 Platforms using EFI/UEFI UEFI provides a shell environment, which can be used to execute other UEFI applications, including UEFI boot Intel's first Itanium workstations and servers, released in loaders.[29] Apart from that, commands available in the 2000, implemented EFI 1.02. UEFI shell can be used for obtaining various other in- Hewlett-Packard's first Itanium 2 systems, released in formation about the system or the firmware, including 2002, implemented EFI 1.10; they were able to boot getting the memory map (memmap), modifying boot Windows, Linux, FreeBSD and HP-UX; OpenVMS manager variables (bcfg), running partitioning programs added UEFI capability in June, 2003. (diskpart), loading UEFI drivers, and editing text files (edit).[44][45][46] In January 2006, Apple Inc. shipped its first Intel-based Macintosh computers. These systems used EFI instead Source code for a UEFI shell can be downloaded from of Open Firmware, which had been used on its previous the Intel's TianoCore UDK2010 / EDK2 SourceForge [58] [47] PowerPC-based systems. On 5 April 2006, Apple first project. Shell v2 works best in UEFI 2.3+ systems and released Boot Camp, which produces a Windows drivers is recommended over the shell v1 in those systems. Shell [44][48][49] disk and a non-destructive partitioning tool to allow the v1 should work in all UEFI systems. installation of Windows XP or Vista without requiring a Methods used for launching UEFI shell depend on the reinstallation of Mac OS X. A firmware update was also manufacturer and model of the system motherboard. released that added BIOS compatibility to its EFI imple- Some of them already provide a direct option in mentation. Subsequent Macintosh models shipped with firmware setup for launching, e.g. compiled x86-64 the newer firmware.[59] 10.5. IMPLEMENTATION AND ADOPTION 61

During 2005, more than one million Intel systems where short name of the machine type can be IA32, shipped with Intel’s implementation of UEFI.[60] New X64, IA64, ARM or AA64.[19] Some operating systems mobile, desktop and server products, using Intel’s imple- vendors may have their own boot loaders. They may also mentation of UEFI, started shipping in 2006. For in- change the default boot location. stance, boards that use the Intel 945 chipset series use Intel’s UEFI firmware implementation. • The Linux kernel has been able to use EFI at boot time since early 2000,[65] using the elilo EFI boot Since 2005, EFI has also been implemented on non-PC loader or, more recently, EFI versions of GRUB.[66] architectures, such as embedded systems based on XScale Grub+Linux also supports booting from a GUID cores.[60] partition table without UEFI.[13] The distribution The EDK (EFI Developer Kit) includes an NT32 target, Ubuntu added support for UEFI secure boot as of which allows EFI firmware and EFI applications to run version 12.10.[67] Further, the Linux kernel can be within a Windows application. But no direct hardware compiled with the option to run as an EFI bootloader access is allowed by EDK NT32. This means only a sub- on its own through the EFI bootstub feature. set of EFI application and drivers can be executed at the • HP-UX has used (U)EFI as its boot mechanism on EDK NT32 target. IA-64 systems since 2002. In 2008, more x86-64 systems adopted UEFI. While • many of these systems still allow booting only the HP OpenVMS has used (U)EFI on IA-64 since its BIOS-based OSes via the Compatibility Support Module initial evaluation release in December 2003, and for [68] (CSM) (thus not appearing to the user to be UEFI-based), production releases since January 2005. other systems started to allow booting UEFI-based OSes. • Apple uses EFI for its line of Intel-based Macs. Mac For example, IBM x3450 server, MSI motherboards with OS X v10.4 Tiger and Mac OS X v10.5 Leopard ClickBIOS, all HP EliteBook Notebook and Tablet PCs, implement EFI v1.10 in 32-bit mode even on newer newer HP Compaq Notebook PCs (e.g., 6730b, 6735b, 64-bit CPUs, but full support arrived with Mac OS etc.). X v10.8 Mountain Lion.[69] In 2009, IBM shipped System x machines (x3550 M2, • The Itanium versions of Windows 2000 (Advanced x3650 M2, iDataPlex dx360 M2) and BladeCenter HS22 Server Limited Edition and Datacenter Server Lim- with UEFI capability. Dell shipped PowerEdge T610, ited Edition) implemented EFI 1.10 in 2002. MS R610, R710, M610 and M710 servers with UEFI ca- Windows Server 2003 for IA-64, MS Windows pability. More commercially available systems are men- XP 64-bit Edition and Windows 2000 Advanced [61] tioned in a UEFI whitepaper. Server Limited Edition, all of which are for the In- In 2011, major vendors (such as ASRock, Asus, tel Itanium family of processors, implement EFI, Gigabyte, and MSI) launched several consumer-oriented a requirement of the platform through the DIG64 motherboards using the Intel 6-series LGA 1155 chipset specification.[70] [62] and AMD 9 Series AM3+ chipsets with UEFI. • Microsoft introduced UEFI for x86-64 Windows With the release of Windows 8 in October 2012, Mi- operating systems with Windows Server 2008 and crosoft’s certification requirements now require that com- Windows Vista Service Pack 1 so the 64-bit ver- puters include firmware that implements the UEFI spec- sions of Windows 7 are compatible with EFI. 32- ification. Furthermore, if the computer supports the bit UEFI was originally not supported since ven- "Connected Standby" feature of Windows 8 (which al- dors did not have any interest in producing native lows devices to have power management comparable to 32-bit UEFI firmware because of the mainstream smartphones, with an almost instantaneous return from status of 64-bit computing.[71] Windows 8 includes standby mode), then the firmware is not permitted to con- further optimizations for UEFI systems, including tain a Compatibility Support Module (CSM). As such, a faster startup, 32-bit support, and secure boot systems that support Connected Standby are incapable of support.[72][73] booting Legacy BIOS operating systems.[63][64] • On March 5, 2013, the FreeBSD Foundation awarded a grant to a developer seeking to add UEFI [74] 10.5.3 Operating systems support to the FreeBSD kernel and bootloader. The changes were initially stored in a discrete branch of the FreeBSD source code, but were merged An operating system that can be booted from a into the mainline source on April 4, 2014 (revision (U)EFI is called a (U)EFI-aware OS, defined by 264095); the changes include support in the installer (U)EFI specification. Here the term booted from as well.[75] a (U)EFI means directly booting the system using a (U)EFI OS loader stored on any storage device. • Oracle Solaris 11.1 and later support UEFI boot for The default location for the operating system loader is x86 systems with UEFI firmware version 2.1 or later. /BOOT/BOOT.EFI,GRUB 2 is used as the boot loader on x86.[76] 62 CHAPTER 10. UNIFIED EXTENSIBLE FIRMWARE INTERFACE

10.5.4 Use of UEFI with virtualization control the computer.[86][87] It does not solve any of the BIOS’s long-standing problems of requiring two different • HP Integrity Virtual Machines provides UEFI boot drivers—one for the firmware and one for the operating on HP Integrity Servers. It also provides a virtual- system—for most hardware.[88] ized UEFI environment for the guest UEFI-aware Open source project TianoCore also provides the UEFI OSes. interfaces.[89] TianoCore lacks the specialized drivers that • Intel hosts an Open Virtual Machine Firmware initialize chipset functions, which are instead provided by project on SourceForge.[77] Coreboot, of which TianoCore is one of many payload options. The development of Coreboot requires cooper- • VMware Fusion 3 software for Mac OS X can ation from chipset manufacturers to provide the specifi- boot Mac OS X Server virtual machines using EFI. cations needed to develop initialization drivers. VMware Workstation unofficially supports EFI, but it needs to be manually enabled by editing the vmx file, and as of 2012 Secure Boot is not yet 10.7.1 Secure boot supported.[78] ESXi/vSphere 5.0 officially support UEFI.[79] See also: Windows 8 § Reception and Hardware restric- tions § Secure boot • VirtualBox has implemented UEFI since 3.1,[80] but limited to Unix/Linux operating systems (does not work with Windows Vista x64 and Windows 7 In 2011, Microsoft announced that computers certified x64).[81][82] to run its Windows 8 operating system had to ship with secure boot enabled using a Microsoft private key. Fol- • QEMU can be used with the Open Virtual Machine lowing the announcement, the company was accused by [83] Firmware (OVMF) provided by TianoCore. critics and free software/open source advocates (includ- • The VMware ESXi version 5 hypervisor, part of ing the Free Software Foundation) of trying to use the VMware vSphere, supports virtualized EFI as an al- secure boot functionality of UEFI to hinder or outright ternative to BIOS inside a virtual machine. prevent the installation of alternative operating systems such as Linux. Microsoft denied that the secure boot re- • Second generation of the Microsoft Hyper-V virtual quirement was intended to serve as a form of lock-in, and machine supports virtualized UEFI.[84] clarified its requirements by stating that Intel-based systems certified for Windows 8 must allow secure boot to enter custom mode or be disabled, but not on systems us- 10.6 Applications development ing the ARM architecture.[41][90] Other developers raised concerns about the legal and EDK2 Application Development Kit (EADK) makes it practical issues of implementing support for secure boot possible to use standard C library functions in UEFI on Linux systems in general. Former Red Hat developer applications. EADK can be freely downloaded from Matthew Garrett noted that conditions in the GNU Gen- the Intel's TianoCore UDK2010 / EDK2 SourceForge eral Public License version 3 may prevent the use of the project. As an example, a port of the Python interpreter GRUB bootloader without a distribution’s developer dis- is made available as an UEFI application by using the closing the private key (however, the Free Software Foun- EADK.[85] dation has since clarified its position, assuring that the re- sponsibility to make keys available was held by the hard- A minimalistic “Hello world” C program written using ware manufacturer),[67] and that it would also be diffi- EADK looks similar to its usual C counterpart: cult for advanced users to build custom kernels that could #include #include #in- function with secure boot enabled without self-signing clude EFI_STATUS them.[90] Other developers suggested that signed builds EFIAPI ShellAppMain(IN UINTN Argc, IN of Linux with another key could be provided, but noted CHAR16 **Argv) { Print(L"hello, world\n”); re- that it would be difficult to persuade OEMs to ship their turn EFI_SUCCESS; } computers with the required key alongside the Microsoft key.[3] Several major Linux distributions have developed different implementations for secure boot. Matthew Gar- 10.7 Criticism rett himself developed a minimal bootloader known as shim; a pre-compiled, signed bootloader that al- Numerous digital rights activists have protested against lows the user to individually trust keys provided by UEFI. Ronald G. Minnich, a co-author of coreboot, and distributors.[91] Ubuntu 12.10 uses an older version of Cory Doctorow, a digital rights activist, have criticized shim pre-configured for use with Canonical's own key that EFI as an attempt to remove the ability of the user to truly verifies only the bootloader and allows unsigned kernels to 10.8. SEE ALSO 63

be loaded; developers believed that the practice of sign- which caused them to be bricked after installing a Linux ing only the bootloader is more feasible, since a trusted distribution in UEFI mode. While potential conflicts kernel is effective at securing only the user space, and with a kernel module designed to access system fea- not the pre-boot state for which secure boot is designed tures on Samsung laptops were initially blamed (also to add protection. That also allows users to build their prompting kernel maintainers to disable the module on own kernels and use custom kernel modules as well, with- UEFI systems as a safety measure), Matthew Garrett out the need to reconfigure the system.[67][92][93] Canoni- uncovered that the bug was actually triggered by stor- cal also maintains its own private key to sign installations ing too many UEFI variables to memory, and that the of Ubuntu pre-loaded on certified OEM computers that bug could also be triggered under Windows as well un- run the operating system, and also plans to enforce a se- der special conditions. In conclusion, he determined that cure boot requirement as well—requiring both a Canoni- the offending kernel module had caused kernel message cal key and a Microsoft key (for compatibility reasons) to dumps to be written to the firmware, thus triggering the be included in their firmware. Fedora also uses shim, but bug.[33][100][101] requires that both the kernel and its modules be signed as well.[92] It has been disputed whether the kernel and its modules 10.8 See also must be signed as well; while the UEFI specifications do not require it, Microsoft has asserted that their contrac- • Booting tual requirements do, and that it reserves the right to re- voke any certificates used to sign code that can be used • GNU GRUB to compromise the security of the system.[93] In February 2013, another Red Hat developer attempted to submit a • Master boot record (MBR) patch to the Linux kernel that would allow it to parse Mi- • crosoft’s authenticode signing using a master X.509 key GUID Partition Table (GPT) embedded in PE files signed by Microsoft. However, the • EFI System partition (ESP) proposal was criticized by Linux creator Linus Torvalds, who attacked Red Hat for supporting Microsoft’s control • BIOS Boot partition over the secure boot infrastructure.[94] • On March 26, 2013, the Spanish free software develop- Advanced Configuration and Power Interface ment group Hispalinux filed a formal complaint with the (ACPI) European Commission, contending that Microsoft’s se- • coreboot cure boot requirements on OEM systems were “obstruc- [95] tive” and anti-competitive. • Open Firmware At the Black Hat conference in August 2013, a group of • security researchers presented a series of exploits in spe- OpenBIOS cific vendor implementations of UEFI that could be used • Platform Initialization Specification to exploit secure boot.[96] Windows 10 will allow OEMs to not offer the ability to • System Management BIOS (SMBIOS) configure or disable secure boot on x86 systems.[97] • System Management Mode (SMM)

• Trusted Platform Module (TPM) 10.7.2 Firmware issues • Unified EFI Forum The increased prominence of UEFI firmware in devices has also led to a number of technical issues blamed on [98] their respective implementations. 10.9 Notes Following the release of Windows 8 in late 2012, it was discovered that certain Lenovo computer models with [1] Various pronunciations have existed for UEFI; according secure boot had firmware that was hardcoded to allow to the UK PC Pro Magazine, the following pronuncia- only executables named "Windows Boot Manager" or tions are in use: “weffy” (PC Pro), “U-E-F-I” (Microsoft), "Red Hat Enterprise Linux" to load, regardless of any “you-fee”, and “you-ef-fee”. The magazine also notes the other setting.[99] Other issues were encountered by several lack of agreement on the pronunciation.[1] Toshiba laptop models with secure boot that were missing certain certificates required for its proper operation.[98] [2] Large disk support and features such as Advanced Config- uration and Power Interface (ACPI) and System Manage- In January 2013, a bug surrounding the UEFI implement BIOS (SMBIOS) were subsequently implemented in mentation on some Samsung laptops was publicized, BIOS-based systems. 64 CHAPTER 10. UNIFIED EXTENSIBLE FIRMWARE INTERFACE

10.10 References [19] “UEFI Speciﬁcations (version 2.4 and older)" (PDF). Uni- ﬁed EFI, Inc. June 2013. Retrieved 2013-09-25.

[1] “UEFI BIOS Explained”. pcpro.co.uk. 2013-05-03. Re- [20] “Linux kernel 3.15, Section 1.3. EFI 64-bit kernels can be trieved 2014-07-05. booted from 32-bit ﬁrmware”. kernelnewbies.org. 2014- [2] Michael Kinney (1 September 2000). “Solving BIOS 06-08. Retrieved 2014-06-15. Boot Issues with EFI” (PDF). pp. 47–50. Retrieved 14 [21] “x86, eﬁ: Handover Protocol”. LWN.net. 2012-07-19. September 2010. Retrieved 2014-06-15.

[3] “MS denies secure boot will exclude Linux”. The Regis- [22] “Linux kernel documentation: Documentation/eﬁ- ter. 23 September 2011. Retrieved 24 September 2011. stub.txt”. kernel.org. 2014-02-01. Retrieved 2014-06- [4] “The 30-year-long Reign of BIOS is Over: Why UEFI 15. W... - Input Output”. H30565.www3.hp.com. Archived [23] “FAQ: Drive Partition Limits” (PDF). UEFI Forum. Re- from the original on 2013-06-26. Retrieved 2012-03-06. trieved 9 June 2010.

[5] IBM PC Real Time Clock should run in UT. [24] Roderick W. Smith (2012-07-03). “Make the most of Cl.cam.ac.uk. Retrieved on 2013-10-30. large drives with GPT and Linux”. IBM. Retrieved 2013- 09-25. [6] Matthew Garrett (Jan 19, 2012). “EFI and Linux: the future is here, and it’s awful - Matthew Garrett”. [25] “block/partitions/Kconﬁg (3.11.1)". CON- linux.conf.au 2012. Retrieved 2 April 2012. FIG_EFI_PARTITION (line #247). kernel.org. Retrieved 2013-09-25. [7] “Emulex UEFI Implementation Delivers Industry-leading Features for IBM Systems” (PDF). Emulex. Retrieved 14 [26] “GRUB”. BIOS systems. Arch Linux. Retrieved 2013-09- September 2010. 25.

[8] Extensible Firmware Interface (EFI) and Uniﬁed EFI [27] “GRUB and the boot process on UEFI-based x86 sys- (UEFI), Intel, archived from the original on 2010-01-05 tems”. redhat.com. Retrieved 2013-11-14.

[9] Wei, Dong (2006), “foreword”, Beyond BIOS, Intel Press, [28] “UEFI Booting 64-bit Redhat Enterprise Linux 6”. fp- ISBN 978-0-9743649-0-2 murphy.com. September 2010. Retrieved 2013-11-14.

[10] “1.10 Specification overview”, Extensible Firmware Inter- [29] “UEFI Bootloaders”. Arch Linux. Retrieved 2013-09-25. face, Intel [30] “Unified Extensible Firmware Interface”. EFI System Par- [11] About, Unified EFI Forum, Q: What is the relationship be- tition. Arch Linux. Retrieved 2013-09-25. tween EFI and UEFI? A: The UEFI specification is based on the EFI 1.10 specification published by Intel with cor- [31] “UEFI system booting from MBR partition table and rections and changes managed by the Unified EFI Forum. GRUB legacy”. Arch Linux Forums. June 2012. Re- Intel still holds the copyright on the EFI 1.10 specifica- trieved 2013-10-06. tion, but has contributed it to the Forum so that the Forum [32] For Microsoft Windows Vista (x64), it is possible only if can evolve it. There will be no future versions of the EFI installed from an installation DVD of Microsoft Windows specification, but customers who license it can still use it Vista (x64) with its service pack 1 or 2 integrated. under the terms of their license from Intel. The license to the Unified EFI Specification comes from the Forum, not [33] “Samsung UEFI bug: Notebook bricked from Windows”. from Intel The H. Retrieved 27 February 2013.

[12] “UEFI and Windows”. Microsoft. 15 September 2009. [34] UEFI specification, section 7.3 Retrieved 14 September 2010. [35] “Intel Embedded Graphics Drivers FAQ: BIOS and [13] “Installation”. 3.4 BIOS installation. GNU GRUB. Re- firmware”. Intel. Retrieved 2014-05-19. trieved 2013-09-25. [36] Intel shows PC booting Windows with UEFI firmware [14] UEFI Specification 2.4, section 2.3 [37] “Red Hat Enterprise Linux 6 Installation Guide”. 30.2.2. [15] UEFI specification 2.3.1, section 1.8.1. Configuring PXE boot for EFI. Red Hat. Retrieved 2013- 10-09. [16] Hardwidge, Ben (1 June 2010). “LBA explained — Solv- ing the 3TB Problem?". bit-tech. Retrieved 18 June 2010. [38] “UEFI Summit” (PDF). Advances in Pre-OS Networking in UEFI 2.4. Hewlett-Packard. July 2013. Retrieved [17] Brian Richardson (10 May 2010). “Ask a BIOS Guy: 2013-10-09. “Why UEFI"". Intel Architecture Blog. Retrieved 18 June 2010. [39] “Storage and Network Convergence Using FCoE and iSCSI” (PDF). IBM. July 2012. Retrieved 2013-10-09. [18] Gary Simpson. “UEFI Momentum — The AMD perspective” (PPTX). AMD. Archived from the original on 2014- [40] Edge, Jake. “UEFI and “secure boot"". LWN.net. Re- 01-04. Retrieved 2014-09-20. trieved 9 September 2012. 10.10. REFERENCES 65

[41] “Windows 8 Secure Boot: The Controversy Continues”. [63] Windows Hardware Certiﬁcation Requirements for PC World. Retrieved 9 September 2012. Client and Server Systems, Microsoft, 2013-1, Sys- tem.Fundamentals.Firmware.CS.UEFISecureBoot.ConnectedStandby [42] Matthew Garrett (2012-12-27). “Secure Boot distribution ... Platforms shall be UEFI Class Three (see UEFI In- support”. Mjg59.dreamwidth.org. Retrieved 2014-03-20. dustry Group, Evaluating UEFI using Commercially Available Platforms and Solutions, version 0.3, for a def- [43] “Intel® Platform Innovation Framework for EFI” (PDF). inition) with no Compatibility Support Module installed Compatibility Support Module Speciﬁcation (revision 0.97). or installable. BIOS emulation and legacy PC/AT boot Intel. 2007-09-04. Retrieved 2013-10-06. must be disabled. Check date values in: |date= (help)

[44] “Uniﬁed Extensible Firmware Interface”. UEFI Shell. [64] “Microsoft: All You Need to Know About Windows 8 on Arch Linux. Retrieved 2013-09-25. ARM”. PC Magazine. Retrieved 30 September 2013.

[45] “EFI Shells and Scripting”. Intel. Retrieved 2013-09-25. [65] Announcement of release 3.5pre1 by maintainer Brett Johnson made on 2004-02-27. [46] “UEFI Shell Speciﬁcation Version 2.0, Errata A” (PDF). Uniﬁed EFI, Inc. May 2012. Retrieved 2013-09-25. [66] EFI version of Grub, Debian GNU/Linux, retrieved 1 May 2008 [47] “TianoCore on SourceForge”. Intel. Retrieved 2013-09- 25. [67] “Ubuntu will use GRUB 2 for its Secure Boot implementation”. The H Online. Retrieved 28 October 2012. [48] “Email Archive: edk2-devel”. [edk2] Inclusion of UEFI shell in Linux distro iso. SourceForge. 2012. Retrieved [68] OpenVMS Release History, HP, retrieved 16 September 2013-09-25. 2008

[49] “TianoCore on SourceForge”. Shell FAQ. Intel. Retrieved [69] rEFIt — Windows Vista and EFI, SourceForge 2013-09-25. [70] “Extensible Firmware Interface”, Windows Server Tech- [50] “Unified Extensible Firmware Interface”. Launching Center, Microsoft UEFI Shell. Arch Linux. Retrieved 2013-09-25. [71] “Unified Extended Firmware Interface support in Win- [51] “Basic Instructions for Using EFI for Server Configura- dows Vista”. Microsoft. 26 October 2006. Retrieved tion on Intel® Server Boards and Intel® Server Systems” 12 June 2010. Microsoft determined that vendors would (PDF). Intel. 2008. Retrieved 2013-09-25. not have any interest in producing native UEFI 32-bit firmware because of the current status of mainstream 64- [52] “Unified Extensible Firmware Interface”. bcfg. Arch bit computing and platform costs. Therefore, Microsoft Linux. Retrieved 2013-09-25. originally did not to ship support for 32-bit UEFI implementations. [53] “GRUB EFI Examples”. Asus. Arch Linux. Retrieved 2013-09-25. [72] “Microsoft Touts Incredible Windows 8 Boot Times”. Re- trieved September 9, 2011. [54] “TianoCore - coreboot”. Retrieved 25 May 2012. [73] Jon Brodkin (21 September 2011). “Windows 8 secure [55] “SecureCore Tiano™". Phoenix Technologies. Retrieved boot could complicate Linux installs”. Ars Technica. Re- 14 September 2010. trieved 23 September 2011.

[56] “Aptio®: The Complete UEFI Product Solution” (PDF). [74] “FreeBSD to get UEFI support”. The H. Retrieved 7 American Megatrends, Inc. Retrieved 8 January 2011. March 2013.

[57] “InsydeH2O UEFI Framework”. Insyde Software Corp. [75] “UEFI - FreeBSD Wiki”. FreeBSD.org. Retrieved 19 Retrieved 8 January 2011. June 2014.

[58] Apple Computer. "Universal Binary Programming [76] “Oracle Solaris 11.1 — What’s New” (PDF). oracle.com. Guidelines, Second Edition: Extensible Firmware Inter- Retrieved 2013-11-04. face (EFI)" [77] Open Virtual Machine Firmware, SourceForge [59] Apple’s Transition from Open Firmware to Extensible Firmware Interface, mactech, 2007. [78] “VMWare Workstation EFI ﬁrmware | VMware Commu- nities”. Communities.vmware.com. Retrieved 2014-02- [60] “Intel® Platform Innovation Framework for UEFI 28. Overview”. Intel. Retrieved 14 September 2010. [79] “What’s New in vSphere 5.0”. Vmware.com. Retrieved [61] Evaluating UEFI using Commercially Available Platforms 2014-02-28. and Solutions (PDF), UEFI, 2011‐5 Check date values in: |date= (help) [80] 3.1 Changelog, VirtualBox

[62] Asus P67 Motherboard Preview. [81] Ticket 7702, VirtualBox 66 CHAPTER 10. UNIFIED EXTENSIBLE FIRMWARE INTERFACE

[82] “Statement by sr. software engineer at Oracle”, Forum, 10.11 Further reading VirtualBox • Zimmer, Vincent; Rothman, Michael; Hale, Robert [83] “Testing secureboot with KVM”. FedoraProject. Re- (10 May 2007). “EFI Architecture”. Dr. Dobb’s trieved 2014-02-28. Journal. UBM. Retrieved 12 October 2012.

[84] “What’s New in Hyper-V for Windows Server 2012 R2”. • De Boyne Pollard, Jonathan (11 July 2011). “The MicrosoftTechNet. Retrieved 2013-06-24. EFI boot process”. Frequently Given Answers. Re- trieved 12 October 2012. [85] “TianoCore on SourceForge”. EDK2 Application Devel- opment Kit (EADK). Intel. Retrieved 2013-09-25. • De Boyne Pollard, Jonathan (8 December 2011). “The Windows NT 6 boot process”. Frequently [86] “Interview: Ronald G Minnich”. Fosdem. 6 February Given Answers. Retrieved 12 October 2012. 2007. Retrieved 14 September 2010. • Smith, Roderick W. (2011). “A BIOS to UEFI Transformation”. Roderick W. Smith’s Web Page. [87] Doctorow, Cory (2011-12-27), The Coming War on Gen- eral Purpose Computation, retrieved 2013-09-25 Retrieved 12 October 2012. • Kothari, Rajiv (21 September 2011). “UEFI – Just [88] “coreboot (aka LinuxBIOS): The Free/Open-Source x86 How Important It Really Is”. Hardware Secrets. Re- Firmware”. YouTube. 31 October 2008. Retrieved 14 trieved 12 October 2012. September 2010. • Fisher, Doug (2011). “UEFI Today: Bootstrapping [89] “Welcome”, TianoCore, SourceForge the Continuum”. Intel Technology Journal (Intel) 15 (01). ISBN 9781934053430. Retrieved 2013-09- [90] “Is Microsoft Blocking Linux Booting on ARM Hard- 24. ware?". Compurer World UK. Retrieved 2012-03-06.

[91] “Shimming your way to Linux on Windows 8 PCs”. ZD- 10.12 External links Net. Retrieved 26 February 2013. • [92] “Ubuntu details its UEFI secure boot plans”. Linux Official website Weekly News. Retrieved 11 September 2012. • Intel-sponsored open-source EFI Framework initiative. SourceForge. [93] “No Microsoft certificate support in Linux kernel says Torvalds”. The H. Retrieved 26 February 2013. • Intel EFI/UEFI portal • [94] “Linus Torvalds: I will not change Linux to “deep-throat UEFI documents Microsoft"". Ars Technica. Retrieved 26 February 2013. • Microsoft UEFI Support and Requirements for Windows Operating Systems [95] “Exclusive: Open software group files complaint against Microsoft to EU”. Reuters. 26 March 2013. Retrieved • How Windows 8 Hybrid Shutdown / Fast Boot fea- 26 March 2013. ture works

[96] “Researchers demo exploits that bypass Windows 8 Se- • Securing the Windows 8 Boot Process cure Boot”. IT World. Retrieved 5 August 2013.

[97] “Windows 10 to make the Secure Boot alt-OS lock out a reality”. Ars Technica. Retrieved 21 March 2015.

[98] “Linux on Windows 8 PCs: Some progress, but still a nui- sance”. ZDNet. Retrieved 26 February 2013.

[99] “Lenovo UEFI Only Wants To Boot Windows, RHEL”. Phoronix. Retrieved 26 February 2013.

[100] “Linux acquitted in Samsung laptop UEFI deaths”. Bit- tech. Retrieved 26 February 2013.

[101] “Booting Linux using UEFI can brick Samsung laptops”. The H. Retrieved 26 February 2013. Chapter 11

Bus (computing)

SDRAM for memory, a hard drive for secondary storage, a graphics card and LCD display as a display system, a mouse and keyboard for interaction, and a Wi-Fi connection for networking. In both examples, computer buses of one form or another move data between all of these devices. In most traditional computer architectures, the CPU and main memory tend to be tightly coupled. A microprocessor conventionally is a single chip which has a number of electrical connections on its pins that can be used to select an “address” in the main memory and another set of pins to read and write the data stored at that location. In most cases, the CPU and memory share sig- 4 PCI Express bus card slots (from top to bottom: x4, x16, x1 and x16), compared to a 32-bit conventional PCI bus card slot (very nalling characteristics and operate in synchrony. The bus bottom) connecting the CPU and memory is one of the defining characteristics of the system, and often referred to simply In computer architecture, a bus (related to the Latin as the system bus. omnibus, meaning “for all”) is a communication sys- It is possible to allow peripherals to communicate with tem that transfers data between components inside a memory in the same fashion, attaching adaptors in the computer, or between computers. This expression covers form of expansion cards directly to the system bus. This all related hardware components (wire, optical fiber, etc.) is commonly accomplished through some sort of stan- and software, including communication protocols.[1] dardized electrical connector, several of these forming Early computer buses were parallel electrical wires with the expansion bus or local bus. However, as the per- multiple connections, but the term is now used for any formance differences between the CPU and peripherals physical arrangement that provides the same logical func- varies widely, some solution is generally needed to en- tionality as a parallel electrical bus. Modern computer sure that peripherals do not slow overall system perfor- buses can use both parallel and bit serial connections, and mance. Many CPUs feature a second set of pins simi- can be wired in either a multidrop (electrical parallel) or lar to those for communicating with memory, but able daisy chain topology, or connected by switched hubs, as to operate at very different speeds and using different in the case of USB. protocols. Others use smart controllers to place the data directly in memory, a concept known as direct memory access. Most modern systems combine both solutions, 11.1 Background and nomencla- where appropriate. As the number of potential peripherals grew, using an ture expansion card for every peripheral became increasingly untenable. This has led to the introduction of bus sys- Computer systems generally consist of three main parts, tems designed specifically to support multiple peripher- the central processing unit (CPU) to process data, main als. Common examples are the SATA ports in mod- memory to hold the data to be processed, and a variety ern computers, which allow a number of hard drives to of peripherals to communicate that data with the outside be connected without the need for a card. However, world. An early computer might use a hand-wired CPU these high-performance systems are generally too expen- of vacuum tubes, a magnetic drum for main memory, and sive to implement in low-end devices, like a mouse. This a punch tape and printer for reading and writing data. In a has led to the parallel development of a number of low- modern system we might find a multi-core CPU, DDR3 performance bus systems for these solutions, the most

67 68 CHAPTER 11. BUS (COMPUTING) common example being Universal Serial Bus. All such data in bit-serial form. The addition of extra power and examples may be referred to as peripheral buses, although control connections, differential drivers, and data con- this terminology is not universal. nections in each direction usually means that most serial In modern systems the performance difference between buses have more conductors than the minimum of one the CPU and main memory has grown so great that in- used in 1-Wire and UNI/O. As data rates increase, the creasing amounts of high-speed memory is built directly problems of timing skew, power consumption, electro- into the CPU, known as a cache. In such systems, CPUs magnetic interference and crosstalk across parallel buses communicate using high-performance buses that operate become more and more difficult to circumvent. One partial solution to this problem has been to double pump the at speeds much greater than memory, and communicate with memory using protocols similar to those used solely bus. Often, a serial bus can be operated at higher overall data rates than a parallel bus, despite having fewer elec- for peripherals in the past. These system buses are also used to communicate with most (or all) other peripher- trical connections, because a serial bus inherently has no timing skew or crosstalk. USB, FireWire, and Serial ATA als, through adaptors, which in turn talk to other peripherals and controllers. Such systems are architecturally are examples of this. Multidrop connections do not work more similar to multicomputers, communicating over a well for fast serial buses, so most modern serial buses use bus rather than a network. In these cases, expansion buses daisy-chain or hub designs. are entirely separate and no longer share any architecture Network connections such as Ethernet are not generally with their host CPU (and may in fact support many dif- regarded as buses, although the difference is largely con- ferent CPUs, as is the case with PCI). What would have ceptual rather than practical. An attribute generally used formerly been a system bus is now often known as a front- to characterize a bus is that power is provided by the bus side bus. for the connected hardware. This emphasizes the busbar Given these changes, the classical terms “system”, “ex- origins of bus architecture as supplying switched or dis- pansion” and “peripheral” no longer have the same conno- tributed power. This excludes, as buses, schemes such tations. Other common categorization systems are based as serial RS-232, parallel Centronics, IEEE 1284 inter- on the buses primary role, connecting devices internally faces and Ethernet, since these devices also needed sepa- or externally, PCI vs. SCSI for instance. However, many rate power supplies. Universal Serial Bus devices may use common modern bus systems can be used for both; SATA the bus supplied power, but often use a separate power and the associated eSATA are one example of a system source. This distinction is exemplified by a telephone sys- that would formerly be described as internal, while in tem with a connected modem, where the RJ11 connection and associated modulated signalling scheme is not certain automotive applications use the primarily external IEEE 1394 in a fashion more similar to a system bus. considered a bus, and is analogous to an Ethernet connection. A phone line connection scheme is not consid- Other examples, like InfiniBand and I²C were designed from the start to be used both internally and externally. ered to be a bus with respect to signals, but the Central Office uses buses with cross-bar switches for connections between phones. 11.1.1 Internal bus However, this distinction— that power is provided by the bus— is not the case in many avionic systems, where data The internal bus, also known as internal data bus, memory connections such as ARINC 429, ARINC 629, MIL- bus, system bus or Front-Side-Bus, connects all the inter- STD-1553B (STANAG 3838), and EFABus (STANAG nal components of a computer, such as CPU and mem- 3910) are commonly referred to as “data buses” or, some- ory, to the motherboard. Internal data buses are also re- times, “databuses”. Such avionic data buses are usually ferred to as a local bus, because they are intended to con- characterized by having several equipments or Line Re- nect to local devices. This bus is typically rather quick placeable Items/Units (LRI/LRUs) connected to a com- and is independent of the rest of the computer operations. mon, shared media. They may, as with ARINC 429, be simplex, i.e. have a single source LRI/LRU or, as with ARINC 629, MIL-STD-1553B, and STANAG 3910, be 11.1.2 External bus duplex, allow all the connected LRI/LRUs to act, at different times (half duplex), as transmitters and receivers The external bus, or expansion bus, is made up of the of data.[2] electronic pathways that connect the different external devices, such as printer etc., to the computer. 11.3 History

11.2 Implementation details Over time, several groups of people worked on various computer bus standards, including the IEEE Bus Buses can be parallel buses, which carry data words in Architecture Standards Committee (BASC), the IEEE parallel on multiple wires, or serial buses, which carry “Superbus” study group, the open microprocessor initia- 11.3. HISTORY 69

tive (OMI), the open microsystems initiative (OMI), the Later computer programs began to share memory com- “Gang of Nine” that developed EISA, etc. mon to several CPUs. Access to this memory bus had to be prioritized, as well. The simple way to prioritize interrupts or bus access was with a daisy chain. In this case 11.3.1 First generation signals will naturally flow through the bus in physical or logical order, eliminating the need for complex schedul- Early computer buses were bundles of wire that ating. tached computer memory and peripherals. Anecdotally termed the "digit trunk",[3] they were named after electrical power buses, or busbars. Almost always, there was 11.3.2 Minis and micros one bus for memory, and one or more separate buses for peripherals. These were accessed by separate instruc- Digital Equipment Corporation (DEC) further reduced tions, with completely different timings and protocols. cost for mass-produced minicomputers, and mapped pe- One of the first complications was the use of interrupts. ripherals into the memory bus, so that the input and Early computer programs performed I/O by waiting in a output devices appeared to be memory locations. This loop for the peripheral to become ready. This was a waste was implemented in the Unibus of the PDP-11 around of time for programs that had other tasks to do. Also, 1969.[5] if the program attempted to perform those other tasks, Early microcomputer bus systems were essentially a pas- it might take too long for the program to check again, sive backplane connected directly or through buffer am- resulting in loss of data. Engineers thus arranged for the plifiers to the pins of the CPU. Memory and other devices peripherals to interrupt the CPU. The interrupts had to would be added to the bus using the same address and data be prioritized, because the CPU can only execute code pins as the CPU itself used, connected in parallel. Com- for one peripheral at a time, and some devices are more munication was controlled by the CPU, which had read time-critical than others. and written data from the devices as if they are blocks High-end systems introduced the idea of channel con- of memory, using the same instructions, all timed by a trollers, which were essentially small computers dedi- central clock controlling the speed of the CPU. Still, de- cated to handling the input and output of a given bus. vices interrupted the CPU by signaling on separate CPU IBM introduced these on the IBM 709 in 1958, and they pins. For instance, a disk drive controller would signal the became a common feature of their platforms. Other high- CPU that new data was ready to be read, at which point performance vendors like Control Data Corporation im- the CPU would move the data by reading the “memory plemented similar designs. Generally, the channel con- location” that corresponded to the disk drive. Almost all trollers would do their best to run all of the bus operations early microcomputers were built in this fashion, starting internally, moving data when the CPU was known to be with the S-100 bus in the Altair 8800 computer system. busy elsewhere if possible, and only using interrupts when In some instances, most notably in the IBM PC, although necessary. This greatly reduced CPU load, and provided similar physical architecture can be employed, instruc- better overall system performance. tions to access peripherals (in and out) and memory (mov and others) have not been made uniform at all, and still generate distinct CPU signals, that could be used to im- Input and Memory plement a separate I/O bus. CPU Output These simple bus systems had a serious drawback when used for general-purpose computers. All the equipment on the bus has to talk at the same speed, as it shared a Control bus single clock. Increasing the speed of the CPU becomes harder, be- Address bus cause the speed of all the devices must increase as well. When it is not practical or economical to have all de- Data bus vices as fast as the CPU, the CPU must either enter a wait System bus state, or work at a slower clock frequency temporarily,[6] to talk to other devices in the computer. While acceptable in embedded systems, this problem was not tolerated Single system bus for long in general-purpose, user-expandable computers. To provide modularity, memory and I/O buses can be Such bus systems are also difficult to configure when con- combined into a unified system bus.[4] In this case, a sin- structed from common off-the-shelf equipment. Typi- gle mechanical and electrical system can be used to con- cally each added expansion card requires many jumpers nect together many of the system components, or in some in order to set memory addresses, I/O addresses, interrupt cases, all of them. priorities, and interrupt numbers. 70 CHAPTER 11. BUS (COMPUTING)

11.3.3 Second generation buses tend to look more like a network than the original concept of a bus, with a higher protocol overhead needed “Second generation” bus systems like NuBus addressed than early systems, while also allowing multiple devices some of these problems. They typically separated the to use the bus at once. computer into two “worlds”, the CPU and memory on Buses such as Wishbone have been developed by the open one side, and the various devices on the other. A bus source hardware movement in an attempt to further re- controller accepted data from the CPU side to be moved move legal and patent constraints from computer design. to the peripherals side, thus shifting the communications protocol burden from the CPU itself. This allowed the CPU and memory side to evolve separately from the device bus, or just “bus”. Devices on the bus could talk to 11.4 Examples of internal com- each other with no CPU intervention. This led to much puter buses better “real world” performance, but also required the cards to be much more complex. These buses also often 11.4.1 Parallel addressed speed issues by being “bigger” in terms of the size of the data path, moving from 8-bit parallel buses • ASUS Media Bus proprietary, used on some ASUS in the first generation, to 16 or 32-bit in the second, as Socket 7 motherboards well as adding software setup (now standardised as Plug- n-play) to supplant or replace the jumpers. • Computer Automated Measurement and Control However these newer systems shared one quality with (CAMAC) for instrumentation systems their earlier cousins, in that everyone on the bus had to • Extended ISA or EISA talk at the same speed. While the CPU was now isolated and could increase speed, CPUs and memory continued • Industry Standard Architecture or ISA to increase in speed much faster than the buses they talked • to. The result was that the bus speeds were now very Low Pin Count or LPC much slower than what a modern system needed, and the • MBus machines were left starved for data. A particularly common example of this problem was that video cards quickly • MicroChannel or MCA outran even the newer bus systems like PCI, and comput- • ers began to include AGP just to drive the video card. By Multibus for industrial systems 2004 AGP was outgrown again by high-end video cards • NuBus or IEEE 1196 and other peripherals and has been replaced by the new PCI Express bus. • OPTi local bus used on early Intel 80486 mother- An increasing number of external devices started employ- boards. ing their own bus systems as well. When disk drives were • Conventional PCI first introduced, they would be added to the machine with a card plugged into the bus, which is why computers have • Parallel ATA (also known as Advanced Technology so many slots on the bus. But through the 1980s and Attachment, ATA, PATA, IDE, EIDE, ATAPI, etc.) 1990s, new systems like SCSI and IDE were introduced disk/tape peripheral attachment bus to serve this need, leaving most slots in modern systems • empty. Today there are likely to be about five different S-100 bus or IEEE 696, used in the Altair and sim- buses in the typical machine, supporting various devices. ilar microcomputers • SBus or IEEE 1496 11.3.4 Third generation • SS-50 Bus • Runway bus, a proprietary front side CPU bus de- See also: Bus network veloped by Hewlett-Packard for use by its PA-RISC microprocessor family “Third generation” buses have been emerging into the • market since about 2001, including HyperTransport and GSC/HSC, a proprietary peripheral bus developed InfiniBand. They also tend to be very flexible in terms by Hewlett-Packard for use by its PA-RISC micro- of their physical connections, allowing them to be used processor family both as internal buses, as well as connecting different ma- • Precision Bus, a proprietary bus developed by chines together. This can lead to complex problems when Hewlett-Packard for use by its HP3000 computer trying to service different requests, so much of the work family on these systems concerns software design, as opposed to the hardware itself. In general, these third generation • STEbus 11.6. EXAMPLES OF INTERNAL/EXTERNAL COMPUTER BUSES 71

• STD Bus (for STD-80 [8-bit] and STD32 [16-/32- 11.5.2 Serial bit]), FAQ • Controller area network (“CAN bus”) • Unibus, a proprietary bus developed by Digital • Equipment Corporation for their PDP-11 and early eSATA VAX computers. • ExpressCard • Q-Bus, a proprietary bus developed by Digital • Fieldbus Equipment Corporation for their PDP and later • VAX computers. IEEE 1394 interface (FireWire) • • VESA Local Bus or VLB or VL-bus RS-232 • RS-485 • VMEbus, the VERSAmodule Eurocard bus • Thunderbolt • PC/104 • USB Universal Serial Bus, used for a variety of ex- • PC/104 Plus ternal devices • PC/104 Express

• PCI-104 11.6 Examples of internal/external

• PCIe-104 computer buses

• Zorro II and Zorro III, used in Amiga computer sys- • Futurebus tems • InﬁniBand • 11.4.2 Serial PCI Express External Cabling • QuickRing • 1-Wire • Scalable Coherent Interface (SCI) • HyperTransport • SCSI Small Computer System Interface, disk/tape • I²C peripheral attachment bus • • PCI Express or PCIe Serial Attached SCSI (SAS) and other serial SCSI buses • Serial ATA (SATA) • Thunderbolt • Serial Peripheral Interface Bus or SPI bus • Yapbus, a proprietary bus developed for the Pixar • UNI/O Image Computer

• SMBus 11.7 See also

11.5 Examples of external com- • Address bus puter buses • Bus contention • Control bus 11.5.1 Parallel • Front-side bus (FSB) • HIPPI HIgh Performance Parallel Interface • External Bus Interface (EBI) • IEEE-488 (also known as GPIB, General-Purpose • Harvard architecture Interface Bus, and HPIB, Hewlett-Packard Instru- mentation Bus) • Network On Chip

• PC Card, previously known as PCMCIA, much used • List of device bandwidths in laptop computers and other portables, but fading • List of network buses with the introduction of USB and built-in network and modem connections • Software bus 72 CHAPTER 11. BUS (COMPUTING)

11.8 References

[1] “bus Deﬁnition from PC Magazine Encyclopedia”. pc- mag.com. 2014-05-29. Retrieved 2014-06-21.

[2] Avionic Systems Standardisation Committee, Guide to Digital Interface Standards For Military Avionic Applica- tions, ASSC/110/6/2, Issue 2, September 2003

[3] See the early Australian CSIRAC computer

[4] Linda Null; Julia Lobur (2006). The essentials of computer organization and architecture (2nd ed.). Jones & Bartlett Learning. pp. 33,179–181. ISBN 978-0-7637- 3769-6.

[5] C. Gordon Bell; R. Cady; H. McFarland; J. O'Laughlin; R. Noonan; W. Wulf (1970). “A New Architecture for Mini- Computers—The DEC PDP-11”. Spring Joint Computer Conference: 657–675.

[6] Bray, Andrew C.; Dickens, Adrian C.; Holmes, Mark A. (1983). “28. The One Megahertz bus”. The Advanced User Guide for the BBC Microcomputer (zipped PDF). Cambridge, UK: Cambridge Microcomputer Centre. pp. 442–443. ISBN 0-946827-00-1. Retrieved 2008-03-28.

11.9 External links

• Computer hardware buses at DMOZ • Computer hardware buses and slots pinouts with brief descriptions 11.10. TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES 73

11.10 Text and image sources, contributors, and licenses

11.10.1 Text

• Computer hardware Source: http://en.wikipedia.org/wiki/Computer%20hardware?oldid=653108483 Contributors: Bearcat, Jondel, Uk- expat, Xrchz, Discospinster, Guy Harris, Wtmitchell, BD2412, RussBot, Geertivp, NawlinWiki, David Biddulph, Rwwww, BenBurch, Yamaguchi, Gilliam, Octahedron80, Nick Levine, Richard001, Kuru, Optakeover, Sohebbasharat, NickW557, DumbBOT, Ebraminio, MasterNetHead, Magioladitis, Faizhaider, Thompson.matthew, Blacksqr, Jesant13, NewEnglandYankee, KylieTastic, Treisijs, Idioma- bot, DoorsAjar, Technopat, Oxfordwang, BotKung, BloodDoll, Bentogoa, Flyer22, Chaitanya bhima, Elassint, Takeaway, Resoru, Joh- nuniq, Dthomsen8, Addbot, CanadianLinuxUser, LaaknorBot, Quercus solaris, Luckas Blade, Margin1522, Kartano, Fraggle81, Ru- binbot, Materialscientist, FrescoBot, Zilgs, Pinethicket, I dream of horses, Ftckyman, SchreyP, DixonDBot, Lotje, Jamietw, Tbhotch, EmausBot, Super48paul, Dewritech, Solarra, Ali.eblis1, Wikipelli, K6ka, FunkyCanute, Bollyjeﬀ, Bamyers99, Kilopi, Junip, Chuispas- tonBot, Senator2029, Rocketrod1960, Petrb, ClueBot NG, JetBlast, Satellizer, Widr, Soulcedric, HMSSolent, Wbm1058, DBigXray, Low- ercase sigmabot, BG19bot, MKar, Fylbecatulous, Tutelary, Mikkytopfem, HueSatLum, Sathyasri, Teammm, EuroCarGT, Jethro B, Duck- nish, Harsh 2580, Dexbot, Cerabot, TwoTwoHello, Numbermaniac, NAVEEN VENKAT, Zaldax, Frosty, Jamesx12345, Sriharsh1234, Wywin, Anna1994, Reatlas, Jvpreethi, Dave Braunschweig, Simonstone1695, Theo’s Little Bot, Rui24114, PWNGWN, Melonkelon, Sand- shark23, Babitaarora, Melody Lavender, Dannyruthe, Sarahanne.1, Margcphelan, JaconaFrere, Sam Hollingsworth, Markoolio97, Shnuce, Miljan1994, Lagoset, Wwesam01, Trackteur, Sccr4u69, JoeHebda, MonkeyWithGlasses44, Maritalaﬀairuk, Amortias, NianFav, Techy- knowsbest, LittleMissRich, Kartikmittal1995, TeaLover1996, Kyleb8181, Mediavalia, JStock89, Avinash2000, Bakosjen and Anonymous: 167

• Central processing unit Source: http://en.wikipedia.org/wiki/Central%20processing%20unit?oldid=653187976 Contributors: Chuck Smith, Brion VIBBER, Mav, The Anome, Tarquin, Alex, Wayne Hardman, Andre Engels, XJaM, JeLuF, Mudlock, SimonP, Ben-Zin, Heron, Chuq, Stevertigo, Frecklefoot, Edward, RTC, Michael Hardy, Booyabazooka, Mahjongg, Nixdorf, Liftarn, SGBailey, Wapcaplet, Ixfd64, TakuyaMurata, 7265, Minesweeper, Ahoerstemeier, Mac, Nanshu, Elano, Muriel Gottrop, Angela, Yaronf, Glenn, Nikai, Cimon Avaro, Mxn, Hashar, Emperorbma, Crusadeonilliteracy, Dmsar, Tpbradbury, Morwen, Saltine, Nv8200p, Taxman, K1Bond007, Temp- shill, ZeWrestler, Traroth, Shizhao, Bloodshedder, Ebricca, Secretlondon, Phil Boswell, Chuunen Baka, Donarreiskoffer, Robbot, Murray Langton, Fredrik, Jmabel, Modulatum, Mayooranathan, Merovingian, Sverdrup, Blainster, Jondel, Hadal, JesseW, Wikibot, Mushroom, Vikingstad, Cyrius, Iain.mcclatchie, David Gerard, Wjbeaty, Cedars, Ancheta Wis, Giftlite, Jacoplane, DavidCary, Netoholic, Popup, Tom harrison, Lupin, Aphaia, Lmno, Peruvianllama, Everyking, Curps, Guanaco, Solipsist, Fanf, VampWillow, SWAdair, Uzume, Bobblewik, Kudz75, Neilc, Chowbok, Jpkoester1, Quadell, Antandrus, Beland, Pearcej, Rdsmith4, Kesac, Epic matt, Tooki, Joyous!, Positron, Mike Rosoft, PZFUN, Freakofnurture, Archer3, Jiy, Discospinster, Solitude, Rhobite, Jpk, Pixel8, Mjpieters, Berkut, Mani1, Deelkar, Paul Au- gust, Dyl, ZeroOne, Neko-chan, BACbKA, Ht1848, CanisRufus, Zippedmartin, Diego UFCG, Lankiveil, Shanes, Art LaPella, Bookofjude, Bobo192, NetBot, Longhair, Fir0002, Smalljim, Duk, R. S. Shaw, .:Ajvol:., Johnteslade, Elipongo, Matt Britt, Cohesion, Richi, Timl, Giraffedata, Sasquatch, Pearle, Justinc, Nsaa, Espoo, Jumbuck, Alansohn, Liao, Guy Harris, Arthena, Atlant, Wouterstomp, AzaToth, Lectonar, Axl, YDZ, Snowolf, Klaser, Angelic Wraith, Velella, Wtshymanski, Rick Sidwell, Suruena, Bsadowski1, Karderio, Dan100, Richwales, Oleg Alexandrov, Feezo, Snowmanmelting, Iwan rahabok, Morkork, LOL, Nuggetboy, Matey, Robert K S, Mjbt, Pol098, Ruud Koot, MONGO, Eleassar777, Damicatz, Terence, GregorB, Wayward, Toussaint, Mandarax, Tslocum, Graham87, Cuchullain, Arunib, MC MasterChef, Kbdank71, Jclemens, Reisio, Саша Стефановић, Quale, MarSch, JHMM13, Tawker, HandyAndy, Ligulem, Ttwar- ing, GeorgeBills, Sango123, Tommy Kronkvist, RobertG, Windchaser, Nihiltres, JiFish, Who, Xenobog, LevelCheck, RexNL, Gurch, Alphachimp, SteveBaker, Synchrite, King of Hearts, CJLL Wright, Ahpook, Cactus.man, Gwernol, Tone, Elfguy, Wavelength, Texas- Android, Spacepotato, Sceptre, Adam1213, Phantomsteve, Rowan Moore, Fabartus, John Quincy Adding Machine, Anonymous editor, Noypi380, Stephenb, Shell Kinney, Rsrikanth05, Wimt, NawlinWiki, DragonHawk, Wiki alf, Malmis, Spike Wilbury, NickBush24, Jaxl, Mmccalpin, Vanished user 1029384756, Icelight, RazorICE, J128, Joelr31, Dureo, Banes, Matticus78, Misza13, Killdevil, Tony1, Jeh, Gra- ham Jones, Jeremy Visser, Mcicogni, Mike92591, Avraham, Robost, Fallout boy, Phgao, Zzuuzz, Demus Wiesbaden, Dr.alf, GraemeL, JoanneB, Shawnc, Smurrayinchester, Willtron, Spliffy, Imdaking, Garion96, Rwwww, MansonP, Finell, Soir, Arcadie, AndrewWTaylor, SmackBot, Tuoreco, Bobet, Prodego, KnowledgeOfSelf, Hydrogen Iodide, Pgk, Phaldo, Jab843, Cessator, Frymaster, Canthusus, Edono- van, Info lover, Ekilfeather, Xaosflux, Gilliam, Ohnoitsjamie, Hmains, Lg1223, Chris the speller, Persian Poet Gal, Jprg1966, Tree Biting Conspiracy, Zelphar, Dlohcierekim’s sock, Ikiroid, Whispering, Bowmanjj, ToobMug, Manta7, Harpastum, Jeffreyarcand, Can't sleep, clown will eat me, Mitsuhirato, Frap, Ashawley, Vulcanstar6, OrphanBot, Nixeagle, JonHarder, Yidisheryid, TheKMan, TonySt, Rip- Fire12901, Celarnor, Krich, Gohst, Emre D., Cybercobra, Nakon, AlyM, Fatal-, Slavy13, Acdx, Luigi.a.cruz, Ligulembot, Ck lostsword, Pilotguy, Qmwne235, Zac67, Dave314159, Kuru, Kipala, Edwy, CaptainVindaloo, Goodnightmush, Jcoy, Ben Moore, 16@r, Andy- pandy.UK, Aceofskies05, George The Dragon, Timmy2, Optakeover, Doczilla, Dhp1080, Ambuj.Saxena, Ryulong, LaMenta3, Phuzion, DwightKingsbury, Levineps, BranStark, Iridescent, Tophtucker, ToastyMallows, Kabu, Jacopone, Tawkerbot2, Scriptfan, YourUserHere, Adamwisky, Bob121, Electron20, Fvasconcellos, Olie93, JForget, FleetCommand, Unixguy, CmdrObot, Anakata, Sax Russell, Neelix, Sahrin, Akaka, Danrok, Steel, Gogo Dodo, ST47, MysticMetal, Chasingsol, Tawkerbot4, DumbBOT, Ameliorate!, Sp, Kozuch, Mtpaley, Omicronpersei8, Davo123, Gimmetrow, S raghu20, Quantyz, Epbr123, Kubanczyk, Kelpherder, Qwyrxian, Newton2, Marek69, TheJosh, James086, Renamed user 1752, Doyley, Java13690, Leon7, Druiloor, Big Bird, Sam42, Dawnseeker2000, Escarbot, Ilion2, Mentifisto, Hmrox, AntiVandalBot, Luna Santin, Widefox, Seaphoto, CZmarlin, Bigtimepeace, Sir Hat, SEG88, Farosdaughter, Malcolm, MECU, DarthShrine, Res2216firestar, Savemeto2, JAnDbot, Tigga, Fiskars007, Barek, MER-C, Instinct, Arch dude, Wiz126, Sitethief, Little- OldMe, Acroterion, Xoneca, Akuyume, Bongwarrior, VoABot II, AuburnPilot, JamesBWatson, Mbarbier, Think outside the box, Omiks3, CTF83!, Dulciana, LaughingMan42, Upholder, ArchStanton69, Marmoulak, 28421u2232nfenfcenc, Allstarecho, P.B. Pilhet, Vssun, Der- Hexer, GermanX, Gwern, MartinBot, Dinshoupang, Frak, R'n'B, CommonsDelinker, Buletproofbrit, Thesalus, LittleOldMe old, Lilac Soul, J.delanoy, Pharaoh of the Wizards, Trusilver, Grungerz, Hans Dunkelberg, Uncle Dick, Jesant13, MooresLaw, Eliz81, Benscripps, Hakufu Sonsaku, Mikael Häggström, R twell27, AntiSpamBot, Cpusweden, NewEnglandYankee, Shoessss, Camoxide, Littleog, KylieTas- tic, Cometstyles, Bonadea, Rjclaudio, The dragon123, Useight, Hmdz105, Meiskam, VolkovBot, ABF, Brheed Zonabp84, Gseandiyh79, Jeff G., Indubitably, RightSideNov, 132qwerty, Philip Trueman, DoorsAjar, TXiKiBoT, Oshwah, Zidonuke, Triggerhappy412, Miranda, NPrice, Nxavar, Z.E.R.O., Qxz, Someguy1221, Personline, Oxfordwang, Anna Lincoln, Mandetory, Melsaran, Priver312, Martin451, The Ice Inside, Don4of4, Headbangerbuggy, Lou.weird, Jackfork, LeaveSleaves, Monkeynoze, Sychen, Srce, Andy Dingley, Michelle192837, Haseo9999, Wasted Sapience, WJetChao, Synthebot, Enviroboy, Turgan, Nagy, Dogah, SieBot, Gmb1994, Fnagaton, Sonicology, Al- phaPyro, Santhosh.thottingal, Krawi, Smsarmad, Yintan, Keilana, Bentogoa, Breawycker, Flyer22, Tiptoety, Bobanater, Wilson44691, Paolo.dL, Oxymoron83, Bichito, Lightmouse, Techman224, Hobartimus, Ks0stm, RyanParis, Dillard421, Sean.hoyland, Mygerardro- mance, WikiLaurent, Pinkadelica, Jbray3179, WikipedianMarlith, Seanm924, Loren.wilton, Martarius, ClueBot, Ano onymis, Snigbrook, 74 CHAPTER 11. BUS (COMPUTING)

Foxj, Wikievil666, The Thing That Should Not Be, Rilak, Jan1nad, Knepflerle, Pheeror, Arakunem, Starcraft.nut, Myhellhereorunder, Yabeeno, Matt 118118, Blanchardb, Ridge Runner, Rprpr, Rockfang, Pointillist, Sensiblemayank, Hallo990, Catfish Jim and the soapdish, Excirial, Goodone121, Tomeasy, Koishii1521, Alejandrocaro35, Tyler, Jjtennisman, Ben ben ben ben ben jerry, Dekisugi, XTermina- tor2000, Netanel h, Deerstop, Aitias, Flipper344, Versus22, Lambtron, SoxBot III, Ginbot86, XLinkBot, Hotcrocodile, Fastily, Gwandoya, Stickee, Rror, Feinoha, Little Mountain 5, Rreagan007, SilvonenBot, NellieBly, Galzigler, Jd027, Torahjerus14, JinJian, Zodon, Lanky217, Dsimic, Tim1980tim, Addbot, Winstonliang6758, Pyfan, Raghavkvp, Mortense, Sdfsakjdhfuioaheif283, Manuel Trujillo Berges, Lan- don1980, Captain-tucker, LHvU, Peti1212, Turnerj, Ronhjones, Fieldday-sunday, Ironholds, D0762, Darklightning1, Scientus, Canadian- LinuxUser, MrOllie, Glane23, Matthewirwin28693, WikiDegausser, Jasper Deng, Beastathon, Brainmachine, Numbo3-bot, Bwrs, DNA to RNA, Tide rolls, Krano, Teles, Gail, Zorrobot, Jarble, Ettrig, Luckas-bot, Yobot, Mcdennis13, Fraggle81, Phatstakks, Pikachu, Archon- Magnus, Mmxx, Knockwood, KamikazeBot, Timir Saxa, AnakngAraw, Radiopathy, Deicool, AnomieBOT, Rubinbot, Jim1138, IRP, Galoubet, Piano non troppo, AdjustShift, Fahadsadah, Kingpin13, RandomAct, Flewis, Materialscientist, The High Fin Sperm Whale, Citation bot, Juhuang, X360Silent, Georgeb92, Wx4sno, Milf&cookies, GB fan, JohnFromPinckney, 04satvinderbi, Xqbot, 4I7.4I7, Cure- den, The sock that should not be, Capricorn42, 4twenty42o, Knowitall44, Jsharpminor, Blargarg, GrouchoBot, Nayvik, Solphusion, Wiz- ardist, RibotBOT, Mpgenius, Genius1789, SCΛRECROW, Luciandrei, Sicklight, Jarred.rop1, Full-hyperion, Shadowjams, Dougofborg, Cekli829, GT5162, FrescoBot, Bighead01753, LucienBOT, Rome109, X5UPR3ME STEV3x, VI, Jamesooders, Citation bot 1, Wd- fowty, Pooosihole, FMAlchemist36, HRoestBot, Edderso, A412, Coekon, Calmer Waters, Tinton5, BRUTE, RedBot, SpaceFlight89, -Peterlunde, Thestraycat57, Ravenperch, Vre ,ئاراس نوری ,Footwarrior, Lineslarge, Rzęsor, Pranayrocks23, WardMuylaert, RMartin-2 nator, Defender of torch, Momma69, Aiken drum, Bitolado, Jeffrd10, Specs112, Diannaa, Tbhotch, Reach Out to the Truth, Jesse V., Minimac, Hornlitz, 11james22, DARTH SIDIOUS 2, Onel5969, Dmytheus, TjBot, Ihateblazing, Dhiraj1984, Noommos, Lauri.pirttiaho, Instigate cjsc (Narine), Thisisafakeaccountfordeletingpages, EmausBot, Orphan Wiki, WikitanvirBot, Mynameiswa, BillyPreset, Akjar13, Racerx11, Wikipelli, Mz7, ZéroBot, John Cline, Cogiati, Daonguyen95, Ida Shaw, Fæ, Imperial Monarch, Pololei, Espin2, Fred Gandt, Stas3717, Wayne Slam, Ferry24.Milan, Arman Cagle, LordJeff, Shrikanthv, GeorgeBarnick, L Kensington, Donner60, Wikiloop, Or- ange Suede Sofa, Ipsign, Jrstern29, LikeLakers2, Erin2003, 28bot, ClueBot NG, Bionik276, TomBridle, Satellizer, Andreas.Persson, Movses-bot, Millermk, Rajayush78, Cntras, O.Koslowski, Kasirbot, Masssly, Widr, Greg.Kerr01, Ashish Gaikwad, Jorgenev, Mapolat, Adam.Amory.97, Yucel114, Hazal018, HMSSolent, Wbm1058, Nashhinton, Dogan900, Wiki13, MusikAnimal, Amp71, IraChester- field, Jonas weepel, Kinnngg, Rm1271, Dauntless28, Anchit singla, Camomen3000, Glacialfox, Klilidiplomus, MantridFreeman, Mikepa- bell, Chip123456, Fylbecatulous, BattyBot, Justincheng12345-bot, WhiteNebula, Computerwoman417, Benjaminjkim, CKsquid, YFdyh- bot, Ekonomka, Modwizcode, MadGuy7023, Gdrg22, Tow, Sniper-ass, Dexbot, KuraAbyss, Taylorclem, ZaferXYZ, Frosty, Graphium, Jamesx12345, Trollilols, Botusharov, EdwardJK, Jazzee8845, Andypandyjay, Reatlas, Greengreengreenred, Sancho .308, Thatginernonce, Mndunne, Bobobob1231, DavidLeighEllis, Edwinblack1, Comp.arch, Ugog Nizdast, Fwiki225, Riehutunut, AddWittyNameHere, Occult- Zone, JammedWords, Lopsidedtriangle, Djgolam, FlashDave, UltraFireFX, Sonyoo1, GeorgeAhad, TKer193, Monkbot, Rudyjuliyanto, MatthewBuchwalder, Jim Carter, Trax support, Sperkowsky, Keonnikpour, Vinaya.mente, QueenFan, TerryAlex, Siraj Khurshied, An- ish057, ChamithN, Darknesssnow, KOool23456, Joeseph kake, Sivaprasadmsr, ComsciStudent, Israelg99, TurkeyWriter77, Benji877, TehBacon, Lumpy247, Troll42069, Thefreeencyclopedia1231, Robolamiah, Superbug1000, Dou14208038, Territory war 3 pwner and Anonymous: 1331 • Chipset Source: http://en.wikipedia.org/wiki/Chipset?oldid=650476841 Contributors: Andre Engels, Michael Hardy, Alfio, Harvester, RickK, David Shay, Robbot, Digital infinity, Presto8, Aechols, Gracefool, Khalid hassani, Ryanaxp, Chowbok, Jonathan Grynspan, Karl- Henner, Maikel, Moxfyre, EagleOne, Discospinster, Pixel8, WegianWarrior, CanisRufus, Kyz, Mairi, Spalding, Polluks, Dungodung, Alansohn, Atlant, Alinor, Suruena, Dtcdthingy, Sciurinæ, Boothy443, Timharwoodx, Rocastelo, Robert K S, Knuckles, Alexthemans, Isnow, Alecv, Kbdank71, Reisio, Ketiltrout, Bubuka, FlaBot, Fivemack, Geimas5, M7bot, Chobot, YurikBot, Vuvar1, Ansell, Nawlin- Wiki, Ethan, Robertvan1, DeadEyeArrow, GaryKlein, Kkmurray, Wknight94, Lt-wiki-bot, Eskimbot, Agentbla, Jerome Charles Potts, Wisden17, Frap, JonHarder, HarisM, JzG, Gobonobo, Robofish, Feureau, CUTKD, Mets501, Kvng, JustinRossi, Amalas, Trentdk, Il- iank, Thijs!bot, Barticus88, Ranunculoid, AntiVandalBot, Janus657, MER-C, Geniac, Magioladitis, Twsx, Allstarecho, ClubOranje, Con- querist, BetBot, Jargon777, Cerebral0214, Y2kbug, Jesant13, Whitebox, Half-Blood Auror, D-Kuru, Adam Zivner, VolkovBot, Philip Trueman, OracleGuy01, GL1zdA, Andy Dingley, Hellcat fighter, Bojan PLOJ, Haiviet, Jakeslogan, Btotanes, SieBot, Agarfield2004, Ger- akibot, Phe-bot, Green-eyed girl, Oxymoron83, Dlrohrer2003, ClueBot, Rilak, ImperfectlyInformed, Zacharychung, Rprpr, Jusdafax, Arjayay, JimMobo, DumZiBoT, Hyins, Addbot, MrOllie, Sanchayansinha, Oldmountains, Eddau, Xalteva, Tide rolls, Lightbot, Luckas- bot, AnomieBOT, Bobi.1, Tehori, Kingpin13, Materialscientist, SvartMan, LouriePieterse, Xqbot, J G Campbell, RibotBOT, Kyng, Der Falke, Mfwitten, Arndbergmann, Jandalhandler, TobeBot, Borandi, Mattias.Campe, EmausBot, Angrytoast, Tecnova, Klelith, ClueBot NG, Martin Berka, Mudasir005, Wbm1058, Habitmelon, Bcmengel, Arcticaribou, BattyBot, BjornVanB, Sumasdad, C5st4wr6ch, Infiniti4, Ju- lianprescott2604juuly and Anonymous: 134 • Graphics processing unit Source: http://en.wikipedia.org/wiki/Graphics%20processing%20unit?oldid=653012511 Contributors: Taw, Wayne Hardman, Heron, Edward, DopefishJustin, Mahjongg, Nixdorf, Karada, Egil, Andres, Harvester, Lee Cremeans, Furrykef, Temp- shill, Wernher, Thue, Topbanana, Stormie, Optim, Robbot, Chealer, Vespristiano, Playwrite, Academic Challenger, Tobias Bergemann, Alan Liefting, Alf Boggis, Paul Pogonyshev, Everyking, Alison, Lurker, DJSupreme23, Gracefool, Rchandra, AlistairMcMillan, Ego- maniac, Khalid hassani, Gadfium, Utcursch, Pgan002, Aughtandzero, Quadell, Lockeownzj00, Beland, MFNickster, Simoneau, Trilo- bite, Imroy, Pixel8, AlexKepler, Berkut, Alistair1978, Pavel Vozenilek, Gronky, Indrian, Evice, Billlion, TOR, CanisRufus, RoyBoy, Drhex, Polluks, Matt Britt, Richi, Kjkolb, Markpapadakis, Kaf, Varuna, Murphykieran, Mc6809e, Hohum, Angelic Wraith, Velella, Suruena, Sciurinæ, Bjorke, Freyr, Marasmusine, Kelly Martin, Woohookitty, Jannex, Ae-a, Macronyx, SCEhardt, Isnow, M412k, Tou- ssaint, Kbdank71, Josh Parris, Tbird20d, Sdornan, Sango123, StuartBrady, FlaBot, Mirror Vax, Arnero, Viznut, Chobot, ShadowHntr, YurikBot, Jtbandes, Locke411, Yyy, ALoopingIcon, Virek, RicReis, Qviri, Panscient, Zephalis, Mike92591, MaxDZ8, Wknight94, Delir- ium of disorder, Arthur Rubin, D'Agosta, E Wing, Red Jay, David Biddulph, Mikkow, Nekura, Veinor, FearTec, SmackBot, Colinstu, AFBorchert, Bigbluefish, Unyoyega, Jagged 85, Renku, KVDP, Jrockley, Eskimbot, Scott Paeth, Jpvinall, Gilliam, Bluebot, TimBent- ley, GoldDragon, QTCaptain, Thumperward, Jerome Charles Potts, Octahedron80, Anabus, Tsca.bot, Can't sleep, clown will eat me, Harumphy, Frap, JonHarder, Ruw1090, Easwarno1, Theonlyedge, Cybercobra, Melter, Nakon, Trieste, HarisM, Nitro912gr, Swaaye, Salamurai, HeroTsai, Soumya92, Disavian, Wibbble, Joffeloff, Codepro, Aleenf1, Vuurmeester, Phranq, Cxk271, Sjf, Hu12, Stargam- ing, Agelu, ScottHolden, Stoakron97, Aeons, Tawkerbot2, Jafet, Braddodson, SkyWalker, Xcentaur, Zarex, Mattdj, Nczempin, Jsmaye, Jesse Viviano, Shandris, Lazulilasher, Sahrin, Pi Guy 31415, Phatom87, Danrok, JJC1138, Gogo Dodo, Scissorhands1203, Soetermans, Mr. XYZ, Tawkerbot4, Bitsmart, Thijs!bot, Wermlandsdata, Mentifisto, Eberhart, AntiVandalBot, Konman72, Gioto, SEG88, Flex Flint, Johan.Seland, Skarkkai, Serpent’s Choice, JAnDbot, MER-C, Jdevesa, Arch dude, Kremerica, RubyQ, Vidsi, AndriusG, RBBrittain, Gbrose85, Michaelothomas, Nikevich, I JethroBT, Marmoulak, David Eppstein, Crazyideas21, Frampis, El Krem, UnfriendlyFire, Tru- sader, R'n'B, J.delanoy, Pharaoh of the Wizards, ChrisfromHouston, Jesant13, Smite-Meister, Gzkn, Xbspiro, M-le-mot-dit, Urzadek, Jo7hs2, EconomistBR, Sugarbat, Spiesr, Canadianbob, Martial75, Lights, VolkovBot, MrRK, TXiKiBoT, Like.liberation, Tr-the-maniac, 11.10. TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES 75

Tandral, Cody-7, Broadbot, Haseo9999, Squalk25, AlleborgoBot, Glitchrf, SieBot, 4wajzkd02, Yulu, Garde, Djayjp, Flyer22, Nopetro, Oxymoron83, Lightmouse, Earthere, Twsl, Pinkadelica, Gillwill, WikipedianMarlith, Accessory, ClueBot, The Thing That Should Not Be, Placi1982, Rilak, Nnemo, Dpmuk, Jappalang, Hexmaster, Niceguyedc, Alexbot, Socrates2008, Technobadger, Arjayay, Jotterbot, Ark25, Muro Bot, Vapourmile, GlasGhost, Andy16666, Socks 01, Tigeron, 5900FX, GeoﬀMacartney, DumZiBoT, Rreagan007, Salam32, Frood, JeGX, Noctibus, Eleven even, Zodon, Veritysense, NonNobisSolum, Dsimic, Osarius, Addbot, Willking1979, Ronhjones, MrOllie, Download, LaaknorBot, Aunva6, Peti610botH, Fiftyquid, Jarble, Xowets, Ben Ben, Legobot, Publicly Visible, Luckas-bot, Yobot, Ptbot- gourou, Becky Sayles, GateKeeper, Sg227, 4th-otaku, AnomieBOT, Masterofwiki666, Galoubet, Materialscientist, Clark89, LilHelpa, JanEnEm, PavelSolin, Xqbot, Holden15, Erud, Victorbabkov, CoolingGibbon, P99am, Braxtonw1, J04n, Winstonliang, =Josh.Harris, Robert SkyBot, FrescoBot, IvarTJ, Umawera, Math1337, Jusses2, Vincentfpgarcia, RedBot, Akkida, Rzęsor, Hitachi-Train, Yogi m, Ale And Quail, Ravenperch, Jesse V., John Buchan, DARTH SIDIOUS 2, Onel5969, Dewritech, Dcirovic, Serketan, Cogiati, Vitkovskiy Roman, Handheldpenguin, Veikk0.ma, Romdanen, Tomy9510, Topeil, Evan-Amos, Des3dhj, ClueBot NG, Matthiaspaul, Dholcombe, Widr, Tijok, MarcusBritish, Helpful Pixie Bot, Largecrashman, Wbm1058, KLBot2, Aayush.nitb, Kangaroopower, Sqzx, MusikAnimal, Joydeep, Diculous, Alanau8605, Isenherz, Tagremover, Comatmebro, Dymatic, Stocbuster, Codename Lisa, Webclient101, Makecat-bot, Ckoerner, Nonnompow, Andrei.gheorghe, Frosty, Calinou1, OSXiOSMacFan, EdwardJK, Jmankovecky, Reatlas, Mahbubur-r-aaman, Hallowin, Eyesnore, Nigma2k, Dannyniu, CrystalCanine, Comp.arch, Papagao, Sibekoe, Jdog147123, ScotXW, UltraFireFX, Kral Petr, Mansoor-siamak, ChamithN, Newwikieditor678 and Anonymous: 463

• Random-access memory Source: http://en.wikipedia.org/wiki/Random-access%20memory?oldid=653000098 Contributors: Damian Yerrick, The Cunctator, Ansible, Brion VIBBER, Mav, Wesley, Robert Merkel, The Anome, Stephen Gilbert, JeLuF, Arvindn, Christian List, Enchanter, William Avery, Roadrunner, Ben-Zin, Maury Markowitz, Imran, Heron, OlofE, Stevertigo, Frecklefoot, Ubiquity, Norm, Ixfd64, Mcarling, Mbessey, Alfio, Pcb21, Iulianu, Mac, Darkwind, Glenn, Whkoh, Andres, Med, Corixidae, CAkira, Mulad, Crusadeonil- literacy, Frieda, Furrykef, Wernher, Traroth, Camerong, Rossumcapek, Jni, Ckape, Robbot, TomPhil, Owain, Davodd, Hadal, Wikibot, LX, Lpetrazickis, Tobias Bergemann, Giftlite, DocWatson42, Wizzy, DavidCary, Harp, Holizz, Rj, Peruvianllama, Digital infinity, Ssd, Yekrats, Mboverload, Gracefool, VampWillow, SWAdair, Bobblewik, Benjeeeboy, Gadfium, Pgan002, Slowking Man, Antandrus, Beland, Joeblakesley, Kesac, Sfoskett, Sillydragon, Urhixidur, Zondor, Trevor MacInnis, Moxfyre, Grstain, Mike Rosoft, Real NC, Brother Dysk, Discospinster, Rich Farmbrough, Rhobite, Vsmith, ArnoldReinhold, YUL89YYZ, Berkut, Alistair1978, Mani1, MarkS, ESkog, ZeroOne, Andrejj, Nmagedman, Oiketohn, CanisRufus, Shadow demon, Shanes, RoyBoy, Triona, Funkyj, Drhex, Bobo192, Smalljim, R. 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BUS (COMPUTING)

load, LaaknorBot, Glass Sword, AndersBot, Jonhjelm, Favonian, Jasper Deng, West.andrew.g, Akyoyo94, Fireaxe888, KaiKemmann, Tide LuK3, Megaman en m, Ochib, Frehley, Luckas-bot, ZX81, Yobot, Ptbotgourou, TaBOT-zerem, Snydale, II ,טבעת-זרם ,rolls, SDJ, Llakais ,Eric-Wester, AnomieBOT, Ciphers, Rubinbot, 1exec1 ,محبوب عالم ,?MusLiM HyBRiD II, Crispmuncher, THEN WHO WAS PHONE Jim1138, IRP, Bmonro, Theqwert, Kingpin13, Law, RandomAct, Flewis, Materialscientist, Bobagoncheese, Blackdogman, Pcb95, Kevin chen2003, Xqbot, Kagemaru16, Capricorn42, Doanjackson, DSisyphBot, Jsharpminor, Ommel, Ubcule, J04n, Frosted14, Wizardist, New- port Beach, SciberDoc, Papercutbiology, Mark Schierbecker, RibotBOT, The Interior, Crashdoom, Amaury, KB Alpha, Masterofabcs, GhalyBot, =Josh.Harris, Savannah Kaylee, CodeMaster123, Chaheel Riens, Alan1000, ELCleanup, Fillepa, Jimfile, ComputerWizerd, Su- per IT guy, Edgars2007, GliderMaven, FrescoBot, Scarypeep, W Nowicki, Grinters, Sagark86, Eehite, SkyHigher, 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Sw33tkill3r24, Basak327, Aslihanbilgekurt, Oddbodz, Arbraini, Anuragiscool12, Aogus, Hsn6161, Onur074, Sinohayja, HMSSolent, Wbm1058, Zim Lex, 2001:db8, Hikmet483, DBigXray, Wowkiddy- mage, Vagobot, M0rphzone, Stevethepanda, Dharmuone, CityOfSilver, Bigjackg, Hallows AG, Wiki13, Mark Arsten, Rm1271, Hllomen, Tehh bakery, Vesna Wylde, Pano38, Jayadevp13, TheLurkerMan, Vanischenu, Klilidiplomus, Bsdjkqvfkj, Seesh cabeesh, Maxxdxx, Anbu121, BattyBot, Jeremy112233, Teammm, Pratyya Ghosh, Theamazingswamp, TheCascadian, Cyberbot II, Mediran, Khazar2, Eu- roCarGT, Marsel92 22, Lakers297065, Theramcerebral, Abhikandoi2000, Will Sandberg, ZaferXYZ, Sourav255, Scottyj200, TwoT- woHello, Frosty, SFK2, Graphium, Sriharsh1234, Milesandkilometrestogo, Liamgaygay, RandomLittleHelper, Raj Singh, Craven, Faizan, Camyoung54, AKATRAZ99, Jacob neale, Daniiielc, Handsome cat, Everymorning, EvergreenFir, Probusiness, DavidLeighEllis, Danny- -Anar ,محمد عصام ,hacker1, Babitaarora, PasseVivant, My name is not dave, Jianhui67, Miner49er5635, Jackmcbarn, SDTV is beast123 cham, DPRoberts534, Joewithers89, Mikeycpud, Yaakovaryeh, Sirspray, UltraFireFX, 7Sidz, Avidee007, LukeSmithlol, Mr Bo Janglez 69, Maxlan1, BethNaught, Kzorq, Swallis11, Scrappyboy88, Cncreate, Ballistic238, NQ, Frinked.tpm, Mjiles85, Gvkmohan5, ChamithN, TAYLORGATE, Crystallizedcarbon, Ggggg1234, Rombom4, Abcdefgjit, Hongkongfoooi, Esquivalience, Brajmohan Pathak, Benji877, Butcrackman, Abu ali-shabat thawadi, AveragelyPro and Anonymous: 1475 • Read-only memory Source: http://en.wikipedia.org/wiki/Read-only%20memory?oldid=645463645 Contributors: Damian Yerrick, Derek Ross, Brion VIBBER, Stephen Gilbert, Drj, Toby Bartels, Ben-Zin, Patrick, RTC, Michael Hardy, TakuyaMurata, Pcb21, Ahoerstemeier, ,Traroth, Shantavira, Riddley, Kizor, Boffy b, Gidonb, Blainster ,דוד ,Mac, Glenn, Netsnipe, Timwi, Cjmnyc, WhisperToMe, Wernher Wikibot, Tobias Bergemann, Wizzy, DavidCary, ShaunMacPherson, Kim Bruning, Bradeos Graphon, Niteowlneils, Sdfisher, Finn-Zoltan, Gracefool, Luigi30, VampWillow, Pne, Bobblewik, TerokNor, Jpeloquin, Ojw, Chmod007, Moxfyre, Zoganes, Lovelac7, ArnoldReinhold, Xezbeth, Quistnix, ESkog, Khalid, CanisRufus, El C, Bobo192, Harald Hansen, Smalljim, .:Ajvol:., Nk, Obradovic Goran, Hooperbloob, Shadoks, Jumbuck, Jic, 119, Atlant, Craigy144, Angelic Wraith, Wtshymanski, Tony Sidaway, ThomasWinwood, Firsfron, Woohookitty, Camw, Optichan, Isnow, Bruns, Mandarax, Graham87, Tangotango, Bruce1ee, DirkvdM, FlaBot, Fresheneesz, CStyle, Chobot, Former user 6, YurikBot, Laurentius, SpuriousQ, Stephenb, Shell Kinney, Yyy, Shanel, NawlinWiki, Wiki alf, Scs, Zwobot, Allens, GrinBot, Krótki, Veinor, SmackBot, Pgk, KocjoBot, Mdd4696, Nscheffey, Brianski, Skizzik, GoneAwayNowAndRetired, JDCMAN, DMS, Mat- tythewhite, DHN-bot, KieferSkunk, Can't sleep, clown will eat me, Frap, Xmastree, Jmlk17, HarisM, Salamurai, Ugur Basak Bot, Fire emblem, Microchip08, Dicklyon, TheOtherStephan, Axipher, Beno1000, CapitalR, Blehfu, Tawkerbot2, Unionhawk, Dgw, Green caterpil- lar, DanielRigal, Neelix, Djg2006, Thijs!bot, Epbr123, Barticus88, Bezking, Qwyrxian, Daniel, N5iln, AntiVandalBot, Majorly, JAnDbot, MER-C, Geniac, ZPM, Pedro, Bongwarrior, VoABot II, AtticusX, Soulbot, JaGa, Gwern, MartinBot, R'n'B, Thugofnewbold, Darin-0, Brest, Jesant13, Tiggerjay, Kvdveer, CardinalDan, EEye, Indubitably, Darksideofarollingstone, DoorsAjar, TXiKiBoT, Hqb, GDonato, Falcon8765, Spinningspark, AlleborgoBot, Nagy, EmxBot, SieBot, AS, BotMultichill, Winchelsea, Timhowardriley, Jerryobject, Happy- sailor, Universalcosmos, Lagrange613, Frappucino, StaticGull, Anchor Link Bot, Dolphin51, ClueBot, Fyyer, The Thing That Should Not Be, Ramstwer, Boing! said Zebedee, Niceguyedc, Muhandes, Posix memalign, OekelWm, Ottawa4ever, Bathis, Joel Saks, Patrick.franklin, XLinkBot, BodhisattvaBot, WikHead, Dsimic, VanMerde, Addbot, Mortense, Fyrael, Atethnekos, Sergei, MrOllie, Favonian, Tassede- the, Tide rolls, Lightbot, Luckas-bot, Ptbotgourou, Nallimbot, KDS4444, Jim1138, Dwayne, School1015895, Kingpin13, ArthurBot, Xqbot, Nasnema, XZeroBot, Knuckx, RibotBOT, The Interior, DaleDe, Salient Edge, Ghoshs89, Thehelpfulbot, Alexf0708, Glider87, Pinethicket, HRoestBot, MastiBot, Ezhuttukari, Amar007sv, TobeBot, Lotje, Ansumang, Minimac, DARTH SIDIOUS 2, Onel5969, EmausBot, Acather96, Dewritech, Vanished user zq46pw21, Wikipelli, Jplcrd, Wayne Slam, Music Sorter, Rombomb12, Bomazi, Evan- Amos, Pana Gill, Whoop whoop pull up, ClueBot NG, Aakashgv, Sph3698, O.Koslowski, Aslihanbilgekurt, John.nuttall.jr, Wbm1058, Usman Nasir Khan, Rancher 42, Rynsaha, Rajeevs1992, Bsdjkqvfkj, Seesh cabeesh, Thomasdavies1993, Lukas²³, None but shining hours, Makecat-bot, Lugia2453, Coketales, My-2-bits, Luke Watto, MasterTriangle12, Fudgcker33, SantiLak, Happy Attack Dog, A.Minkowiski, Amortias, Gvkmohan5, Wiscipidier, Laudson, Sane007, Brajmohan Pathak, Ondrej34 and Anonymous: 308 • BIOS Source: http://en.wikipedia.org/wiki/BIOS?oldid=652046163 Contributors: Zundark, The Anome, Tarquin, Koyaanis Qatsi, Taw, Jeronimo, Andre Engels, Ted Longstaffe, Christian List, William Avery, Roadrunner, Edward, Michael Hardy, Modster, Tannin, Chinju, MichaelJanich, Ahoerstemeier, Cyan, Chrysalis, Robertkeller, Lenaic, Timwi, Dcoetzee, Dysprosia, Greenrd, WhisperToMe, Lee Cre- means, Rvalles, Jgm, Jimbreed, Fvw, Robbot, Dersonlwd, SchmuckyTheCat, Auric, Pcr, Wikibot, Cek, Iain.mcclatchie, Nagelfar, Alan Liefting, Xyzzyva, Giftlite, DavidCary, Tom harrison, Ferkelparade, Jdavidb, Chris Wood, AlistairMcMillan, Richard cocks, VampWil- low, Edcolins, Chowbok, Andycjp, Knutux, Antandrus, OverlordQ, Piotrus, Imlepid, Maximaximax, Henriquevicente, Frau Holle, Salv236, Abdull, Zondor, Trevor MacInnis, Kate, Gazpacho, Mormegil, Hinrik, Discospinster, Rich Farmbrough, Guanabot, FT2, Caesar, Vsmith, ArnoldReinhold, Berkut, Dyl, ESkog, Andrejj, Swid, Evice, CanisRufus, Zenohockey, Bletch, Kwamikagami, Deanos, Bobo192, Cmdr- jameson, Mactenchi, Matt Britt, JW1805, Cghost, Towel401, Hesperian, Officiallyover, Lysdexia, Jumbuck, Poweroid, Alansohn, Guy Harris, M7, Lord Pistachio, Cibumamo, Denniss, Wtshymanski, LFaraone, Ringbang, Ceyockey, Forderud, Peter Putzer, Kbolino, Billh- pike, OwenX, Mindmatrix, Timharwoodx, Rocastelo, Peng, Pol098, Ruud Koot, WadeSimMiser, Fred J, Srborlongan, Wikiklrsc, Blue- moose, Sega381, Palica, Cuvtixo, Magister Mathematicae, Feydey, Alll, DoubleBlue, Kwharris, RoceKiller, Antimatt, FayssalF, Titoxd, FlaBot, Mirror Vax, SchuminWeb, Flydpnkrtn, Riluve, Jrtayloriv, Antiuser, Bgwhite, Mortenoesterlundjoergensen, YurikBot, Todd Vier- ling, Logixoul, RussBot, Fabartus, Ineedbettername, Epolk, SpuriousQ, Yuhong, Akamad, Stephenb, Manop, Sikon, Gaius Cornelius, Rsrikanth05, Wimt, NawlinWiki, Aeusoes1, Długosz, Jabencarsey, CecilWard, Cybergoth, Bayerischermann, Closedmouth, Arthur Ru- bin, KGasso, GraemeL, Snaxe920, GrinBot, CIreland, NetRolller 3D, SmackBot, Verdafolio, Bobet, Gribeco, IEdML, KocjoBot, Thun- derboltz, Jedikaiti, Eskimbot, Srnec, Brianski, Ohnoitsjamie, Chris the speller, Michele.alessandrini, Bluebot, Jprg1966, Thumperward, Snori, Nbarth, DHN-bot, Darth Panda, Jimwelch, Audriusa, Can't sleep, clown will eat me, Blah2, Mitchell7man, Frap, Onorem, Burns 11.10. TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES 77

flipper, Nixeagle, Zazpot, The tooth, Luigi.a.cruz, Chopin1810, Kukini, SashatoBot, Harryboyles, Rodri316, Lakinekaki, Ocee, Rafert, Shadowlynk, Kashmiri, Minna Sora no Shita, Turanyuksel, Prasannaxd, Slakr, Yodaat, Epimorph, BranStark, Kiwi8, Asmpgmr, Rigurat, Blehfu, Tawkerbot2, Jafet, Drachenstern, CmdrObot, Caomhin, Chrumps, Coolerhead, Basawala, Harej bot, Jesse Viviano, Requestion, WeggeBot, T23c, Michael J. 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S. Shaw, Jerryseinfeld, Perceval, Diego Moya, Andrewpmk, Zippanova, Hu, Ish ishwar, DV8 2XL, Forderud, Oleg Alexandrov, Radiant, Natalya, Thryduulf, Clemmy, Turnstep, Graham87, BD2412, Syndicate, Hulagutten, ErikHaugen, Nirkus, Mirror Vax, Harmil, Krzysiu, Eldred, Jrtayloriv, Chobot, Uriah923, YurikBot, Kafziel, Esco, Conscious, Hellbus, Stephenb, Welsh, Adamrush, Kassie, Asams10, Cengelbart, Flooey, TimHesterberg, Dontaskme, That Guy, From That Show!, Eykanal, Johnmarkh, DocendoDiscimus, SmackBot, VnutZ, TheBilly, Unyoyega, Scott Paeth, Slaniel, Hmains, Bluebot, Ce1984, Thumperward, Nbarth, Chruck, LouScheffer, Adamantios, COMPFUNK2, Valenciano, Andrew Gildehaus, Bgoswami, Bige1977, Lambiam, Cody5, Archimerged, Rsimmonds01, Physis, 16@r, Smith609, Peyre, Snezzy, Phoenixrod, Glaberson, Frank Lofaro Jr., Npdoty, Cydebot, Ahawowow, Rdls01, Kozuch, Pellucid, Ebraminio, Ncjones, Thijs!bot, Seaphoto, SummerPhD, AubreyEllenShomo, Greensburger, Magioladitis, Parsecboy, Transcendence, Pixel ;-), Steven Walling, Rich257, Lenticel, Myshark, Gkklein, Mulangi, Mojodaddy, Gblandst, Tichondrius, STBotD, Philip Trueman, Altermike, Johnson487682, The Thing That Should Not Be, Wesleyneo, Anon lynx, Arjayay, XLinkBot, Galzigler, Dsimic, Addbot, Bhargavasaikumar, Bushfire Bill, Sp- Bot, 1RadicalOne, Yobot, Megatron must be stopped, AnomieBOT, Zk00006, Flewis, Synaptophysin, Jacobspaulsen, Thomas Maierhofer, FrescoBot, Iconmode, Haeinous, Gottesmm, Citation bot 1, Pinethicket, I dream of horses, Achitchcock, Linus Smithson, RjwilmsiBot, EmausBot, Frabrunelle, J.kadlubowska, ZéroBot, Dkevanko, ClueBot NG, Lgaglioti10, Matthiaspaul, Lord Roem, Lemuellio, Denemark, Widr, Boots12, MerlIwBot, Curb Chain, Wbm1058, Walk&check, Atomician, Ugncreative Usergname, ChrisGualtieri, Cynmcc, Mogism, Alt Content, ProfessorHouseCat, Andyhowlett, Bossyandpicky, Postonm, Mei lin fung, AfadsBad, Paul2520, Jamalmunshi, Mario Castelán Castro, Leslie belden, Googleguacamole and Anonymous: 179 • Firmware Source: http://en.wikipedia.org/wiki/Firmware?oldid=652758618 Contributors: Damian Yerrick, Zundark, The Anome, Tar- quin, Andre Engels, Enchanter, Hannes Hirzel, Rbrwr, Nixdorf, Mac, Smack, Dysprosia, Myshkin, Furrykef, Wernher, Robbot, Zz, Tech- tonik, Bkell, Wikibot, Engerim, Alan Liefting, David Gerard, DavidCary, Kenny sh, Antandrus, Beland, Panit, Abdull, Adashiel, Vsmith, Jojit fb, Lysdexia, Alansohn, Guy Harris, Spangineer, Brock, Wtshymanski, TahitiB, Dzordzm, SCEhardt, Isnow, Graham87, Raffaele Megabyte, NeonMerlin, Fred Bradstadt, Titoxd, FlaBot, SchuminWeb, Ayla, Fresheneesz, BMF81, King of Hearts, Chobot, Nastajus, WriterHound, YurikBot, Borgx, MMuzammils, Stephenb, Manop, Sikon, Cunado19, Jabencarsey, Code65536, Bota47, Nlu, Gregzeng, Nikkimaria, GrinBot, Perardi, NetRolller 3D, SmackBot, YellowMonkey, Redslime, F, Wlindley, Hydrogen Iodide, Gribeco, Ultramandk, Evanreyes, Brianski, Jcarroll, Dlohcierekim’s sock, Frap, Chlewbot, Steveo1544, LouScheffer, Joema, Decltype, DylanW, NickPenguin, Autopilot, Weatherman1126, AThing, Mr Stephen, UKER, Dicklyon, Bashari, Amitch, The7thmagus, CapitalR, Sph147, Tawkerbot2, Ryt, Nuclearo, Sandeep pranavam, HenkeB, SolarisBigot, Phatom87, O mores, MikeLacey, Normix, Stevag, Thijs!bot, Kubanczyk, Fourchette, Dgies, Icep, Mentifisto, Widefox, Nosbig, JAnDbot, Arch dude, Aki009, ProjectPlatinum, VoABot II, Kuyabribri, Tedickey, Some- thingWittyHere, Alex Spade, Gwern, Majesty9012, Herbythyme, Public Menace, Thaurisil, Laurusnobilis, JensRex, LordAnubisBOT, Cometstyles, STBotD, DorganBot, Ertyeryery, Aaronsingh, CardinalDan, Idioma-bot, Deor, Philip Trueman, Rocketmagnet, TyrantX, WolfgangEcker, DennyColt, LeaveSleaves, Mazarin07, Softtest123, Miko3k, Alaniaris, SieBot, WereSpielChequers, Winchelsea, Stone- jag, Steven Zhang, OKBot, Dillard421, ClueBot, Meekywiki, ChandlerMapBot, Posix memalign, SchreiberBike, Zappa711, Joel Saks, Darkicebot, S1fw, Rror, Cmr08, Jaymacdonald, Kurniasan, Dsimic, Addbot, Grandscribe, Cptnoremac, Colcolstyles, Fluffernutter, Cst17, Aclews56, ChenzwBot, 5 albert square, Tide rolls, Rainbow will, Another-anomaly, Crt, Luckas-bot, Yobot, Ptbotgourou, Fraggle81, 78 CHAPTER 11. BUS (COMPUTING)

Legobot II, Crispmuncher, MrBurns, AnomieBOT, Exp HP, Rubinbot, Jim1138, Name5555, Gacpro, Xqbot, Rijndael, The Evil IP address, GrouchoBot, RibotBOT, Universalss, Fobeteh, Erik9, SupportFTP, FrescoBot, Mohandesi, Winterst, SpaceFlight89, Jandalhandler, Siddharthsivakumar, TobeBot, SchreyP, RjwilmsiBot, Jtsandlund, Lopifalko, WikitanvirBot, Chewbaca75, Liquidmetalrob, Doomedtx, Contribute23, The contributor 4783, Chezi-Schlaff, MaGa, ChuispastonBot, VictorianMutant, Kenny Strawn, Rocketrod1960, ClueBot NG, Rajaram Sarangapani, Steve dexon, Wbm1058, BG19bot, Walk&check, Arashium, Mark Arsten, Compfreak7, Rancher 42, Winston Chuen-Shih Yang, BattyBot, Tkbx, Tagremover, Bachware, Ajv39, Marian Robinson, NoBearHere, Melonkelon, Gerardwm, Shaddycrook, Comp.arch, Monkbot, Guglastican, Tanankmaster118, MXocrossIIB, Garfield Garfield, Ggordonbyrne and Anonymous: 317 • Unified Extensible Firmware Interface Source: http://en.wikipedia.org/wiki/Unified%20Extensible%20Firmware%20Interface?oldid= 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Genhuan, RjwilmsiBot, Jlhcpa, Kreig303, EmausBot, John of Reading, RA0808, Zambi007, Cyberkagami, David Markun, Lokpest, TheChampionMan1234, Risthel, Mlorer, ClamDip, Mikhail Ryazanov, ClueBot NG, Freevanx, Jamesw2010, Matthi- aspaul, Lostick, Snotbot, Rezabot, Widr, Titodutta, BG19bot, Compfreak7, Mattwick, Dwduback, ChrisGualtieri, 2040tech, Jdratlif5942, Codename Lisa, PeteMaz, Kephir, Calinou1, MartinMichlmayr, Ashwestonr, The Herald, Gogrp89, Someone not using his real name, ScotXW, Flechaig, Monkbot, Sofia Koutsouveli, Sawsmith, JW19335762743 and Anonymous: 353 • Bus (computing) Source: http://en.wikipedia.org/wiki/Bus%20(computing)?oldid=652616543 Contributors: Uriyan, The Anome, Drj, Css, Dachshund, Shd, Aldie, Fubar Obfusco, Deb, SimonP, Maury Markowitz, Heron, Olivier, Michael Hardy, Mahjongg, Nixdorf, Egil, ArnoLagrange, Mac, Nanshu, Glenn, Nikai, Rl, GRAHAMUK, CAkira, Reddi, Magnus.de, Colin Marquardt, Tschild, Saltine, Wernher, Thue, Veghead, Jni, Chuunen Baka, Robbot, MrJones, Fredrik, Scott McNay, RedWolf, Naddy, Merovingian, Hadal, Marc Venot, David- Cary, Kenny sh, Guanaco, Ezhiki, Tom-, Ferdinand Pienaar, AlistairMcMillan, VampWillow, Uzume, Sam Hocevar, Klemen Kocjancic, Mike Rosoft, Olki, Imroy, Slady, JTN, Discospinster, Guanabot, Bert490, Xezbeth, Mjpieters, Horsten, WegianWarrior, Johannes Rohr, Limbo socrates, Violetriga, Tooto, CanisRufus, R. S. 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11.10.2 Images • File:4Mbit_EPROM_Texas_Instruments_TMS27C040_(1).jpg Source: http://upload.wikimedia.org/wikipedia/commons/3/34/ 4Mbit_EPROM_Texas_Instruments_TMS27C040_%281%29.jpg License: CC BY 2.0 Contributors: 4Mbit EPROM Texas Instruments TMS27C040 Original artist: yellowcloud from Germany • File:6600GT_GPU.jpg Source: http://upload.wikimedia.org/wikipedia/commons/4/44/6600GT_GPU.jpg License: CC-BY-SA-3.0 Con- tributors: Own work Original artist: Berkut 11.10. TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES 79

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Original artist: ? • File:Ambox_current_red.svg Source: http://upload.wikimedia.org/wikipedia/commons/9/98/Ambox_current_red.svg License: CC0 Contributors: self-made, inspired by Gnome globe current event.svg, using Information icon3.svg and Earth clip art.svg Original artist: Vipersnake151, penubag, Tkgd2007 (clock) • File:Ambox_important.svg Source: http://upload.wikimedia.org/wikipedia/commons/b/b4/Ambox_important.svg License: Public domain Contributors: Own work, based oﬀ of Image:Ambox scales.svg Original artist: Dsmurat (talk · contribs) • File:Amiga-Chip-Set1.png Source: http://upload.wikimedia.org/wikipedia/commons/a/a8/Amiga-Chip-Set1.png License: Public domain Contributors: Originally from de.wikipedia; description page is/was here. Original artist: PeterFrankfurt at de.wikipedia • File:Award_BIOS_setup_utility.png Source: http://upload.wikimedia.org/wikipedia/commons/0/05/Award_BIOS_setup_utility.png License: Public domain Contributors: Self-made, by extracting the bitmap font from the video ROM and recreating the screen character by character. Based on an actual setup screen of a computer I (User:Kephir) once had. The color palette may be a bit inaccurate, but otherwise it is probably the closest thing to a screenshot one could ever get with this kind of software. Original artist: Award Software International Inc., recreated by User:Kephir • File:Binary_Forty.PNG Source: http://upload.wikimedia.org/wikipedia/commons/2/25/Binary_Forty.PNG License: CC0 Contributors: Own work Original artist: P Astbury • File:Bios_chip-2011-04-11.jpg Source: http://upload.wikimedia.org/wikipedia/commons/f/f7/Bios_chip-2011-04-11.jpg License: CC BY-SA 3.0 Contributors: Own work Original artist: Tremaster • File:Bundesarchiv_Bild_183-1989-0406-022,_VEB_Carl_Zeiss_Jena,_1-Megabit-Chip.jpg Source: http://upload.wikimedia.org/ wikipedia/commons/e/ec/Bundesarchiv_Bild_183-1989-0406-022%2C_VEB_Carl_Zeiss_Jena%2C_1-Megabit-Chip.jpg License: CC BY-SA 3.0 de Contributors: This image was provided to Wikimedia Commons by the German Federal Archive (Deutsches Bundesarchiv) as part of a cooperation project. The German Federal Archive guarantees an authentic representation only using the originals (negative and/or positive), resp. the digitalization of the originals as provided by the Digital Image Archive. Original artist: Kasper, Jan Peter • File:Commons-logo.svg Source: http://upload.wikimedia.org/wikipedia/en/4/4a/Commons-logo.svg License: ? Contributors: ? Original artist: ? • File:Computer-aj_aj_ashton_01.svg Source: http://upload.wikimedia.org/wikipedia/commons/c/c1/Computer-aj_aj_ashton_01.svg License: CC0 Contributors: ? Original artist: ? • File:Computer_from_inside_018.jpg Source: http://upload.wikimedia.org/wikipedia/commons/a/ac/Computer_from_inside_018.jpg License: Public domain Contributors: Own work Original artist: kallerna • File:Computer_system_bus.svg Source: http://upload.wikimedia.org/wikipedia/commons/6/68/Computer_system_bus.svg License: CC BY-SA 3.0 Contributors: Own work, based on a diagram which seems to in turn be based on page 36 of The Essentials of Computer Organization and Architecture By Linda Null, Julia Lobur, http://books.google.com/books?id=f83XxoBC_8MC&pg=PA36 Original artist: W Nowicki • File:DIAMONDSTEALTH3D2000-top.JPG Source: http://upload.wikimedia.org/wikipedia/en/f/f8/ DIAMONDSTEALTH3D2000-top.JPG License: PD Contributors: ? Original artist: ? • File:Dr_Martens,_black,_old.jpg Source: http://upload.wikimedia.org/wikipedia/commons/3/39/Dr_Martens%2C_black%2C_old.jpg License: CC-BY-SA-3.0 Contributors: ? Original artist: ? • File:Dstealth32.jpg Source: http://upload.wikimedia.org/wikipedia/commons/2/22/Dstealth32.jpg License: Public domain Contributors: Own work Original artist: Swaaye at English Wikipedia • File:EBIntel_Corei5.JPG Source: http://upload.wikimedia.org/wikipedia/commons/5/52/EBIntel_Corei5.JPG License: CC BY-SA 3.0 Contributors: Own work Original artist: highwycombe (talk) • File:Early_SSA_accounting_operations.jpg Source: http://upload.wikimedia.org/wikipedia/commons/f/f7/Early_SSA_accounting_ operations.jpg License: Public domain Contributors: http://www.ssa.gov/history/acalcs.html Original artist: US Social Security Admin- istration 80 CHAPTER 11. BUS (COMPUTING)

• File:Edit-clear.svg Source: http://upload.wikimedia.org/wikipedia/en/f/f2/Edit-clear.svg License: Public domain Contributors: The Tango! Desktop Project. Original artist: The people from the Tango! project. And according to the meta-data in the file, specifically: “Andreas Nilsson, and Jakub Steiner (although minimally).” • File:Edvac.jpg Source: http://upload.wikimedia.org/wikipedia/commons/1/17/Edvac.jpg License: Public domain Contributors: Photo located at: http://ftp.arl.mil/ftp/historic-computers/ Original artist: ? • File:Efi-simple.svg Source: http://upload.wikimedia.org/wikipedia/commons/4/4e/Efi-simple.svg License: Public domain Contributors: Own work Original artist: Msikma • File:Efi_flowchart_extended.svg Source: http://upload.wikimedia.org/wikipedia/commons/f/ff/Efi_flowchart_extended.svg License: CC BY-SA 2.5 Contributors: File:Efi flowchart extended.jpg Original artist: Original file by User Msikma on en.wikipedia, SVG version by me • File:Eprom.jpg Source: http://upload.wikimedia.org/wikipedia/commons/3/39/EPROM_Intel_C1702A.jpg License: CC-BY-SA-3.0 Contributors: Author personnal collection. Original artist: • Author : Poil 01:10, 17 Apr 2005 (UTC) • File:Fivestagespipeline.png Source: http://upload.wikimedia.org/wikipedia/commons/2/21/Fivestagespipeline.png License: CC-BY- SA-3.0 Contributors: ? Original artist: ? • File:Folder_Hexagonal_Icon.svg Source: http://upload.wikimedia.org/wikipedia/en/4/48/Folder_Hexagonal_Icon.svg License: Cc-by- sa-3.0 Contributors: ? Original artist: ? • File:Front_Z9_2094.jpg Source: http://upload.wikimedia.org/wikipedia/commons/2/21/Front_Z9_2094.jpg License: Public domain Contributors: Own work Original artist: Ing. Richard Hilber • File:IBM_360_20_TROS.jpg Source: http://upload.wikimedia.org/wikipedia/commons/6/64/IBM_360_20_TROS.jpg License: CC- BY-SA-3.0 Contributors: Own work I took these photos at the en:Computer History Museum and edited them together into a single photo. Original artist: en:User:RTC • File:IBM_T42_Motherboard_IMG_2591a.jpg Source: http://upload.wikimedia.org/wikipedia/commons/8/85/IBM_T42_ Motherboard_IMG_2591a.jpg License: CC BY-SA 3.0 Contributors: Own work Original artist: Eddau • File:Intel_80486DX2_bottom.jpg Source: http://upload.wikimedia.org/wikipedia/commons/e/e7/Intel_80486DX2_bottom.jpg License: CC BY-SA 2.0 Contributors: ? Original artist: ? • File:Intel_80486DX2_top.jpg Source: http://upload.wikimedia.org/wikipedia/commons/d/dc/Intel_80486DX2_top.jpg License: CC BY-SA 2.0 Contributors: ? Original artist: ? • File:Intel_ICH7_Southbridge.JPG Source: http://upload.wikimedia.org/wikipedia/commons/7/70/Intel_ICH7_Southbridge.JPG Li- cense: CC BY-SA 4.0 Contributors: Own work Original artist: Julianprescott2604juuly • File:Marktanteil_GPU-Hersteller.png Source: http://upload.wikimedia.org/wikipedia/commons/2/20/Marktanteil_GPU-Hersteller. png License: CC BY-SA 3.0 Contributors: Own work Original artist: Mark H. • File:Memory_module_DDRAM_20-03-2006.jpg Source: http://upload.wikimedia.org/wikipedia/commons/c/ca/Memory_module_ DDRAM_20-03-2006.jpg License: Public domain Contributors: ? Original artist: ? • File:Motherboard_diagram.svg Source: http://upload.wikimedia.org/wikipedia/commons/b/bd/Motherboard_diagram.svg License: CC-BY-SA-3.0 Contributors: Transferred from en.wikipedia; transferred to Commons by User:Moxfyre using CommonsHelper. Original artist: user:Moxfyre. Original uploader was Moxfyre at en.wikipedia • File:Nopipeline.png Source: http://upload.wikimedia.org/wikipedia/commons/2/2c/Nopipeline.png License: CC-BY-SA-3.0 Contribu- tors: ? Original artist: ? • File:Nuvola_apps_ksim.png Source: http://upload.wikimedia.org/wikipedia/commons/8/8d/Nuvola_apps_ksim.png License: LGPL Contributors: http://icon-king.com Original artist: David Vignoni / ICON KING • File:PCIExpress.jpg Source: http://upload.wikimedia.org/wikipedia/commons/f/fc/PCIExpress.jpg License: CC-BY-SA-3.0 Contribu- tors: come from en.wikipedia Original artist: w:user:snickerdo • File:PDP-11-M7270.jpg Source: http://upload.wikimedia.org/wikipedia/commons/8/88/PDP-11-M7270.jpg License: GFDL Contribu- tors: Own work Original artist: Shieldforyoureyes Dave Fischer • File:PDP-8i_cpu.jpg Source: http://upload.wikimedia.org/wikipedia/commons/0/03/PDP-8i_cpu.jpg License: Public domain Contribu- tors: http://en.wikipedia.org/wiki/Image:PDP-8i_cpu.jpg Original artist: Robert Krten • File:Padlock-silver-light.svg Source: http://upload.wikimedia.org/wikipedia/commons/2/28/Padlock-silver-light.svg License: CC0 Contributors: ? Original artist: ? • File:Personal_computer,_exploded_5.svg Source: http://upload.wikimedia.org/wikipedia/commons/4/41/Personal_computer%2C_ exploded_5.svg License: CC BY 2.5 Contributors: ? Original artist: ? • File:Phoenix_bios.jpg Source: http://upload.wikimedia.org/wikipedia/commons/2/23/Phoenix_bios.jpg License: CC-BY-SA-3.0 Con- tributors: ? Original artist: ? • File:PokemonSilverBoard.jpg Source: http://upload.wikimedia.org/wikipedia/commons/c/cc/PokemonSilverBoard.jpg License: CC BY-SA 3.0 Contributors: Own work Original artist: Simon A. Eugster • File:Question_book-new.svg Source: http://upload.wikimedia.org/wikipedia/en/9/99/Question_book-new.svg License: Cc-by-sa-3.0 Contributors: Created from scratch in Adobe Illustrator. Based on Image:Question book.png created by User:Equazcion Original artist: Tkgd2007 • File:ROM_BIOS.jpg Source: http://upload.wikimedia.org/wikipedia/commons/3/3d/ROM_BIOS.jpg License: Public domain Contribu- tors: ? Original artist: ? 11.10. TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES 81

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