Multiprocessor Initialization of INTEL SOC in Coreboot

Multiprocessor Initialization OF INTEL SOC in Coreboot

1 Agenda

• Intel Multiple Processor (MP) Initialization • Coreboot + Intel FSP Boot Flow • Problem with existing model • Solution space • Design • Future Scope

2 Intel Multiple Processor (MP) Initialization

• The IA-32 architecture (beginning with the P6 family processors) defines a multiple-processor (MP) initialization protocol called the Multiprocessor Specification Version 1.4.

• The MP initialization protocol has the following important features:

• It supports controlled booting of multiple processors without requiring dedicated system hardware.

• It allows hardware to initiate the booting of a system without the need for a dedicated signal or a predefined boot processor.

• It allows all IA-32 processors to be booted in the same manner, including those supporting Intel Hyper-Threading Technology.

• The MP initialization protocol also applies to MP systems using Intel 64 processors.

• Entire CPU multiprocessor initialization can be divided into two parts – BSP (Boot Strap Processor) Initialization – AP (Application Processor) Initialization

Reference: Intel SDM Multiple Processor Init - section 8.4

3 Coreboot + Intel FSP (Firmware support package) Boot Flow

Coreboot/BIOS

FSP * Coreboot uses its own temp ram init code. 4 Problem Statement with existing model • Background: Coreboot is capable enough to handle multiprocessor initialization on IA platforms. So ideally, CPU features programming can be part of Coreboot MP Init sequence. • But, there might be some cases where certain feature programming can't be done with current flow of MP init sequence. Because, Intel FSP-S has to program certain registers to meet silicon init flow due to SAI (Security Attributes of Initiator) and has to lock other registers before exiting silicon init API. Also, certain features programming can not be done after calling FSP-S from Coreboot. • E.g. Intel SGX (Software Guard eXtension), ACPI PM timer emulation, C6 DRAM etc.. features have certain programming flows. • Platform code might need to compromise on those features if we don't plan to provide an alternate interface which can be used by coreboot (or any other BIOS firmware) and be as open as possible while using Intel FSP. Solution space

# Options Pros Cons Notes

1 coreboot performs complete MP initialization by Coreboot’s opensource MP Init CNL onwards platforms • USE_COREBOOT_NATIVE_MP_INIT its own. framework is utilized. would get compromised Kconfig option to select. on some of the features, • SoCs like SKL, KBL, APL are okay to make like Intel SGX, Intel use of this solution. C6DRAM. 2 coreboot skips MP initialization and make use of FSP does every thing for MP init and Coreboot’s open source • USE_INTEL_FSP_MP_INIT Kconfig option Intel FSP to do the job. restricted CPU features MP Init framework is not to select. initialization. utilized. • Also, Coreboot can set various UPDs to configure CPU features programming. • As of 2019 all Intel SOC based Google Chrome products are using coreboot native MP initialization mechanism and some IOTG platforms are using Intel FSP MP Init solution as well. 3 coreboot publishes PPI (PEIM to PEIM Interface). • Coreboot’s open source MP Init N/A • USE_INTEL_FSP_TO_CALL_COREBOOT_P In this case, coreboot will use its native MP init framework is utilized. UBLISH_MP_PPI Kconfig can be set to framework and additionally publish MP service • Intel FSP will execute restricted choose this solution. PPI for Intel FSP to consume. CPU features programming using • For latest Intel SoCs like CNL, ICL, etc, its Coreboot APIs. recommended to make use of this option in order to perform restricted CPU features programming like SGX , C6DRAM.

6 Design Layout

In a Nutshell, 1. Create MP PEIM-PEIM interface (PPI). 2. Provide this MP PPI pointer to Intel FSP via FSP-S upd parameter (CpuMpPpi). 3. FSP executes PPI to perform CPU features programming. MP Services APIs [PI specification vol 1, section 8.3.9]

EDK specs Coreboot implementation

PeiGetNumberOfProcessors cpu_read_topology() to get processor count

Fill ProcessorInfoBuffer: • ProcessorID: APIC ID: lapicid() PeiGetProcessorInfo • Status Flags: Processor health | BSP_bit • Location: { Package ID, Core ID, Thread ID } with EFI_PEI_MP_SERVICES_PPI CPUID mMpServicesPpi PeiStartupAllAPs mp_run_on_aps() based on MP_RUN_ON_ALL_CPUS mp_run_on_aps() based on argument PeiStartupThisAP “logical_cpu_num” PeiSwitchBSP Optional. Hence return “not supported”. PeiEnableDisableAP Provide CPU number based on APIC ID, make use of PeiWhoAmI cpu_map structure to convert apic id to cpu number.

Code: https://review.coreboot.org/q/topic:%2522PUBLISH_MP_SERVICE_PPI%2522+(status:open+OR+status:merged) bootblock Coreboot does the multi-processor initialization during ramstage early before calling FSP-S APIs. romstage 1 All possible APs are out of reset and ready to execute CPU feature programming. ramstage AP 0 Coreboot creates MP services API as per PI 2 MP initialization CallingFSP-S Fill FSP-S UPDs FSP-S Fill specification vol 1, section 8.3.9. AP 1 Coreboot 1 MP Services MP 2 . . . Implement EFI_MP_SERVICES_PPI structure into API

AP n Coreboot and point “CpuMpPpi” FSP-S UPD to it, before calling FSP-S entry point. FSP-S to publish EFI_MP_SERVICES_PPI based on structure provided by Coreboot. At later 4 3 stage of FSP-S call, locate MP service PPI and 3 run CPU feature programming on APs While executing EFI_MP_SERVICE_PPI to run Intel FSP CPU feature programming, FSP-S will invoke 4 Coreboot MP service API and run “restricted” Install MP InstallPPI services Locate MP ServiceLocatePPI feature programming on APs Programmingon FSP-Notify CPUFeature FSP-M FSP-S FSP-T CPUs Future Scope

• This PEIM-PEIM interface can be expanded for serial debug library • Today “cbmem –c” only shows coreboot serial log only. • With this approach coreboot serial library may be used by Intel FSP to populate its debug message. • With that “cbmem –c” might show both coreboot and intermediate Intel FSP serial log together. (if FSP debug is enabled) • Any other suggestions are welcome! Questions ?

Pratik Prajapati ([email protected])

Subrata Banik ([email protected])