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Introduction to I What is coreboot? I How can I try it out? I How can I contribute? What is coreboot?

coreboot is firmware targeting multiple mainboards and processor architectures, including . By default, ’s are running coreboot. You can get coreboot on laptops from System76, , and some refurbished . Payloads

coreboot itself only initializes hardware and will need a payload to execute. The default payload of coreboot is SeaBIOS, an open implementation of a legacy BIOS. You can use any ELF binary as a payload, including a kernel or a DOOM port. Stages

coreboot consists of multiple stages.

1. Boot Block (CAR / Cache As RAM) 2. Verification (TPM, vboot) 3. ROM stage (memory init, ucode update) 4. RAM stage (PCIe, SMM, ACPI) 5. Payload How can I try it out? Run coreboot in an

See the end users docs at https://coreboot.org/users.html.

1. clone the repo: git clone https://review.coreboot.org/coreboot.git && cd coreboot 2. build the toolchain: make toolchain- CPUS=4 && make iasl 3. generate a generic config: make defconfig 4. build it: make -j4 5. run it in QEMU -system-x86_64 - build/coreboot.rom -serial stdio Demo Output

coreboot-4.9-2-g96374e7978-dirty Mon Mar 18 17:28:15 UTC 2019 bootblock starting... 2 CBFS: 'Master Header Locator' located CBFS at [200:40000) CBFS: Locating 'fallback/romstage' 4 CBFS: Found @ offset 80 size 3c04

6 coreboot-4.9-2-g96374e7978-dirty Mon Mar 18 17:28:15 UTC 2019 romstage starting... 8 CBMEM: IMD: root @ 07fff000 254 entries. 10 IMD: root @ 07ffec00 62 entries. Output (continued)

CBFS: 'Master Header Locator' located CBFS at [200:40000) 2 CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 3d00 size aca9 4 Decompressing stage fallback/ramstage @ 0x07fbcfc0 (128664 bytes) Loading module at 07fbd000 with entry 07fbd000. filesize: 0x15750 memsize: 0x1f658 6 Processing 1257 relocs. Offset value of 0x071bd000

8 coreboot-4.9-2-g96374e7978-dirty Mon Mar 18 17:28:15 UTC 2019 ramstage starting... 10 Enumerating buses... Output (continued)

CBFS: Locating 'fallback/payload' 2 CBFS: Found @ offset 1c080 size 12ba8 [...] 4 Loading segment from ROM address 0xfffdc2d4 Entry Point 0x000fd258 6 Jumping to boot code at 000fd258(07fb4000) SeaBIOS (version rel-1.12.0-19-g2cb654b) Run coreboot on real hardware

1. get a fully supported device, e.g., Thinkpad X230, T430 etc 2. get a SOIC8 test clip and an SPI programmer, e.g., CH341A 3. open the laptop and read out the old ROM using 4. configure coreboot for your device and build it 5. flash it Demo? Come to our workshop! :) How can I contribute? Ways to contribute

I fix bugs, implement features I write documentation I port to new hardware I get board schematics and other docs I work on coreboot utils I Thanks! :)