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Applications of the Scalable Coherent Interface to Data Acquisition At CERN LIBRARIES, GENEVA e8a ¥foi`<¥ lllll flliIllllllllllllllllllllllllllll SCOOOO0123 SP:. Ib RDC- EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH ... 3 Q` 6 CERN DRDC 92-6 QJan.DRDCPBS 2 , 1992 Add.1 Applications of the Scalable Coherent Interface to Data Acqu1s1t1on at LHC A. Bogaertsl, J. Buytaertz, R. Divia, H. Miillerl, C. Parkman, P. Ponting, D. Samyn CERN, Geneva, Switzerland B. Skaali, G. Midttun, D. Wormald, J. Wikne University of Oslo, Physics Department, Norway S. Falciano, F. Cesaroni INFN Sezione di Roma and University of Rome, La Sapienza, Italy V.I. Vinogradov Institute of Nuclear Research, Academy of Sciences, Moscow, Russia K. Lochsen, B. Solbergs Dolphin SCI Technology A.S., Oslo, Norway A. Guglielmi, A. Pastore Digital Equipment Corporation {DEC}, Joint Project at CERN F·H. Worm, J. Bovier Creative Electronic Systems {CES}, Geneva, Switzerland C. Davis Radstone Technology plc, Towcester, UK joint spokesmen Fellow at CERN Scientific associate at CERN, funded by Norwegian Research Council for Science and Humanities OCR Output $U?£(.<> Addendum to P33 The proposed work on SCI during 1992 has been revised due to delays in availibil ity of SCI chips. The revised plans are summarized in the new appendices A-D below. Some parts of the project for which the necessary items will not be available in 1992 (such as cache controller chip, the SCI-fiber version, the SCI-SCI bridge and the Futurebus+ bridge) have been postponed till 1993. This concerns primarily the cache coherent readout proposed for the 3"" level trigger. The content and spirit of proposal P33 is however unchanged. We will concentrate on building an SCI demonstration system which should test the data moving properties first, and at the same time prepare the first stage of an SCI ringlet system. This stage will initially not make use of caching nor cache coherency. These features will be added and tested after a successful first stage in 1993. The demonstration system will use an environment which produces real data. We have chosen Delphi because several participants have either historical or current links with DELPHI. Beneficial for this choice is that both profound knowledge of the Delphi Fastbus system is available within the SCI team and budget contributions to Fastbus·SCI developments can be expected under condition that these developments are linked to DELPHI. Resources are to a large extent brought in from other sources than the DRDC. The DEC-CERN Joint Project will contribute a VAXstation and interfacing software. The SCI-Fastbus interface will be developed and financed by the University of Oslo and ECP—EDA. Resources requested from the DRDC have been confined to the one year pro gram 1992-1993 and have consequently been reduced. DRDC money will be mainly used for constructing the first stage of the ringlet system during 1992. External con tributions have been increased. Interfacing to SCI has been simplified by connecting directly to the CBUS of the node chips. CBUS-adapters are required for SCI connections to external mem ory, Sparcstation (SBUS), VAXstation/DECstation (TURBOchannel), and VMEbus CPUs. All of these adapters have Dolphin’s CBUS in common, i.e. the bus protocol of the SCI node chips. By choosing modern, hardware independent design tools, we can build these adapters jointly with various partners. CERN-EDA will design the TUR BOchannel adapter, CERN/Dolphin the 68040 adapter, Dolphin the SBUS adapter, CERN/Dolphin/Radstone the VMEbus adapter and CES the RISC R4000 (MIPS) adapter. The CAE work at CERN on TURBOchannel interfacing will be carried out in collaboration with the NA48. The method of ’e1ectron.ic breadboarding’ using com puters leaves the choice of hardware open until the implementation stage when specific programmable devices, such as the XILINX technology, or fast ASICs can be selected. Due to this flexibility in hardware, the first stage of the SCI ringlet can still be refined, and even reprogrammed at implementation time. An SCI interface to external memories of data acquisition systems, such as the two port memories of the RD12 or RD16 projects can be derived from the design of the demonstration system, where experience with CBUS adapters has been acquired. OCR Output The SCI-68040 adapter is specifically important since it provides a natural in terface to 68040 based CPUs such as the VMEbus based SBC from Radstone but also commercial 68040 based workstations and possible standard VMEbus and Futu turebus+ bridges. Large computer manufacturers have expressed their interest in this development. This design could be the basis of many commercial products and will initially be carried out at CERN in collaboration with Dolphin. Most developments required for the construction of the first ringlet sys tem are carried out by our industrial partners. Apart from SCI chips, we expect commercial interfaces to Sparc workstations via SBus and MBus, developed by Dol phin. Two major European VME manufacturers, Radstone and CES are offering to extend their current VME CPU architectures to include SCI ports. The interfacing to VAXstations is performed with strong support from the Digital Joint Project at CERN. Our test program for the ringlet sytem includes access to data from external memories and performance measurements of the data driven implementation of the 2 level global trigger. SCI behavioural parameters will be measured and used as input into our large system simulation. Diagnostic hardware and software will be provided by the Physics Department of the University of Oslo. This software will be written for Dolphin’s SCI Tracer, connected to a UNIX workstation. This work has already started. The test software to control and evaluate both the demo system and the ringlet will be provided by ECP·DS. This software is a first step towards data acquisition packages for SCI. The new features of SCI need first to be tested and understood before such packages can be specified. The development environment is UNIX. We will adhere as much as possible to open standards such as Posix and Motif, following the work of RD13. The architectural studies of large SCI based DAQ systems are being continued. These studies, carried out in the object-oriented MODSIM II language within ECP-DS and ECP·RA, are meant to predict the behaviour of different architectural approaches, such as the data driven and the process-driven concept. These studies require input parameters from hardware components as well as from the detailed SCI behaviour. A large part of the required hardware descriptions are already available in Verilog, whilst the SCI protocol description is ava.ilable as the C code description of the IEEE P1596 specification. OCR Output A Collaboration with industry The European computer industry is providing a large measure of essential support for our proposal. Several companies are involved, lending their expertise as well as design and de velopment effort. In addition to bilateral contacts with our direct partners (listed below), the Project has numerous relations with industry at large through its involvement with the IEEE SCI standardisation process. These include: Apple Computers (personal computer net works), Hewlett Packard (optical SCI applications and specific SCI memories) and National Semiconductor (low—voltage CMOS implementations of SCI). CREATIVE ELECTRONIC SYSTEM- SA (Switzerland) CES is a very important supplier of VMEbus and related equipment to CERN and other research laboratories. They are bringing their expertise in VMEbus RISC microprocessor implementations and system interconnect technology to provide an intelligent data controller which will be used for the collection and high-performance processing of data. DIGITAL EQUIPMENT CORPORATION (CERN Joint Project) DEC is well known as a supplier of computer equipment and software for real-time appli cations. The DEC-CERN Joint Project, based on the CERN site, is participating in our proposal, bringing their experise in this field, particularly in the domain of powerful work stations allied to data acquisition systems. DOLPHIN SCI TECHNOLOGY AS (Norway) Dolphin is the supplier of indispensable technology and expertise for the SCI. Their personnel are heavily involved in the IEEE standardisation process for the SCI itself (IEEE Pl596) as well as a VMEbus to SCI bridge (IEEEP1596.1). They have taken the world-wide lead in developing the VLSI parts necessary for the initial implementation of SCI node. They are contributing one engineer who is working full-time at CERN paid by Dolphin and the Norwegian Research Council for Science and Humanities. RADSTONE TECHNOLOGY plc (United Kingdom) Radstone is a major manufacturer of VMEbus boards and VMEbus-based systems. They are bringing that expertise into the project to design and construct an SCI general-purpose CISC-based processor module in VMEbus. This device will provide the means to graft SCI into existing data acquisition systems and allow the early testing of some basic architectural concepts without major investments in hardware and software. OCR Output B 1992 Budgets Our revised budget estimation covers one year of pu1·cha.se and development of SCI test equipment, starting from an assumed approval in 2/92 and ends at 3/93 This includes the demo system and the first stage of the ringlet system. Work on the second stage after 2/93 will require an additional budget. DEMO SYSTEM: [fig. 2] kCHF Source VAXstation 4000 20 DEC Joint Project System Software: 20 DEC Joint Project TURBOchaxmel-XILINX interface: 10 ECP·EDA 1 CBUS·FIFO interface: 10 DRDC 1 CBUS-Fastbus interface: 10 ECP-EDA 2 SCI Node chips + carrier: 10 DRDC Fastbus Cable Master: 20 Uni Oslo Phys SCI Cables Connectors etc: DRDC Subtotal 105 (DRDC contribution: 25) STAGE 1 RINGLET SYSTEM [fig. 1] RADSTONE 68040 CPU: 10 Radstone RADSTONE SCI Node Adapter: 20 Radstone CES MIPS CPU: 15 CES CES MIPS·SCI Adapter: 15 CES Diagnostic Tracer: 30 Uni Oslo Phys. Var. Software Dolphin: 20 DRDC 1 SCI Node chips incl.
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