UPA—Sun'shighperformance Graphicsconnection

UPA—Sun’sHighPerformance GraphicsConnection TechnicalWhitePaper 1999 Sun Microsystems, Inc. All rights reserved. Printed in the United States of America. 901 San Antonio Road, Palo Alto, California 94303 U.S.A. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, Ultra, Sun Elite3D, Sun Enterprise, Java 3D, PGX, Java, SBus, and VIS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. OpenGL is a registered trademark of Silicon Graphics, Inc. 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Please Recycle Contents Introduction. 1 Analyzing System Design and Application Performance. 2 Design Trade-offs . 2 An Overview of the UPA Interconnect . 3 Scalability, High Bandwidth, and Efficiency . 5 The UPA64S Graphics Bus. 6 Characterizing Application Performance and Bus Traffic. 7 UPA64S and Other Graphics Bus Technologies . 8 Comparing PCI and UPA . 8 Comparing AGP and UPA . 10 UPA64S Delivers Performance and Scalability Today . 14 The Future . 15 References . 17 i ii UPA — Sun’s High Performance Graphics Connection— January 1999 UPA—Sun’sHighPerformance GraphicsConnection Introduction Designing high-performance systems is a complex balancing act. As faster components are implemented in designs, performance bottlenecks inevitably shift to other areas of the system. For example, a faster processor may cause a bottleneck in performance to shift from the CPU to the system bus if the bus can’t feed data to the processor fast enough. A wider bus could cause the bottleneck to shift back again to the processor, or perhaps to some other part of the system. The challenge for system architects is to carefully balance system performance, and to keep costs within the product’s targeted goals. In 1994, engineers at Sun Microsystems faced these challenges in designing a new family of desktop workstations. These new systems — the Ultra family of workstations — were designed to use the new high-speed UltraSPARC family of processors. At that time, there was no standardized system or graphics bus technology with adequate bandwidth and scalability to meet Sun’s demanding performance requirements. For this reason, Sun developed the Ultra Port Architecture (UPA) interconnect bus architecture, which was first introduced at the heart of the Ultra 1 workstation in 1995. The UPA design has proven to be a superior interconnect architecture, even when compared to other bus technologies that have since emerged in the market. The purpose of this paper is to describe the UPA interconnect, and in particular, its functionality as a graphics bus. In addition, this paper will compare the UPA interconnect with other graphics bus technologies, and discuss how UPA helps to accelerate application performance. 1 Analyzing System Design and Application Performance Design Trade-offs In designing workstations for technical computing, system architects commonly make trade-offs between cost and performance (including the system’s ability to handle tasks concurrently, such as computations and simultaneous graphics display). Trade-offs are made according to the platform’s targeted markets and price points — for example, whether the system is aimed at low-end 2D graphics applications or high-end 3D geometry or texture mapping applications. As an example, a platform targeted at high- end performance graphics will typically perform geometry calculations on a graphics accelerator, freeing the processor for other computations. Other trade- offs include how much local graphics memory will reside on the graphics accelerator card, which may affect the frequency at which data is accessed from system memory. A high-bandwidth graphics bus can facilitate faster memory access, which can accelerate overall application performance. Sun’s approach is to engineer balanced systems performance into all of its system designs. Sun’s engineers architect a careful balance between major system components — processor, memory, I/O, and graphics (Figure 1). A system interconnect like UPA helps to deliver this balance, especially since UPA scales according to the system clock speed. As processor speeds increase, the UPA interconnect keeps pace, delivering faster data throughput, enabling better performance of attached UPA graphics devices. Processor I/O Memory Graphics Processor Graphics I/O Memory Figure 1 Sun architects systems for balanced performance 2 UPA — Sun’s High Performance Graphics Connection— January 1999 An Overview of the UPAInterconnect As shown in Figure 2, the UPA acts as a high-bandwidth interconnect between major system components in Sun systems. Because of its high bandwidth, the UPA interconnect enables fast data transfers between the processor, system memory, and any UPA-attached graphics accelerators. The net effect is faster application performance, especially for demanding graphics applications in Sun’s traditional markets: MCAD, MCAE, visualization, simulation, and DCC (Digital Content Creation). UltraSPARC UPA128 UltraSPARC (128-bit Data) UPA Cross-Bar Memory Interconnect I/O Bridge SBus or PCI Memory I/O Bridge SBus or PCI ... UPA Graphics Memory UPA Graphics (256-bit Data) UPA64S (64-bit Data) Figure 2 The crossbar design of the UPA interconnect allows simultaneous connections between major system components, unlike circuit-switched buses The UPA architecture is a crossbar interconnect design, allowing independent connections on the bus simultaneously — its packet-switched, crossbar nature is similar to interconnect designs used in many high-end servers and supercomputers. UPA —Sun’s High Performance Graphics Connection 3 In looking at Figure 2, note that the UPA interconnect is much more than just a graphics bus. The UPA interconnect is responsible for delivering data to bandwidth-hungry processors, as well as to graphics devices. Because the crossbar design allows independent connections, data transfers can occur at the same time between memory and processors and between memory and I/O devices. The UPA interconnect is also much more than a peripheral bus (such as PCI or SBus). As Figure 2 shows, Sun systems typically include PCI or SBus as a peripheral bus, in addition to the UPA interconnect at the heart of the system architecture. (More detailed comparisons of other bus technologies appear later in this paper.) As shown in Figure 2, different width paths are defined for different system components within the UPA backbone, enabling more balanced system performance. For example, the memory data path is 256 bits wide, while the data path to the processor(s) is 128 bits wide. The wide path to memory helps to deliver data quickly to the UltraSPARC processor(s), facilitating better performance as processor speeds increase. Data transfers to graphics accelerators occur over the 64-bit wide UPA path known as UPA64S. This 64-bit graphics bus provides high bandwidth — enough to sustain the real-time display of high-resolution video, such as that required for streaming uncompressed HDTV video (1920 x 1080 at 24 frames per second). The UPA64S graphics bus is discussed in more detail later in this paper. 4 UPA — Sun’s High Performance Graphics Connection— January 1999 Scalability, High Bandwidth, and Efﬁciency In originally designing the UPA interconnect, Sun’s engineers anticipated the need for a scalable design, one that could be used in a number of systems over an extended period of time. As the clock rate in systems increases, the UPA interconnect scales accordingly, as shown in Figure 3. Ultra 60 120-MHz 1.92-GB/s Ultra 2 100-MHz 1.6-GB/s 1998 Ultra 1 Clock Speed 83-MHz 1.3-GB/s 1996 Ultra 1 67-MHz 1.0-GB/s 1994 Time Figure 3 Bandwidth scales with the system clock When the UPA interconnect premiered in Sun’s Ultra 1 workstation, it was clocked at both 67-MHz and 83-MHz, which resulted in peak bandwidths of 1.07-GB/s and 1.32-GB/s. Today, at a clock speed of 120-MHz in Sun’s Ultra 60 workstation, the UPA interconnect can deliver up to 1.92-GB/s to the processor and 960-MB/s to a graphics accelerator. (For example, to sustain the display of a 1-million pixel truecolor image at 60 frames per second, a sustained bandwidth on the graphics bus of at least 180-MB/s is required. With a peak bandwidth of 960-MB/s, the UPA interconnect provides more than enough bandwidth for today’s — and even tomorrow’s — UPA-attached graphics accelerators.) Perhaps more important than raw bandwidth, the UPA interconnect is also extremely efficient, meaning that its sustained performance is very close to its peak bandwidth capabilities. This is because the UPA architecture features separate address, control, and data lines, which run at the full UPA speeds. UPA —Sun’s High Performance Graphics Connection 5 Other less-expensive bus designs may offer high peak bandwidths, but their sustained performance suffers because address and control lines are carried at slower speeds. Because of the UPA’s efficiency, high bandwidth, and tremendous scalability, it offers distinct advantages in Sun systems for performance hungry applications. The UPA64SGraphics Bus In Sun systems, high-performance graphics accelerators (like Creator, Creator3D, and the Sun Elite3D) attach directly to the 64-bit wide UPA graphics bus known as UPA64S.

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