Design Verification
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Design Verification Mike Butts Synopsys Prof. Kurt Keutzer EECS UC Berkeley 1 Design Process Design : specify and enter the design intent Verify: verify the Implement: correctness of refine the design and design implementation through all phases Kurt Keutzer 2 1 Design Verification HDL specification RTL manual Synthesis design netlist Is the Library/ design module logic generators optimization consistent with the original netlist specification? physical Is what I think I want design what I really want? layout Kurt Keutzer 3 Implementation Verification HDL RTL manual Synthesis design a 0 d netlist q b 1 Is the Library/ s clk implementation module logic generators optimization consistent with the original a 0 d q design intent? netlist b 1 s clk physical Is what I design implemented what I layout wanted? Kurt Keutzer 4 2 Manufacture Verification (Test) HDL Is the manufactured RTL manual circuit Synthesis design consistent with the a 0 d netlist q 1 Library/ b implemented s clk module logic design? generators optimization a 0 d Did they q b 1 netlist build s clk what I physical wanted? design layout Kurt Keutzer 5 Design Verification HDL specification RTL manual Synthesis design netlist Is the Library/ design module logic generators optimization consistent with the original netlist specification? physical Is what I think I want design what I really want? layout Kurt Keutzer 6 3 Verification is an Industry-Wide Issue Intel: Processor project verification: “Billions of generated vectors” “Our VHDL regression tests take 27 days to run. ” Sun: Sparc project verification: Test suite ~1500 tests > 1 billion random simulation cycles “A server ranch ~1200 SPARC CPUs” Bull: Simulation including PwrPC 604 “Our simulations run at between 1-20 CPS.” “We need 100-1000 cps.” Cyrix : An x86 related project “We need 50x Chronologic performance today.” “170 CPUs running simulations continuously” Kodak: “hundreds of 3-4 hour RTL functional simulations” Xerox: “Simulation runtime occupies ~3 weeks of a design cycle” Ross: 125 Million Vector Regression tests DesignDesign TeamsTeams areare DesperateDesperate forfor FasterFaster SimulationSimulation Kurt Keutzer 7 The Verification Crisis VerificationVerification ConsumesConsumes HardwareHardware DesignDesign CycleCycle 1995 Design Physical Creation Verification Implementation Design Physical 2002 Creation Verification Implementation Kurt Keutzer 8 4 Kurt Keutzer Productivity Gap Kurt Keutzer Verification Gap c Transistors per Chip ogi .10µ L .35µ c Transistors per Chip 2.5µ ogi .10µ L .35µ 2.5µ (K) (K) 10,000,000 1,000,000 10,000,000 1,000,000 100,000 10,000 100,000 1,000 10,000 1,000 100 10 100 10 1 1 1981 Complexity growth rate 1981 58%/Yr. compound Complexity growth rate 58%/Yr. compound 1983 1983 1985 x Tr./S.M. 1985 Logic Tr./Chip x Tr./S.M. x Logic Tr./Chip x 1987 1987 x x 1989 x 1989 x x x 1991 1991 x x 1993 x 1993 x 1995 21%/Yr. compound Productivity Gap 1995 Productivity growth rate 21%/Yr. compound Verification Gap Productivity growth rate 1997 1997 1999 1999 2001 2001 2003 2003 2005 2005 2007 2007 100,000,000 10,000,000 1,000,000 100,000 10,000 1,000 100 2009 10 100,000,000 10,000,000 1,000,000 100,000 10,000 1,000 100 2009 10 Source: SEMATECH Source: SEMATECH Productivity Productivity Trans./Staff - Mo. 9 10 Trans./Staff - Mo. 5 Why the Gap? logic_transistors lines_in_design bugs X X chip logic_transistors line_of_design bugs = chip Kurt Keutzer 11 Filling in Reasonable Numbers logic_transistors lines_of_design bugs X X chip logic_transistors lines_of_design 10,000,000 trs 1 1 X X chip 10 10,000 100 bugs = chip Kurt Keutzer 12 6 Raising the Level of Abstraction logic_transistors lines_of_design bugs X X chip logic_transistors lines_of_design 10,000,000 trs 1 1 X X chip 100 10,000 10 bugs = this year!! chip Kurt Keutzer 13 Moore’s Law Implies More Bugs logic_transistors lines_of_design bugs X X chip logic_transistors lines_of_design 1,000,000,000 trs 1 1 X X chip 100 10,000 1000 bugs = 5 years!! chip Kurt Keutzer 14 7 The Verification Bottleneck Verification problem grows even faster due to the combination of increased gate count and increased vector count 100 x 10,000 = 10B 2002 1 million times more Simulation Load 100M 1996 1M 1990 RequiredValidate to 10,000x more Vectors 100k1M 10M 100x Gate Count Kurt Keutzer 15 Time to boot VxWorks M. Butts - Synopsys 1 million instructions, assume 2 million cycles Today’s verification choices: 50M cps: 40 msec Actual system HW 5M cps: 400 msec Logic emulator1 (QT Mercury) 500K cps: 4 sec Cycle-based gate accelerator1 (QT CoBALT) 50K cps: 40 sec Hybrid emulator/simulator2 (Axis) 5K cps: 7 min Event-driven gate accelerator2 (Ikos NSIM) 500 cps: 1.1 hr 50 cps: 11 hr CPU and logic in HDL simulator3 (VCS) 5 cps: 4.6 days 1: assumes CPU chip 2: assumes RTL CPU 3: assumes HDL CPU Kurt Keutzer 16 8 Aspects of Design Verification Initial Specification Validation HDL Functional Verification (interactive) HDL Functional Verification (regressions) Implentatation In-System Verification Kurt Keutzer 17 Phases of Design Verification Basic Functionality Tapeout Finding tough bugs is ad hoc & brute force ¾ takes 80% of time, effort, & resources ¾ represents most of the risk Bugs Found ¾ is an unbounded problem Time Kurt Keutzer 18 9 Technologies for Design Verification Software Simulation – Application of simulation stimulus to model of circuit Hardware Accelerated Simulation – Use of special purpose hardware to accelerate simulation of circuit Emulation – Emulate actual circuit behavior - e.g. using FPGA’s Rapid prototyping – Create a prototype of actual hardware Formal verification – Model checking - verify properties relative to model – Theorem proving - prove theorems regarding properties of a model Kurt Keutzer 19 Matching Problems and Technologies Event Driven Specification Event-driven Simulation – Interactive Phase Validation – High flexibility Functional – Quick turnaround time Verification – Good debug capabilities (interactive) Cycle-based simulation Cycle-base Functional simulation – Regression Phase Verification – Highest performance (regressions) – Highest capacity Emulation and Acceleration In-System Emulation/ – In-System Verification Verification Rapid Protyping – Highest performance – Highest Capacity Implementation – Real system environment Equivalence Checking Verification Kurt Keutzer 20 10 Axis (Emulator) View Kurt Keutzer 21 Approaches to Design Verification Software Simulation – Application of simulation stimulus to model of circuit Hardware Accelerated Simulation – Use of special purpose hardware to accelerate simulation of circuit Emulation – Emulate actual circuit behavior - e.g. using FPGA’s Rapid prototyping – Create a prototype of actual hardware Formal verification – Model checking - verify properties relative to model – Theorem proving - prove theorems regarding properties of a model Kurt Keutzer 22 11 Simulation: The Current Picture Simulation Simulation Monitors driver engine SHORTCOMINGS: • Hard to generate high quality input stimuli – A lot of user effort – No formal way to identify unexercised aspects • No good measure of comprehensiveness of validation – Low bug detection rate is the main criterion • Only means that current method of stimulus generation is not achieving more. Kurt Keutzer 23 Simulation Simulation Monitors Simulation Drivers driver engine Symbolic simulation Diagnosis of Vector Coverage unverified generation analysis Input stimuli consistent with circuit portions interface must be generated Environment of circuit must be represented faithfully Tests can be generated – pre-run (faster, hard to use/maintain) – on-the-fly (better quality: can react to circuit state) Environment and input generation programs written in – HDL or C, C++, or – Object-oriented simulation environment • VERA, Verisity Sometimes verification environment and test suite come with product, e.g. PCI implementations, bridges, etc. Kurt Keutzer 24 12 Simulation Simulation Monitors Simulators driver engine Symbolic simulation EVENT DRIVEN Diagnosis of Vector Coverage unverified generation analysis • VCS portions • Affirma • Verilog-XL, ... CYCLE-BASED • Cyclone VHDL • Cobra, ... HYBRID • VSS Kurt Keutzer 25 Simulation Simulation Monitors Monitors driver engine Symbolic simulation Reference models (e.g. ISA model) Diagnosis of Vector Coverage unverified generation analysis Temporal and snapshot “checkers” portions Can be written in C, C++, HDLs, and VERA and Verisity: A lot of flexibility Assertions and monitors can be automatically generated: 0-in’s checkers Protocol specification can be given as a set of monitors a set of temporal logic formulas (recent GSRC work) Kurt Keutzer 26 13 Types of software simulators Circuit simulation – Spice, Advice, Hspice – Timemill + Ace, ADM Event-driven gate/RTL/Behavioral simulation – Verilog - VCS, NC-Verilog, Turbo-Verilog, Verilog-XL – VHDL - VSS, MTI, Leapfrog Cycle-based gate/RTL/Behavioral simulation – Verilog - Frontline, Speedsim – VHDL - Cyclone Domain-specific simulation – SPW, VCC, COSSAP, Architecture-specific simulation Kurt Keutzer 27 Event-driven simulation Key elements: – Circuit models and libraries • cells • interconnect – Event-wheel • Maintains schedules of events • Enables sub-cycle timing Advantages – Timing accuracy – Handles asynchronous Disadvantage - performance and data management Kurt Keutzer 28 14 Event versus cycle-based simulation D Q data D Q clock QN Combo Logic clock QN D Q clock QN clock data Event-Driven Simulator: • Simulates Function • Tracks event activities and timing