SuperH® Family of Microcontrollers and Microprocessors

®

2006.4 Renesas Technology America

SuperH® Family of Microcontrollers & Microprocessors 2006 Catalog

Renesas — Your Best Decision for Microcontrollers and Microprocessors Choose for your next design; use for all your future ones.

Renesas Technology, the leading global supplier of microcontrollers and microprocessors for embedded systems, especially flash microcomputers, makes it easy to select the right device for any application. The hundreds of devices in our H8®, M16C™ and SuperH® families, among others, have upwardly compatible architectures and standard platforms covering wide spans of performance, integration, power efficiency and price points. Your choices extend from cost-effective 8-bit microcontrollers to high-performance 16-bit and high-end 32-bit devices. These easy-to-use chips can enable your design innovations now and in the future. Our advanced silicon solutions simplify system optimizations, facilitate design enhancements and diversifications, and help you meet tight cost budgets.

Key markets for Renesas microcontrollers and microprocessors include the mobile, automotive and PC/AV fields. For example, we are a leader in devices for car information systems, the technology forerunner in application processors for multimedia mobile phones, and an innovator in devices for power inverter applications. By choosing world-class Renesas solutions, you get highly reliable designs produced in high-quality fabrication facilities, and benefit from ongoing development defined by solid technology roadmaps. You can shorten your system design cycles and improve your time-to-market by taking advantage of our total system support, including software solutions, starter kits, reference platforms, reference designs, and middleware. Expert third-party support is available as well.

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IMPORTANT! • This document may, wholly or partially, be subject to change without notice. • All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without the express permission of Renesas Technology America, Inc. • Renesas will not be held responsible for any damage to the user that may result from accidents or any other reasons during the operation of the user’s unit according to this document. • Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Renesas semiconductor products. Renesas assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. • No license is granted by implication or otherwise under any patents or other rights of any third party or Renesas Technology Corp. • MEDICAL APPLICATIONS: Renesas products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Renesas’ sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Renesas products are requested to notify the relevant Renesas sales officers when planning to use the products in MEDICAL APPLICATIONS. Support andtraining Off-the-shelf solutions environment Development Power consumption Code compatibility Architecture roadmap interfaces Industry-standard On-chip peripherals Graphics support DSP support Floating-point and Flash ROM Code efficiency Power/performance Cost/performance Performance Market Needs 32-Bit 16-Bit 16-Bit • LowestcostMCUs 8-Bit for8-bitapplications • Lowestcostsystemsolution • BroadestselectionofMCUs atanaggressiveprice highintegration • Highperformance, • HighestperformanceCISC • Highestintegration • Highestperformance 32-Bit RISC DSP (SH2-DSP, SH3-DSP),superscalarFPU(SH-2A,SH-4,SH-4A) Up to1MBflash,accessibleinonecycleat80MHz;single-voltageprogrammable 16-bit instructions:upto40%smallermemoryfootprint,more dataincache High MIPS/Wratings High MIPS/$ratings Up to1080MIPS,4.2GFLOPS(SH-4A);up360MIPS(SH-2A),superscalararchitecture SuperH Solutions Experienced application engineers,online evaluation lab,trainingcourses Middleware, reference boards, broad OS support Comprehensive integratedH/WandS/Wtools,extensive third-party support, on-chipdebug Low static/dynamicoperating currents, highMIPS/W ratings,power-down modes Upward compatiblefamilies(SH-1,SH-2,SH-3,SH-4) Instruction setaccommodatessuperscalardesigns PCI,SCI,I USB, Ethernet, BSC, cryptoaccelerator, more Timers, DSP, MMU,A/D,D/A,memorycontroller, LCDcontroller, AFE,motor controller, cache, Superscalar operation[FPUoperationsindependentofnon-FPU operations](SH-2A,SH-4,SH-4A) H8/300H SLPseries H8/300L SLPseries SH-2, SH2-DSP, SH-2Aseries H8/Tiny series H8SX series SH-3, SH3-DSPseries H8S series SH-4, SH-4Aseries 2 C, PCMCIA,audio,CAN,SmartCard, IrDA,SDRAM,DDR-SDRAM

H8 Architecture Architecture SuperH M16C/62P series M32C/100 series M16C/Tiny series M32C/80 series M32C/90 series R8C/Tiny series Introduction

M16C Architecture SuperH® Family of Microcontrollers & Microprocessors 2

The SuperH Family Roadmap

Up to SH-4A 1800 MIPS

SH-4A Up to (Superscalar & FPU) 1080 MIPS

SH-4 Up to (Superscalar & FPU) 432 MIPS

SH3-DSP Up to Up to (Hybrid RISC/DSP) 260 MIPS 720 MIPS SH-Dual SH-3 Up to (MMU and Cache) 260 MIPS SH-2A Up to (Superscalar & FPU Opt.) 360 MIPS PERFORMANCE

SH2-DSP Up to 81 MIPS Available (Hybrid RISC/DSP) Now

SH-2 Up to NEW (Multiply/Accumulate) 173 MIPS

In SH-1 26 MIPS Planning

APPLICATION COMPLEXITY

The first 32-bit SuperH RISC device was introduced in Our SuperH MCUs for general-purpose embedded system 1993. In the years since, this popular product line has use — devices in the SH-1, SH-2, SH2-DSP and (New!) continuously grown and steadily evolved. Today it SH-2A series — currently offer performance levels up to encompasses eight major product families, with more in 360 MIPS. Most provide reliable, high-capacity flash development. They continue a solid technology roadmap memory that is easy to use and simplifies system designs. of innovation fine-tuned to meet the changing needs of Our SuperH MPUs for specialized applications — devices designers of embedded systems for diverse global in the SH-3, SH3-DSP, SH-4 and (New!) SH-4A series — markets. now deliver performance levels up to 1080 MIPS. Many have on-chip peripherals tailored for leading-edge A steadfast goal throughout the history of the applications, like those in the automotive, mobile, and SuperH family has been to produce microcomputers PC/AV markets, among others. A large international [microcontrollers (MCUs) and microprocessors (MPUs)] community of technology partners and third-party that deliver optimum mixes of performance and vendors support SuperH microcomputers, offering functionality, achieve requisite levels of performance operating systems, drivers, middleware, tools, consulting at low power, and have compact packages. We also services and more to facilitate the rapid development of work to ensure that SuperH devices are offered at SuperH-based products. competitive prices and are supported by a comprehensive suite of Renesas hardware and software development The SuperH family of MCUs and MPUs serve a wide tools. Importantly, we maintain code compatibility range of embedded systems. The table on the next page throughout the product line to facilitate software reuse summarizes key applications of each device series. that saves development time and engineering cost. 3 Family Overview

SuperH Series Performance, Features and Applications

Core CPU/Bus Speed Performance Series Features / Remarks Key Applications

SH-2 80/40MHz 104 MIPS SH7080 High-performance embedded AC/DC drives, inverters, SH7040 controller with integrated servo/motion controllers, SH7140 RAM/cache/ROM/flash and machine tools advanced motor control timers

50/40MHz 65 MIPS SH7125 SH/Tiny series; compact package

133/66MHz 173 MIPS SH7600 SH-Ether series; Industrial control, networking integrated Ethernet, host interface

SH2-DSP 62.5/31.25MHz 81 MIPS/ SH7065 Combined RISC/DSP architecture; Industrial control, 125 MOPS SH7600 derivatives with integrated networking, Ethernet and PWM timers office automation

SH-2A 200/66MHz 360 MIPS SH7200 High performance, superscalar, Industrial control, optional FPU, fast interrupt office automation, multimedia response time

SH-3 200/66MHz 260 MIPS SH7700 Low-power consumption, Office appliances, high-speed, MMU, cache, bar code scanners, SDRAM I/F, PCMCIA digital still cameras

SH3-DSP 200/66MHz 260 MIPS/ SH7729R Combined RISC/DSP architecture; Handheld/portable devices, 400 MOPS SH7727 pin-compatible to some SH-3 routers, cable modems, SH7720 derivatives, other features similar postage meters, multimedia, SH7710 to SH-3 devices web phones

SH-4 240/120MHz 432 MIPS SH7750R High performance, superscalar, CIS/telematics, video game 1.7 GFLOPS SH7751R FPU, vector graphic operations, consoles, sub-note books, SH7760 MMU, SDRAM I/F, PCMCIA, etc. set-top boxes, residential gateways, etc.

SH-4A 600/300MHz 1080 MIPS SH7780 High performance, superscalar, CIS/Telematics, 4.2GFLOPS SH7785 FPU, vector graphic operations, home multimedia, SH7763 SuperHyway bus, MMU, entertainment, gateways DDR-SDRAM interface

A GLOBAL LEADING POSITION

Renesas Technology has acquired an impressive reputation for leadership and earned a large share of the embedded processor market in leading-edge growth areas of automotive and mobile applications. For example, through SuperH devices incorporating an SH-4 or SH-4A CPU core, we have gained about an 80% worldwide share of the microcontrollers used in car navigation systems. And our SH-Mobile family is the de facto standard in application processors for mobile phones, being used in over 200 different models. As we expand the SuperH family, we are applying the advanced technology acquired in those fields to other markets that have technology and application challenges, such as industrial control and office automation. Techniques for obtaining improved power efficiency have wide appeal, as do on-chip peripherals and high code density. The SuperH family of MCUs and MPUs continues to be the architecture of choice for embedded system designers. SuperH® Family of Microcontrollers & Microprocessors 4

■ SuperH Architecture: Common Features SuperH Instruction Set

RISC-type instruction set Code • Instruction length: fixed compatibility 16-bit-long instructions for SH-4A improved code efficiency 103 instructions FPU, Cache operations • Load-store architecture SH-4 (basic arithmetic and logic 91 instructions operations are carried out Single/double-precision FPU between registers) SH3-DSP SH-3 160 instructions 68 instructions • Delayed unconditional branch 92 DSP instructions MMU Control

instructions reduce pipeline SH-2 SH-2A compatibility 62 instructions Code Code SH2-DSP 91 instructions disruption 32-bit MAC 154 instructions Enhanced shift, bit, compatibility & divide operations 92 DSP instructions • Instruction set optimized for SH-1 112 Instructions 56 instructions the C language with FPU Mixed Fixed Mixed 16-/32-bit length 16-bit length 16-/32-bit length

CPU register set SuperH Programming Model • Sixteen 32-bit general-purpose registers

31 0 • Up to 7 control registers and 31 0 R0 General Register R0 4 system registers for fast jumps R1 R1 R2 and interrupt response R2 - • - • - • - • • R7 Efficient caching scheme R7 • for each series • • R14 • LRU replacement policy R15 algorithm for improved hit rates 31 0 31 0 Control Register SR: Status Register SSR: Saved Status Register • Each family’s cache architecture MD RR RI M Q I I I I . . S T GBR: Global Base Register has been optimized for the best VBR: Vector Base Register 31 0 latency/miss-rate balance: System Register MACH: Multiply and Accumulator High e.g., SH-4A devices have MACL: Multiply and Accumulator Low 32KB + 32KB, 4-way PR: Procedure Register set-associative, separate 31 31 0 0 instruction and operand caches Program Counter PC: Program Counter SPC: Saved Program Counter for improved performance : Accessible only in Privilege mode (SH-3 and SH-4 only) 5 The SuperH Architecture

Built in hardware multiply-accumulate unit SH-2A/SH-4/SH-4A Two-Way Superscalar Architecture • 16-bit x 16-bit + 42-bit 64 bit (SH-1 devices) Parallel execution 8 instruction x 16 bit InInsstructiontruction queuequeue • 32-bit x 32-bit + 64-bit of two instructions InInsstructiontruction queuequeue (SH-2, SH-3, SH-4 chips) Inst. 1 Inst. 2

Instruction execution Decoder 1 Decoder 2

• Scalar architecture: One instruction per clock cycle

• Superscalar architecture (SH-2A/SH-4/SH-4A onwards): Branch unit Integer unit Load/store unit Floating point unit Maximum of two instructions (BR)(EX) (MT) (LS) (MT) (FE) per cycle

• 5-stage instruction pipeline Superscalar Operations (7-stage in SH-4A)

Clock Memory Management Unit for RTOS (SH-3 and beyond) Instruction Instruction Instruction Instruction Single Scalar A B C D ··· ··· • 4-Gbyte address space, Instruction Instruction ··· 256 address space identifiers Superscalar A C Instruction Instruction ··· Execution (8-bit ASIDs) B D time = 1/2 • Single virtual mode and Parallel processing multiple virtual memory mode Execution time

• Supports multiple page sizes: 1KB, 4KB, 64KB, 1MB MMU Block Diagram • 4-entry fully-associative TLB Data for instructions Bypass Physical • 64-entry fully-associative TLB Cache RAM Data for instructions and operands Tags • Supports software-controlled replacement and random- Address counter replacement algorithm VPN offset MMU Page TLB (1KB or 4 KB): • TLB contents can be accessed page boundary: Virtual Address 0 1 directly by address mapping 2 offset

PPN offset 127 Physical Address Page Tables

Swap Area TLB Miss Handler Paging Routine Mass Storage SuperH® Family of Microcontrollers & Microprocessors 6

DSP registers SH2-DSP Core Architecture • Two 40-bit data registers, six 32-bit data registers Single CPU Engine with Two Execution Units

4-Bus Structure • Modulo register (MOD, 32 bits) Parallel execution of 1 program fetch and 2 SH RISC CPU decodes DSP instructions added to control registers data accesses • Background DMA-capable Can generate three addresses for DSP instructions 32 or execute RISC instructions IAB • Repeat counter (RC) added to 32 DSP execution unit LAB General-purpose registers status registers (SR) 16 16 x 32-bit file single-cycle MAC and YAB General-Purpose other DSP functions • Repeat start register (RS, 32-bit) 16 Register File XAB 8 x 32-bit and repeat end register (RE, 32-bit) Data Register File added to control registers

DMAC RISC RISC RISC ALU

or or or MULT DSP(Y) DSP(X) DSP Key DSP instructions Memory Memory Cache (4-way ALU Flexible Memory unified) • Saturation arithmetic for Data/Program Barrel Decoder CONTROL SIGNAL (2 banks for Shifter 16/32-bit ALU – Prevents overflows and underflows each X and Y) Pre-Fetch Unit – Result that exceeds the 16 register width is set to the XDB 16 max width of the register YDB (Ex: H’FF + H’01 = H’FF). 32 LDB • Guard bits 32 DB – DSP execution unit has two 40-bit registers that provide an additional 8 bits to accommodate ■ SuperH Hybrid RISC/DSP Full-featured 16-bit integer overflow/underflow results Architectural Features DSP capabilities • Independent add and multiply operations Instruction set upward compatible • Executes four independent parallel operations with SuperH RISC chips – Either multiply and then add on • Upward compatible with SuperH: • Single-cycle 16x16 operations the same data, or multiply and add on two separate data SH1, SH-2, SH-3 (for SH3-DSP) • Harvard architecture: accesses • Execute four independent • Compact 16/32-bit instruction one instruction and two data operations simultaneously code (32-bit code only for DSP words per cycle instructions) • Zero overhead looping, circular – multiply , add, mov x, mov y buffer, saturation arithmetic – suited for performing FIR filters A single SH and DSP CPU engine optimized for low power and cost Adds DSP performance to the Easier to program and simplified • Less than 5% power increase SuperH architecture product development from SH core (non-DSP) • Performs a real FIR algorithm • Multitasking instead of • Less than a 10% size increase of T taps in T cycles multiprocessing from SH core (non-DSP) • Simultaneous access of • Eliminates inter-processor • Unified program/data memory two data buses and one communication for RISC and DSP operations instruction bus • Single hardware/software design environment 7 Hybrid RISC/DSP Architecture • Floating Point Features

■ SuperH On-Chip Floating Point Co-processor 128-bit Floating Point Vector Engine: DSP/SIMD Instructions Architectural Features

• Supports single-precision 16-tap, 40-sample block FIR (1.6 MACs/cycle) (32 bits) and double-precision STAGE 1 STAGE 4 (64 bits) yi xi xi+1 xi-2 xi-3 c0 xi-12 xi-13 xi-14 xi-15 c12 • 10-stage floating instruction yi+1 xi+1 xi xi-1 xi-2 c1 xi-11 xi-12 xi-13 xi-14 c13 = x + ... + x pipeline (SH-4A) yi+2 xi+2 xi+1 xi xi-1 c2 xi-10 xi-11 xi-12 xi-13 c14 yi+3 xi+3 xi+2 xi+1 xi- c3 xi-9 xi-10 xi-11 xi-12 c15 • Supports IEEE754-compliant data types and exceptions

• Floating-point registers: 32 bits x 16 words x 2 banks 1024-point, radix-2 FFT (35.4 cycles)

• (Single-precision x 16 words, In1 Out1 1 0 1 0 In1_r Out1_r or double-precision x 8 words) 0 1 0 1 In1_i Out1_i x 2 banks a -b -a b x In2_r = Out2_r b a -b -a In2_i Out2_i • 32-bit CPU-FPU floating-point In2 Out2 communication register (FPUL) -1 W=a+jb A single DIF butterfly • Supports FMAC (multiply- and-accumulate) instruction Versatility of the floating point co-processor • Supports FDIV (divide) and FSQRT (square root) instructions MULTIPLICATION • Supports FLDI0/FLDI1 A single SuperH (load constant 0/1) instructions Y1 c11 c12 c13 c14 x1 instruction, FTRV, Multiplication Y2 c21 c22 c23 c24 x2 can perform this • 3D graphics instructions 3-D graphics = x Y3 c31 c32 c33 c34 x3 matrix-vector geometry (single-precision only) 1 c41 c42 c43 c44 1 multiplication every 4 cycles. • 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 8 cycles (latency) INNER PRODUCT

• 4-dimensional vector (FIPR) d1 Rn inner product: 1 cycle (pitch), Surface judgement d2 I = r1 r2 r3 0 x 5 cycles (latency) brightness d3 calculation ray 0 • Instruction execution times source d – Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), A single SuperH instruction, FIPR, can perform this 8 cycles (double-precision) inner-product multiplication every cycle. – Pitch (FMAC/FADD/FSUB/FMUL): Powerful 4-way FPU for 3-D graphics 1 cycle (single-precision), 6 cycles (double-precision) SuperH® Family of Microcontrollers & Microprocessors 8

SH-2A Enhancements SH-4A Enhancements

Higher Execution Relative Value SH-4A SH-4 Performance 6 5 6x • Superscalar gives 4 Higher Performance 600 MHz @ 1.25V 240 MHz @ 1.5V 3 4.8x 1.5x more performance 2 at Lower Power at the same MHz 1 0 Improved Micro- Superscalar Superscalar • SH-2A = 6x the SH-2 SH-2A SH-2A @50MHz @160MHz @200MHz Architecture 7-Stage Pipeline 5-Stage Pipeline performance of SH-2 Improved FPU 10-Stage Pipeline 5-Stage Pipeline Faster Interrupt Relative Value Architecture Response Time 1 0.75 • SH-2: 37 cycles; 0.50 Larger Cache Size 32/32 KB I/O Cache 16/32 KB I/O Cache SH-2A: 6 cycles 0.25 0 1/25x 4-Way 2-Way • SH-2A = 1/25 the SH-2 @ 50MHz SH-2A @ 200MHz Set-Associative Set-Associative response time of SH-2 Greater Bandwidth SuperHyway Shared Bus Denser Program Code Size Relative Value 1 Bus Architecture 3 Independent • Improved C compiler 0.75 Buses 0.50 0.75x and additions to 0.25 Instruction Set 103 Instructions 91 Instructions instruction set provide 0 25% code size reduction SH-2 SH-2A Architecture

TOP REASONS TO SELECT SuperH

■ Total upward code compatibility Upward Code Compatibility The roadmap for the SuperH processor product line is upwardly code compatible. This cale SH-4 S compatibility enables a faster time-to-market s

Toshiba IBM Free SH-3 NEC IDT with further amortization of prior engineering cale S SH-2 investment and preservation of previously Atmel/Cirru Free Intel written software. SH-1 ARM7

Non-DSP Instructions ARM9 XScale • Processor choice from 10 to 1080 MIPS

DSP

tions

Instruc- • Large selection of devices within each family SuperH ARM MIPS PowerPC

■ Best code efficiency

• 16-bit instruction length for high code SuperH Code Efficiency density

C Object Size Comparison • Up to 40% less memory footprint than SuperH 1.0 32-bit instructions (16-bit fixed) V830 1.24 (32-bit variable) • Up to 40% more data in cache than MIPS64 1.28 32-bit instructions (32-bit fixed) ARM 1.44 (32-bit fixed) • Twice the number of instructions loaded on the SDRAM bus PowerPC 1.5 (32-bit fixed) RELATIVE VALUE 0.5 1.0 1.5 9 Top Reasons To Select SuperH

TOP REASONS TO SELECT SuperH

■ Balanced power/performance Bus State Controller, via the external bus, provides the specialized inputs, outputs and functions for The fast speeds that SuperH devices provide would different types, widths, and speeds of external not be usable by portable applications if the chips’ memory (8/16/32-bit interfaces to DRAM, power dissipation was excessive. Therefore, Renesas SDRAM, DDR-SDRAM, flash, ROM, etc.) has designed the RISC and RISC/DSP devices in low-power sub-micron CMOS processes with ■ Best cost/performance low-voltage capabilities. Low static operating current is achieved in all circuit designs; low dynamic (peak) The SuperH architecture has a superior performance- currents are guaranteed by logic and circuit design. to-price ratio (Dhrystone MIPS/$). The architecture’s 16-bit RISC instruction set reduces system memory • Power-reducing techniques used in cache design requirements, which lowers the overall cost of – The sense amplifiers utilize SRAM circuit-design embedded system designs. techniques that reduce word-line voltage swings; this permits lower currents to be used without ■ sacrificing speed Superior floating point and DSP support

– A unique cache-way-enable circuit minimizes power • The SuperH floating point (SH-2A, SH-4, SH-4A) demands by turning on the sense amplifiers only in that and DSP (SH2-DSP, SH3-DSP) support is built into portion of the cache that has a “hit” in a given access; this the processors to reduce overall system cost and reduces the cache data array's operating current by 75% system power consumption. • Software-controlled power-reduction mechanisms: • The SH-4 FPU is ideal for computer graphics and – Each device family offers a selection of power-reduction can be utilized to efficiently implement multimedia techniques from a palette that includes Standby and and networking operations. Sleep modes, clock-speed control and selective module shutdown – Low operating and standby currents for longer battery life. SH2-DSP Signal Processing Performance ■ High integration JPEG image compression/expansion Renesas meets the dual needs for compact devices and processing performance: • 10 times higher than SH-1 low system cost by providing a broad choice of on-chip • 3 times higher than SH-3 memories and peripherals in the SuperH series. JPEG compression processing time (in seconds) • Large size and high performance on-chip memory: 01234 5 Up to 1MB on-chip flash memory, up to 128KB

on-chip RAM, and up to 32KB instruction and SH-1 5.3 32KB data cache 20 MHz

SH-2 3.36 • 4- to 12-channel DMAC, 2 to 5 SCIs, 16-bit and 28 MHz 32-bit timers (3 to 34 channels), up to 149 I/O SH-3 ports, RTC, analog interfaces (4 to 32 channels), 1.56 60 MHz Image size (VGA): 640x480 2 I C, CAN (up to 2 channels), others 24-bit full color SH2-DSP 0.55 Y: Cr: Cb = 4: 2: 2 60 MHz • All SuperH-series processors feature direct Compression ratio: 1/10 interfaces to external memories. The on-chip SuperH® Family of Microcontrollers & Microprocessors 10

TOP REASONS TO SELECT SuperH

■ SuperH has 2D and 3D graphics capabilities Fast Data Transfers to Frame Buffers Using the SH-4 Store Queues SuperH RISC and RISC/FPU microprocessors have excellent graphics-handling capabilities, SDRAM Graphic Processor DIRECT ACCESS allowing consumer-level prod- s ucts with highly integrated, SH-4 H Bu

S Geometry enhanced features at popular Processor SQ 1-32 Bytes PRIMITIVES Frame Buffer

Local OF DISPLAY prices. Systems built with other CPU Interface Display SQ 2-32 Bytes LIST processor architectures require a Controller Frame Buffer Interface Frame Buffer separate graphics chip, which would increase complexity and Display add cost.

• Superscalar architecture SuperH Flash Roadmap (SH-2A, SH-4, and SH-4A) – Allows FPU operations to occur Memory Structure 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013

independently from non-FPU 80MHz (0.2- 0.18µm) NOR operations of the system. This Stack (NOR) 80MHz (150nm) optimizes the performance NOR (180nm)

M 50MHz of the graphics calculations 80MHz

M (150nm) 100MHz and minimizes flicker and MONOS Metal Oxide M 100MHz (130nm) graphic stalling. Nitride Oxide Silicon

M 100MHz (90nm)

• Pair single-precision data (65nm) 133MHz (45nm) New transfer – Data transfer Next-Gen NVM NVMs MRAM 166MHz can be performed by pair New NVM single-precision data transfer instructions, which enable two single-precision (each 32-bit) data items to be transferred for without a penalty cycle. This functionality is especially double the transfer performance. useful to transfer video, graphic or display list data to the frame buffer of the graphic processor. • Vector/matrix calculation – Data can be processed efficiently because four multiplication operations and ■ SuperH MCU flash technology leadership one addition operation are performed in parallel. Fourth-generation embedded flash, introduced in 2002, • Geometric-operation instructions – To enable features single-cycle access to on-chip flash memory. high-speed computation with a minimum of hardware, geometric-operation instructions • 0.18µm process, flash size as high as 1MB perform approximate-value computations. • Access as fast as 12.5ns @ 80MHz • The SH-4 supports two 32-byte store queues (SQ) to perform high-speed burst writes to external memory. • Up to -40°C to +125°C range While the contents of one SQ are being transferred to • Minimum endurance up to 10,000 erase/write cycles external memory, the other SQ can be written to 11 Top Reasons To Select SuperH

TOP REASONS TO SELECT SuperH

■ SuperH standard, off-the-shelf solutions SuperH Multimedia Solution Example

Renesas’ qualified middleware and proven reference boards comprise a complete set of solutions that can reduce overall chip count and minimize system cost, without sacrificing perform- ance. These solutions allow a faster time to market.

■ SuperH offers broad OS support

• SuperH offers a broad range of operating system choices to accommodate diverse applications.

■ Sophisticated on-chip debug controller

• Hardware Break Controller provides 2 to 4 independent hardware breakpoints

• Advanced User Debug (AUD) on SH-3 and SH-4 devices provides trace capability

• Third parties offer tools that support the SuperH on-chip debug by utilizing the SuperH hardware resources in the RTOS debug environment

• JTAG BSDL is available for SH-3, SH3-DSP, SH-4, and SH-4A User Debugging Interface (UDI) [JTAG = Joint Test Action Group, a standard developed for boundary scan test. TDI BSDL = boundary scan debug layer] ter • Emulators are available from s Renesas and third-party suppliers SDIR hift Regi S • Development environments are available SDID from Renesas and third-party vendors TDO MUX

■ User Debugging Interface (UDI)

• Supplied with E10A-USB and E200F TCK in-circuit emulators (see page 20) Local TMS TAP Controller Decoder Bus • The main unit of the emulator is connected through the UDI port to the user’s system SuperH A (MediaAccessControl)functions MAC • ■ Aunifiedmemoryarchitecture • Powercontrolfunction • Hardware-rotationmodeis • Supportsinversionoftheoutput • Supportsvariationsoftheburst • Supportsdataformatsfor • 8-bitframeratecontroller • 1/2/4bppgrayscale • 1/2/4/6/8/16bpp(bitperpixel) • From16x1to800x600pixels • ■ Shortpackets/long packets – Supportsfull-duplexandhalf-duplex – Built-inFIFO(2KBforTx, 2KBforRx) – CRC/PAD processing – CSMA/CDlinkmanagement – Dataframeassembly/disassembly – stored insystemmemory so theimagedatafordisplayis is adoptedfortheLCDcontroller portrait-format LCDpanels landscape-format LCDpanelsas included tosupporttheuseof LCD panel’s signalpolarity signal, ifnecessary, tomatchthe high data-readspeeds synchronous DRAMtoachieve length inreadingfromthe (8/12/16/18-bit buswidth) STN/dual-STN/TFT panels with 18-bitcolorpallet (SVGA) canbesupported Ethernet MAC Ethernet Controller LCD Peripheralstransmission/reception (collision avoidance,processing incaseofcollision) (IEEE802.3-compliant frame) ® Family ofMicrocontrollers &Microprocessors EtherC FunctionBlockDiagram ControllerBlockDiagram LCD P Clock LCLK CKIO MAC Peripheral Bus ECMR.DM Command/ Tran Receive Control Interface Bus Interface s P mit Control S R.LMON S PIR MagicPacket • CompatiblewithMII(MediaIndependentInterface) • A (Contents AddressableMemory) Interface CAM • tatu Regi Variable transferrate:10/100Mbps – 18TTL-levelsignals(5Vor3.3V interface) – Stationmanagement(STA) functions – Converts8-bitdatastreamfromMAClayertoMIInibble – standard s (based onPHYchipfeatures) data stream(4bits) s ter TX RX Li Bu G Li Bu enerator Interface s Cloc Interface ™ MII (with wake-on-LANoutput) s k

clk LCDC MDC/ MCIO LIN Power Control MII 512 byte K Pallet RAM Line Buffer 2.4 kbyte PHY s

S PHY Chi s T S M/DI VEPWC VCPWC DON LCD 15 FLM CL2 CL1 D p S S P 0 12 13 Fourtransfermodes (Control, • Compatiblewith Universal • ■ Otherfeatures • 16-bitfree-runningtimer(FRT) • Supports7operatingmodes • Supports12CPUinterrupts • Datatransmission:Two methods • Databuffers:32(onereceive-only • Numberofchannels:1or2 • Bosch2.0B version: CAN • ■ Interrupt, Bulk, Isochronous) Serial Busstandardver. 2.0 DTCcanbeactivatedbymessage – prescaler with flexibleclocksourcesand Messagepriority(identifier) – Mailbox(buffer)numberorder – be setfortransmission/reception) buffer and31bufferswhichcan Datalength:0to8bytes – Communicationspeed:Max. – Transmission path:Bi-directional – Broadcastcommunicationsystem – Communicationsystems:NRZ – active compatible Universal SerialBus (CAN) Controller Area Network Peripheralsreception mailbox reverse-order (high-to-low) (high-to-low) 1Mbps (at40MHzoperation) 2-wire serialcommunication (with bit-stuffingfunction) (Non-Return toZero)system Overcurrent detectionfeature • Offersfull-speedmode (12Mbps) • RootHubfunction • and low-speedmode(1.5Mbps) USB BlockDiagram CAN BlockDiagram

Port 2 Peripheral Address Bus Port 1 Port 1 USB Host U SuperH MainOn-chipPeripherals S

B function Peripheral Data Bus Tran Tran Tran CAN Power Power Power s s s ceiver ceiver ceiver BCR Microprocessor Interface (MPI) Control 16-bit Timer Tran pwr_en REC Tran s ceiver s VBU i ufrReceiveBuffer mit Buffer Tran S s ceiver pwr_en ho S multiplexer multiplexer control pin tran multiplexer elect RD HTxD1 HRxD1 pwr_en/ s s VBU t/function ignal U s S ceiver B S S elect s On-chiptransceiver • Upto127endpoints control • / (multiplex Host orFunction) (Function) canbespecified (Host) and4endpoints U S Tran Tran B digital U U s s S S 1 2 ceiver ceiver B B s ignal TEC Mailboxes Mailbox Control 0 to31 U U U U U U U U S S S S S S S S B2_pwr_en B1_pwr_en B2M B2P B1M B1P B1d BF_VBU S / SuperH Two typesofDMACchannel priority • Choiceofaddressmode;singleordual; • Choiceof8-bit,16-bit,32-bit,64-bit,or • Uptotwelvechannels • ■ Supportforbig-endianandlittle-endian • 32-bitor16-bitmemorydatabusfor • SRAM,DRAM,SDRAM,DDR-SDRAM, • Six32-bitx16longwordinternalFIFO • FourDMAtransferchannels • Whenoperatingasmaster, PIOand • Canoperateasmasterortarget • ArbitrationcontrolisavailableasaPCI • UptofourPCImasterdevicesrunningat • Compatiblewith32-bitPCIbus • CompatiblewithPCIbusoperating • ■ robin mode ranking: fixed-prioritymode andround- burst mode choice ofbusmode:cyclesteal modeor 32-byte transferdatalength modules operateswithbigendian) endian, whileinternalbusforperipheral local bus(PCIoperateswithlittle connected toSDRAMorDDR-SDRAM) transfers withPCIbus(32-bitwhen for PCIbusdatatransfers and MPXcanbeusedasexternalmemory writing, andfourforDMAtransfer) (one fortargetreading,one DMA transferareavailable host function 66MHz, canbeconnected 33MHz, oronePCImasterdeviceat speeds of33MHz/66MHz Peripherals Controller (DMAC) DMA Peripheral Control Interconnect (PCI) ® Family ofMicrocontrollers &Microprocessors C BlockDiagram PCI MC SingleandDualAddressModes DMAC: Internal Peripheral Internal Acknowledge Bu (Peripheral Bu Module Bu s Interrupt Reque DMAC DMAC B B : Dataflow 2nd bu S S in theB SuperH device SuperH device C s C 1 s t SuperH Device s s from thetran s t bu ) DUAL-ADDRESS MODE:Two-cycle readandwrite SINGLE-ADDRESS MODE:Parallelreadandwrite Data Buffer s Data Buffer S cycle: s C' cycle: DAR S DAR S AR AR s Module Bu DMAC data buffer intheBu Peripheral databuffer i Interface Internal PCIC Module Interrupt Control Ta s regi Local Ta fer k ing theDARvaluea k s s ing the ter ource moduleand s DACK s

addre E bu w x S ritten tothetran ternal ternal s Address bus Address bus AR valuea s ss

S B )Cycle:Bcyc (Bf Local Bu

tate Controller (B Local Bu data bu E s x theaddre s s ternal ternal theaddre tored temporarilyinthe

Data bus s Data bus PCIC Bu Data Tran PCI Bu Clock Regi Regi s Regi s fer de Local Local Local s s s s ter ter s ss ter s Interface s ss Controller Tran s Tran , thedata tination module. S fer Control , datai C). Tran Tran 32B s s from CKIO Input Clock Feedback with DACK Configuration PCI Bu fer De fer De E Memory Memory Module Module Module Module s E s memory Regi device x fer fer (2 s x FIFO ternal ternal PCI read ternal s s S tored S s ide s s s ter ource ource tination tination s )6 (PCICLK) 33/66 MHz PCI Clock 14 15 Adjustablecarrier frequencyforlowswitching losses • Output-offfunctions • PWMdutyprogrammable between0and100% • PWMoutputhaltedbyexternal signal • Toggle output synchronizedwithPWMperiod • Non-overlaptimesgeneratedbytimer’s deadtime • Triangular-wave comparison-type6-phasePWM • ■ HIFbootfunctioneliminatestheneedforROM • ConnectabletothemainCPUwithparallelbus • ■ Transfer canbesetinbyte,word,orlongwordunits • Activationbysoftwareallowed • Directspecificationof32-bitaddressspace • Oneactivationsourcecantriggeranumberofdata • 3transfermodes:normal,repeat,andblock • Transfer possibleoveranynumberofchannels • ■ Channelfunctions:differenttransfermodes • Various DMACtransferrequestsareprovided: • AninterruptrequestcanbesenttotheCPUon • and lessaudible noise improved voltageutilization counters decreasetorquepulsations/harmonicsfor waveform outputwithnon-overlapdeadtimes transfers (chaintransfer) can besetforeachchannel Auto-request(Atransferrequestisgenerated – On-chipperipheralmodules(Transfer requestsfromthe – Externalrequest – completion ofthespecifiednumbertransfers Motor ManagementTimer(MMT) Host Interface(HIF) Data Transfer Controller (DTC) Peripheralsautomatically withintheDMAC) SCI, SCF, andTMUcanbeacceptedonallchannels.) SuperH MainOn-chipPeripherals 2channel8-bit D/Aconverter • 4-to32-channel10-bitsuccessive-approximation • ■ Deadtimecanbegeneratedautomatically • A/Dconvertertriggersignalcanbegenerated • Highsinkcurrent(15mA)for6pins;candirectly • Countercascademodeto32-bitcounter • 2-phaseencoderpulseup/downcount • Upto12-phasePWMoutputwithsynchronous • ■ Threesample-and-holdswithmaximum conversiontime – Precisecurrentdetectionfor control – A/D converter drive opto-isolators operation Analog Interfaces Multi-function TimerUnit(MTU) of 5.4microseconds reque Interrupt memory Fla Main CPU Data Transfer ControllerBlockDiagram s s h t controller Interrupt Main CPUbu 16 bit Host InterfaceBlockDiagram reque s DTC Connectable withgeneralbu ervice s s RAM S RAM HIF s H-2 t On-chip 1KBRAM S H7618 Channel n S n +2 n +1 H7619 Ether-C Cache DMAC E- s PHY S LAN port H localbu Memory Destination Serial I/O Source DMA Register Destination Memory data Source Boot ROM Optional memory S Fla DRAM s s LAN h SuperH® Family of Microcontrollers & Microprocessors 16

■ Overview

Renesas and the many third-party suppliers in the • Debugging—When you begin working on the design SuperH community provide a wide range of hardware of your system, you can develop code using the full and software tools and other support services. Renesas unlimited compiler in exactly the same HEW offers products that cover all stages of the development environment. To track down bugs, use Renesas’ on- of embedded systems that use SuperH microcontrollers chip and full in-circuit emulators, which have and microprocessors. powerful specialized debugging hardware for trapping specific conditions and recording program activity. • Evaluation—Low-cost or no-cost Renesas tools make it easy to discover the capabilities of SuperH MCUs • Final Programming—Use Renesas’ Flash and test the problem-solving power of the tools Development Toolkit, which has an easy-to-use themselves, including the High-performance interface, to program your debugged application into Embedded Workshop (HEW) software development any of the many SuperH MCUs that incorporate and debugging environment. A free downloadable Renesas’ mature on-chip flash memory technology. evaluation version lets you evaluate the ability of the All the tools required for developing SuperH-based Renesas C/C++ compiler to generate efficient code, applications are available from Renesas distributors. and evaluation boards enable you to immediately test These tools have been developed by groups within the that code on known working hardware. In addition, worldwide Renesas organization, experienced engineers the Renesas Interactive remote engineering laboratory who have access to the designers of the devices gives you the ability to use your own PC to obtain themselves. Their insight and expertise ensures the best hands-on experience with powerful software and possible tool performance and support. hardware tools before purchase.

■ Software

Renesas’ Integrated HEW provides enhanced functional- customizable, so you can create an Development Environment ity and an integrated instruction even more efficient environment for simulator that allows you to debug developing your application. The High-performance Embedded application code even when Workshop (or HEW) is a graphical Wizards simplify start-up processes hardware isn’t available. Also, the development environment for C/C++ compiler toolchains bundled You can start projects fast by taking C/C++ compiler toolchains with an with HEW generate code that advantage of HEW’s Project industry-standard look and feel. executes faster and/or takes Generator “Wizards.” Let them Through the use of menus, toolbars, less memory space on Renesas guide you through the selection of status bars, dockable windows and processors. configuration options, debugger context-sensitive local menus, HEW targets, and the creation of startup integrates key capabilities that can One familiar interface, code. help you create and manage your many functions embedded microcontroller software projects. Its capabilities include: You can quickly learn the powerful tools you need for developing • Project creation and editing application code, and you have easy- • Graphical configuration to-use control over those tools. of compiler tools Moreover, you can work with an • Project make interface that remains consistent across the entire range of Renesas • Debugging MCUs and MPUs for greater • Version control efficiency. The interface is also highly 17 SuperH® Development Tools

HEW 4 Integrated Development Environment

Project Manager – Graphical control of compiler/linker options – Function browser Local – Drag-and-drop code Variable templates Watch – Built-in (or external) project make C/C++ Variable Watch Output Window – Shows messages from build and Stack find-in-files Trace – Linked to source in editor – Version-control log Complex Break Conditions Built-in Editor – Syntax sensitive coloring – Multiple files open at once Full Bus Virtual Desktop Memory View – Source-level debugging Trace – Allows multiple screen layouts to be – Highlights changed recalled at the click of a button values

New features to help optimize your application code HEW Profile Tree and Chart views The integrated simulator/debugger has specific features and windows for testing the application code produced in the build process:

• Code profiling window (includes statistical and graphical displays)

• Performance analysis

• Code coverage window

Additional analysis tools help you understand the operation and architecture of your embedded system application:

• Call Walker stack trace analyzer

• Link Map file viewer SuperH® Family of Microcontrollers & Microprocessors 18

HEW Compiler Toolchain Options Dialogs

■ Software (continued)

Optimized C/C++ code generation Free evaluation HEW download performance. After 60 days, code toolchains size is limited to 256 Kbytes, which The flexible licensing technology still allows you to evaluate the The Renesas compiler toolchains in Renesas’ compiler toolchains architecture or experiment with (compiler, assembler and linker) means you can download a free peripherals or, for smaller devices, support the full C++ language evaluation copy of HEW with the even complete a full application, specification and are backward compiler and generate unlimited since the evaluation version is compatible with C. They have code for 60 days. This is very identical to the full version with extensions for complete embedded useful for benchmarking optimiza- the exception of the code size system control directly from C, tion efficiency and architecture limits. without requiring the use of any assembler code. These extensions cover: Flash Development Toolkit • Interrupt service routines

• Condition control register operations

• Sleep instruction

• Pseudo functions for instructions such as multiply-and-accumulate and decimal add and subtract

• Control of the optimized addressing and function call features of the device architecture and instruction set

The inter-module optimizing linker produces optimized software load modules by performing global optimizations on your application. 19 SuperH® Development Tools

HEW Integrated Debugging ■ Hardware SuperH Modular debug target Evaluation and Development Kits RSK support is provided directly Renesas’ low-cost Evaluation and within the HEW environ- Development Kits (EDKs) are inex- ment so you can build your pensive ways to experience the per- application and debug formance of SuperH microcontrollers without leaving HEW. and microprocessors. Each kit comes A debug session wizard complete with an EDK board and a allows you to easily add a CD-ROM that contains: new debug target to your workspace: • Evaluation version of HEW with C/C++ compiler and a debug • Instruction Simulator monitor • In-Circuit Emulators • Flash Development Toolkit (FDT) (E200F series) • Quick-Start guide • On-chip Emulators (E10A-USB, E8) • Full documentation with sample tutorials and a tutorial Project • Evaluation boards using a Generator plug-in for HEW ROM-resident monitor

Renesas Starter Kits Flash Development Toolkit SuperH Solution Engine RSKs are the latest line of evaluation Renesas’ Flash Development and development kits from Renesas. The SuperH architecture provides Toolkit (FDT) is an easy-to- The target boards provide a standard- advantages in price, performance, use utility for programming ized platform for all Renesas MCUs power and code density. The Solution your code into the on-chip (H8, R8C, M16C, M23C and SuperH). Engine family of development boards flash memory of SuperH The kit comprises all of the content of make implementing SuperH-based MCUs. You can create the EDK kits and – additionally – a designs easy and provide complete workspaces to combine low-cost USB on-chip debugger (E8) system platforms ready for application several s-record files into one that provides full remote boot development with spacious SDRAM download image and save programming and debugging. and FLASH memory to enable develop- connection settings to easily ment of large and complex programs. manage device program- They also enable rapid ming. evaluation of the SuperH FDT offers: architecture and available SuperH peripherals. • Direct USB connection Solution for USB boot mode Engine Multiple vendors support devices the Solution Engine plat- forms with real-time • Serial communication at operating systems (RTOSs), up to 115,200 baud board support packages and • Hex image editor middleware to enable rapid product implementation for • Extensive messaging designs that require operat- that helps hardware ing systems. The Solution development Engine boards support SuperH® Family of Microcontrollers & Microprocessors 20

■ Hardware (continued) interface that can be used both to You can configure the AUD trace to debug the system and to program stream source and destination multiple SuperH devices. Typical the MCU’s on-chip flash memory. branch addresses, memory accesses features of the Solution Engine (from user-specified data buses and E10A-USB emulators use plug-and- include: “windows” in the address space) play USB 2.0 compatible interfaces and also source-level variables via a • External flash for user code for easy connection to both special software-trace function call. • EPROM containing monitor code notebook computers and desktop machines. These emulators offer: This data is compressed on-chip, • JTAG connector easily connects streamed out of the AUD port, and • 255 PC breakpoints to E10A on-chip emulator then captured in a dedicated • Unbuffered CPU bus connectors • One hardware breakpoint on trace buffer in the E10A-USB provide direct connection to data and address (HS0005KCU02H model only) or E200F (see next section). address data and control lines • The ability to save a record of up to the last eight branches • Expansion slot for daughter E200F Configurable boards (buffered CPU bus • On-chip flash programming On-Chip/In-Circuit Emulator provides direct connection to address data and control lines) The E10A-USB emulator is available The E200F is an expandable in two configurations: emulation system for both on-chip • I/O connectors (for SuperH and in-circuit debugging. It provides • HS0005KCU01H (14pin H-UDI) peripheral signals) all of the same H-UDI (JTAG) and • HS0005KCU02H AUD debug features as the E10A-USB on-chip emulators (14pin H-UDI + 36pin AUD) E10A-USB, but with enhanced The E10A-USB emulators, designed capabilities and system expansion Both provide on-chip debugging via to connect with Renesas’ JTAG with add on options. the Renesas H-UDI (JTAG) interface. on-chip debugging interfaces, Enhanced Capabilities provide real-time debugging on Advanced User Debug (AUD) The E200F has a high-speed USB the target device, using the dedicated 2.0 host interface for fast debug file Renesas’ Advanced User Debug debugging resources built into the download and data upload. Eight interface allows you to trace target microcontroller in your user AUD Event points allow you to halt real-time data out of the device hardware. The on-chip emulators on a match of AUD trace data while it is running in-system. connect to the target system via an such as branch source/destination address, windowed memory access and software data variable trace. E10A-USB Four external probe inputs and one Emulator external trigger output are also included.

Performance Analysis The E200F emulator provides three methods of application performance analysis: • On-chip performance • AUD performance analysis • Real-time profiling

The real-time profiling method gives execution statistics for 21 SuperH® Development Tools

AUD on-chip control logic Advanced User Debug (AUD) Trace

CPU DMAC DTC BSC

I-bus Address 32 bits I-bus Data 32 bits AUD Configuration dialog in HEW I-bus Command 4 bits HPB Address 8 bits HPB Data 16 bits HPB psize 1 bit HPB data HPB pms output HPB pread HPB pwrite AUD AUCSR AUDCK Window trace AUWASR control FIFO AUWAER Branch trace AUWBSR control AUDATA[3:0] AUWBER AUBCSR PFBA PFDA Sync logic Comparator Comparator control and state machine

P-P conversion

Legend AUCSR : AUD control register AUWASR : AUD window A start address register AUWAER : AUD window A end address register AUWBSR : AUD window B start address register AUWBER : AUD window B end address register AUBCSR : AUD bus master control register PFBA : Previous full branch address PFDA : Previous full data address

AUD Trace View in HEW showing memory window trace

functions in up to 4MB of the system address Included in main unit: Debugger (CD-R), E200F System space (8 x 512K blocks). An optional profiling AC adapter, USB cable, external probe Full Configuration expansion board increases the profiling capabil- ity to 12MB (24 x 512K blocks). Trace cable Expansion profiling (optional) unit (optional) External Bus Trace You can further expand the E200F system by

connecting the optional Bus Trace unit. This Top to bottom: lets you synchronously trace 256K external bus Trace unit Memory unit cycles from the device in your target system and EV-chip unit (all optional) examine them in the HEW IDE.

The Bus Trace unit also provides 10 Bus Event points that you can use to control trace acquisi- tion or halt program execution. SuperH® Family of Microcontrollers & Microprocessors 22

■ Hardware (continued)

Evaluation Chip Unit Emulation Memory Units The special “bond-out”chip on the The optional Emulation Memory units give you 8 or 16 Mbytes of system optional Evaluation Chip unit memory. When used with the Evaluation Chip unit, you can do real-time brings out internal CPU buses, software debugging without any target hardware. which – when used with the Bus Trace unit – give you full bus trace from within the device itself. The E200F Evaluation Chip unit has connec- Bus Event Setup tors on the underside that can con- nect, via a user interface adaptor, to your target system in place of the regular chip. You can then emulate the device in your target system with access to all the E200F Emulator’s enhanced debugging features – even with devices that lack the AUD trace output.

Real-time profiling

SuperH Tool Selector

E200F Full Emulator 2 Suggested Starter Kit E10A-USB On-chip Evaluation chip User interface IDE 3 Series Group or Reference Platform Debug Emulator Base Unit board board (C Compiler) SH-Tiny 7125 R0K571242S000BR [2Q06] HS0005KCU01H R0E0200F1EMU00 R0E570800VKK00 R0E571250CFK00 RTA-HEWSH-1U SH-2 7146 EDK7145 / RSK7149 [TBD] HS0005KCU01H R0E0200F1EMU00 R0E570800VKK00 R0E571460CFJ00 RTA-HEWSH-1U SH-2 7086 - HS0005KCU02H 1 R0E0200F1EMU00 R0E570800VKK00 R0E570860CFK00 RTA-HEWSH-1U SH-2A 7206 MS7206SE01 HS0005KCU02H 1 R0E0200F1EMU00 R0E572060VKK00 R0E572060CFK00 RTA-HEWSH-1U SH-2A 7261 - HS0005KCU02H 1 ---RTA-HEWSH-1U SH-2 7618 MS7618ACP01 HS0005KCU01H ---RTA-HEWSH-1U SH-2 7619 MS7619SE01 HS0005KCU01H ---RTA-HEWSH-1U SH3-DSP 7712 MS7712SE01 [2Q06] HS0005KCU02H 1 ---RTA-HEWSH-1U SH3-DSP 7720 MS7720RP02 HS0005KCU02H 1 ---RTA-HEWSH-1U SH-4 7760 MS7760CP02P HS0005KCU02H 1 R0E0200F0EMU00 - - RTA-HEWSH-1U SH-4A 7780 MS7780SE03 [2Q06] HS0005KCU02H 1 R0E0200F0EMU00 - - RTA-HEWSH-1U SH-4A 7763 MS7763SE01 [3Q06] HS0005KCU02H 1 ---RTA-HEWSH-1U

NOTES: 1. Includes AUD real-time trace support and both 36-pin AUD & 14-pin H-UDI target cables. 2. E200 emulation system, can operate with the base unit alone (see website for details). 3. Five-user pack and floating network licences also available (see website for details). 23 SuperH® Development Tools

■ Third-party Development Tools

Many third-party experts offer development tools and highest performance. By embedding these supported by design services, RTOS, compilers, board- engineered solutions in systems, customers can greatly level solutions, custom firmware, and board-support reduce overall system design/debug time and packages (BSPs) to meet the needs of customers development schedule risk because the board design, developing SuperH-based products. Product-ready integration and debug, driver development, driver single-board computers (SBCs) and application-specific optimization, and driver and board testing have reference designs offered by systems integrators are already been done. As a result, customers can bring end fully developed solutions designed for the lowest cost products to market months faster.

NUCLEUS

Third-party RTOS Support

SH-1 / SH-2 SH-2A SH-3 SH-4 SH-4A ATI Nucleus x soon x x x CMX x xxx Express Logic ThreadX xxx LynxOS x Microsoft Windows®CE xxx Montavista Linux xx Open Source Linux soon soon x x x OS9 xx QNX x soon WindRiver VxWorks x x x soon

Third-party Compiler Support

SH-1 / SH-2 SH-2A SH-3 SH-4 SH-4A Altium xxx GAIO xxxx GHS xxxxsoon GNU xxxxx IAR xxx Metrowerks xxx

Third-party System Integrators

Hardware WindowsCE Linux Other Website BSquare X www.bsquare.com CalAmp X X X X www.calamp.com California Software Labs X X X www.cswl.com JJPlus X X linux.jjplus.com Logic Products Development X X www.logicpd.com Software Research Associates X www.sraoss.com Systemic Realtime Design X X X www.sysrtime.com TrygTech X www.trygtech.com SH-2 Series 24

SH-2 Series Line-up

SH-Ether Series SH-Dual SH7060 SH2-DSP Ether MAC/PHY SH-2A Series Series ROM: 256KB SH7200 RAM: 8KB Series SH7080 RAM: 32-128KB Series ROM option: 512KB SH7144 FPU Option Series SH-2 ROM: 256-512KB RAM: 16-32KB SH7606 ROM: 256KB Series

S RAM: 8KB RAM: 4KB SH7040 SH7046/7 SH7146 Series Series Series

FEATURE ROM: 256KB ROM: 256KB ROM: 256KB RAM: 4KB RAM: 12KB RAM: 8KB Available Now

SH7010 SH/Tiny NEW Series Series

ROM: 128-160KB ROM: 64-128KB In Planning RAM: 3-4KB RAM: 8KB

20MHz 50MHz 80MHz 100MHz 120-200MHz

PERFORMANCE

■ Features • Industry-standard CAN interface for networking com- munication in applications such as factory automation • Large size and high-performance on-chip memory: Up to 512KB on-chip flash memory and up to • Excellent MIPS/watt and low-power support, as well 32KB on-chip RAM as low-voltage options • Direct connection to external memory (e.g., SDRAM, • On-chip debug hardware allows low-cost software SRAM and Flash) via 8/16/32-bit external data bus debugging; no in-circuit emulator required • Devices with on-chip DSP enable accurate • Other on-chip peripherals include DMAC, DTC, SCI, current/position control. The RISC/DSP devices allow up to 149 I/O ports, etc. concurrent monitoring and controlling of a system ■ Applications • Special advanced Motor Management Timer with outputs for 6-phase PWM waveform Industrial: AC/DC drives, inverters, servos/motion (complementary/reset-synchronized) with controllers, robotics, machine tools, factory automation programmable dead-time for 3-phase motor control Consumer/Office Appliances: Air conditioners, • Special Multi-function Timer Unit 3-phase motor washers, refrigerators, DVD recorders, digital cameras, controller includes 2 quadrature encoding channels LCD projectors, multi-function printers, seismic for speed/position detection of rotor monitoring systems, etc. • MTU and MMT have error input for emergency Automotive: Power door closers, seat positioners, PWM shutdown starter/generators, air conditioners, electric power steering, etc. • Synchronized A/D converter enables precise current detection for motor control Medical: Heart-rate monitors, dental equipment, etc. 25 Up to 80MHz MCUs for cost-sensitive motor control applications

SH-2 Series Selector Guide

Package Family Series Device Number Special Features Code Flash (Kbytes) RAM (Kbytes) Vcc min Vcc max Vcc max max MHz @ Modes Down Power 8-bit timers 16-bit timers Timers Watchdog Timer PWM Motor Control A/D 10-bit resolution D/A 8-bit resolution Serial (sync/async) DTC DMA Channels External Interrupts GPIO SH-2 7046 HD64F7046F50V 256 12 4.0 5.5 50 3 - 5 1 1 12 - 2 Y - 5 54 MTU, CMT, MMT FP-80Q 7047 HD64F7047F50V 256 12 4.5 5.5 50 4 - 5 1 1 16 - 3 Y - 5 69 MTU, MMT, CAN P-100M 7144 HD6417144F50V - 8 3.0 3.6 50 3 - 5 1 1 8 - 4 Y 4 9 82 MTU, I2C, AUD FP-112B 7144 HD6417144FW50V - 8 3.0 3.6 50 3 - 5 1 1 8 - 4 Y 4 9 82 MTU, I2C, AUD FP-112B 7144 HD64F7144F50V 256 8 3.0 3.6 50 3 - 5 1 1 8 - 4 Y 4 9 82 MTU, I2C, AUD FP-112B 7144 HD64F7144FW50V 256 8 3.0 3.6 50 3 - 5 1 1 8 - 4 Y 4 9 82 MTU, I2C, AUD FP-112B 7145 HD6417145F50V - 8 3.0 3.6 50 3 - 5 1 1 8 - 4 Y 4 9 106 MTU, I2C, AUD FP-144F 7145 HD6417145FW50V - 8 3.0 3.6 50 3 - 5 1 1 8 - 4 Y 4 9 106 MTU, I2C, AUD FP-144F 7145 HD64F7145F50V 256 8 3.0 3.6 50 3 - 5 1 1 8 - 4 Y 4 9 106 MTU, I2C, AUD FP-144F 7145 HD64F7145FW50V 256 8 3.0 3.6 50 3 - 5 1 1 8 - 4 Y 4 9 106 MTU, I2C, AUD FP-144F 7146 R5F71464AN80FPV 256 8 4.0 5.5 80 4 - 11 1 - 12 - 3 Y - 5 57 MTU2, MTU2S, CMT FP-80W 7146 R5F71464AD80FPV 256 8 4.0 5.5 80 4 - 11 1 - 12 - 3 Y - 5 57 MTU2, MTU2S, CMT FP-80W 7146 R5F71494AN80FPV 256 8 4.0 5.5 80 4 - 11 1 - 12 - 3 Y - 5 75 MTU2, MTU2S, CMT FP-100U 7146 R5F71494AD80FPV 256 8 4.0 5.5 80 4 - 11 1 - 12 - 3 Y - 5 75 MTU2, MTU2S, CMT FP-100U 7080 R5F70834AN80FTV 256 16 3.0 5.5 80 4 - 11 1-8-4Y49 73MTU2, MTU2S, CMTTFP-100B 7080 R5F70834AD80FTV 256 16 3.0 5.5 80 4 - 11 1-8-4Y49 73MTU2, MTU2S, CMTTFP-100B 7080 R5F70844AN80FPV 256 16 3.0 5.5 80 4 - 11 1-8-4Y49 84 MTU2, MTU2S, I2C FP-112E 7080 R5F70844AD80FPV 256 16 3.0 5.5 80 4 - 11 1-8-4Y49 84 MTU2, MTU2S, I2C FP-112E 7080 R5F70854AN80FPV 256 16 3.0 5.5 80 4 - 11 1-8-4Y49108 MTU2, MTU2S, I2C FP-144L 7080 R5F70854AD80FPV 256 16 3.0 5.5 80 4 - 11 1-8-4Y49108 MTU2, MTU2S, I2C FP-144L 7080 R5F70855AN80FPV 512 32 3.0 5.5 80 4 - 11 1-8-4Y49108 MTU2, MTU2S, I2C FP-144L 7080 R5F70855AD80FPV 512 32 3.0 5.5 80 4 - 11 1-8-4Y49108 MTU2, MTU2S, I2C FP-144L 7080 R5F70865AN80FPV 512 32 3.0 5.5 80 4 - 11 1 - 16 - 4 Y 4 9 134 MTU2, MTU2S, I2C FP-176E 7080 R5F70865AD80FPV 512 32 3.0 5.5 80 4 - 11 1 - 16 - 4 Y 4 9 134 MTU2, MTU2S, I2C FP-176E 7606 HD6417606BG100V - 4 3.0 3.6 100 3 - - 1 - - - 3 - - 9 78 HIF, CMT, SDRAM, PCMCIA BP-176V 7606 HD6417606BGN100V - 4 3.0 3.6 100 3 - - 1 - - - 3 - - 9 78 HIF, CMT, SDRAM, PCMCIA BP-176V 7606 HD6417606BGW100V - 4 3.0 3.6 100 3 - - 1 - - - 3 - - 9 78 HIF, CMT, SDRAM, PCMCIA BP-176V SH-Tiny 7125 R5F71242D50FPV 64 8 4.5 5.5 50 4 - 8 1-8-3-- 4 31 MTU2, CMT FP-48F 7125 R5F71242N50FPV 64 8 4.5 5.5 50 4 - 8 1-8-3-- 4 31 MTU2, CMT FP-48F 7125 R5F71243D50FPV 128 8 4.5 5.5 50 4 - 8 1-8-3-- 4 31 MTU2, CMT FP-48F 7125 R5F71243N50FPV 128 8 4.5 5.5 50 4 - 8 1-8-3-- 4 31 MTU2, CMT FP-48F 7125 R5F71252D50FAV 64 8 4.5 5.5 50 4 - 8 1-8-3-- 5 45 MTU2, CMT FP-64A 7125 R5F71252N50FAV 64 8 4.5 5.5 50 4 - 8 1-8-3-- 5 45 MTU2, CMT FP-64A 7125 R5F71252D50FPV 64 8 4.5 5.5 50 4 - 8 1-8-3-- 5 45 MTU2, CMT FP-64K 7125 R5F71252N50FPV 64 8 4.5 5.5 50 4 - 8 1-8-3-- 5 45 MTU2, CMT FP-64K 7125 R5F71253D50FAV 128 8 4.5 5.5 50 4 - 8 1-8-3-- 5 45 MTU2, CMT FP-64A 7125 R5F71253N50FAV 128 8 4.5 5.5 50 4 - 8 1-8-3-- 5 45 MTU2, CMT FP-64A 7125 R5F71253D50FPV 128 8 4.5 5.5 50 4 - 8 1-8-3-- 5 45 MTU2, CMT FP-64K 7125 R5F71253N50FPV 128 8 4.5 5.5 50 4 - 8 1-8-3-- 5 45 MTU2, CMT FP-64K SH2-DSP 7065 HD64F7065SV 256 8 3.0 3.6 60 4 - 6 1 - 8 2 3 - 4 9 118 MMT, DSP, CMT, TPU FP-176 SH-2A 7206 R5S72060W200FPV - 128 1.15 1.35 200 3 - 911824-81779MTU2, MTU2S, CMT, SDRAMFP-176CV 7211 R5F72115D160FPV 512 32 3.0 3.6 160 3 - 2 19824-8 - - MTU2, MTU2S, CMT, I2CFP-144L 7261 R5S72611P80FPV - 32 1.15 1.35 80 3 2 6 1 - 8 2 8 - 8 - - MTU2, CAN, I2C, FPU, SDRAM FP-176EV 7261 R5S72611C120FPV - 32 1.15 1.35 120 3 2 6 1 - 8 2 8 - 8 - - MTU2, CAN, I2C, FPU, SDRAM FP-176EV 7261 R5S72611P80FPV - 32 1.15 1.35 80 3 2 6 1 - 8 2 8 - 8 - - MTU2, CAN, I2C, FPU, SDRAM FP-176EV 7261 R5S72611C120FPV - 32 1.15 1.35 120 3 2 6 1 - 8 2 8 - 8 - - MTU2, CAN, I2C, FPU, SDRAM FP-176EV SH-Ether Series 26

SH-Ether Series Line-up

SH-4 Ether 400MHz

SH7763 266MHz

GbE, IPsec, PCI SH-4A USB, LCDC Dual-Gbit SH3-DSP Ethernet Dual-Channel R4J7710ABG Controller Ethernet Controller 200MHz SH7710 8MB SDRAM SH7710 4MB Flash 200MHz

Ether, IPsec SH7712 200MHz

Ether

S SH-2 Ether SH7650

FEATURE SH-2 Single-channel 133MHz Ether, FIFO 512B Ethernet Controller SH7619 PCI, DTCP 125MHz MPEG TS-I/F Ether + PHY SH7618 FIFO 512B 100MHz SH7616 Ether, FIFO 512B 62.5MHz SH7615 Ether, FIFO 2KB 62.5MHz

Ether, FIFO 512B

Available Now

NEW

In Planning

PERFORMANCE 27 SH-Ether CPUs for networking and OA applications

■ Features ■ Applications

• Built-in 10/100Mbps or 10/100/1000Mbps Network/Communication: Ethernet MAC with up to 8KB FIFO for better Network printers, network security cameras, networked network efficiency and dedicated DMAC for factory automation terminals, routers, cable modems, efficient data transfer home gateways, etc. • Easy connectivity via built-in peripherals such as Office Appliances: USB function controllers Printers, scanners, postage meters • Large-size on-chip memory: Up to 16KB RAM and Consumer: 32/32KB instruction/data cache for higher performance DVD recorders, HDD recorders, digital home • Widely supported by third parties and Renesas; appliances product-ready platforms, schematics, software and middleware available • On-chip hardware support for debugging • Clever power management – Three power-down modes for lower power consumption – Clock gearing enables clock to be changed on the fly – On-chip hardware support for debugging • Highly-integrated RISC CPUs in compact micro-BGA and QFP packages reduce board space and system cost

SH-Ether Series Selector Guide

Package Family Series Device Number Special Features Code RAM (Kbytes) Vcc min Vcc max Vcc max max MHz @ Timer Watchdog A/D 10-bit resolution D/A 8-bit resolution Serial (Sync/Async) SSU (SPI Compatible) DMA Channels External Interrupts GPIO SH2-DSP 7616 HD6417616ARFV 8 3.0 3.6 62.5 1 - - 5 - 2 5 30 DSP, Ether MAC, SDRAM FP-208C SH-2 7618 HD6417618RBG100V 4 3.0 3.6 100 1 - - 3 - - 9 78 HIF, Ether MAC, PCMCIA, SDRAM BP-176V 7618 HD6417618RBGN100V 4 3.0 3.6 100 1 - - 3 - - 9 78 HIF, Ether MAC, PCMCIA, SDRAM BP-176V 7618 HD6417618RBGW100V 4 3.0 3.6 100 1 - - 3 - - 9 78 HIF, Ether MAC, PCMCIA, SDRAM BP-176V 7619 R4S76190B125BGV 16 3.0 3.6 125 1 - -4-4978 HIF, Ether MAC PHY, PCMCIA, SDRAM BP-176V 7619 R4S76190N125BGV 16 3.0 3.6 125 1 - -4-4978 HIF, Ether MAC PHY, PCMCIA, SDRAM BP-176V 7619 R4S76190W125BGV 16 3.0 3.6 125 1 - -4-4978 HIF, Ether MAC PHY, PCMCIA, SDRAM BP-176V 7650 R4S76500B133BG 16 3.0 3.6 133 1 - -2-4- - HIF, Ether MAC, PCI, PCMCIA, SDRAM BP-336V SH3-DSP 7710 HD6417710BPV 16 1.4 1.6 200 1 - -4-6724 Dual Ether MAC, IPsec, PCMCIA, SDRAM BP-256HV 7710 HD6417710FV 16 1.4 1.6 200 1 - -4-6724 Dual Ether MAC, IPsec, PCMCIA, SDRAM FP-256GV 7710 R4J7710ABGV 8K 1.4 1.6 200 1 - -4-6724Dual Ether MAC, IPsec, PCMCIA, 8MB SDRAM, 4MB Flash BP-340V 7712 HD6417712BPV 16 1.4 1.6 200 1 - -4-6724 Dual Ether MAC, PCMCIA, SDRAM BP-256HV 7712 HD6417712FV 16 1.4 1.6 200 1 - -4-6724 Dual Ether MAC, PCMCIA, SDRAM FP-256GV SH-4A 7763 R5S77630Y-266BGV 161.1 1.3 266 1423365 118 Dual GbE MAC, USB Host & Function, LCDC, PCI, FPU, DDR BP-449V SH-3 and SH-4 Series 28

SH-3 and SH-4 Series Line-up

SH-4A 800-1000MHz SH7751R SH7780 200/240MHz Series PCI 400-600MHz SH-4A Ether SH7750R 400MHz 200/240MHz SH7763 266MHz

SH-4 Gb-Ether, PCI SH7760 USB, LCDC, IPsec 200MHz

USB Host SH-4A LCDC

SH3-DSP SH7710 Series 200MHz

Ether 2ch IPsec option

S SH7720 SH7729R 133MHz 100/133/167/200MHz USB (H/F), LCDC FEATURE MMC I/F, I2C

SH7727 SH7641 100/160MHz 100MHz

USB2F

SH-3

SH7709S 100/133/167/200MHz SH7705 133MHz Available Now

SH7706 USB Function Low power NEW 133MHz In Planning

PERFORMANCE 29 Up to 200MHz, excellent MIPS/$ for very integrated applications

■ SH-3 Features

• Highest MIPS/watt and MIPS/$ ratings in the industry • SH3-DSP devices have on-chip DSP for applications • Easy connectivity with built-in peripherals such as USB such as signal processing, video streaming, etc. host/function controllers • On-chip hardware support for debugging • Highly-integrated RISC MPUs in compact micro-BGA • Clever power management for longer battery life and QFP packages reduce board space and system cost – Ultra-low power appliances, boasting a current • Flexible bus structure: Four-bus structure allows simul- consumption of just 1mA per MHz (e.g., SH7705) taneous DMA, CPU and DSP access – Three power-down modes are available to lower power consumption • Widely supported by third parties and Renesas; prod- uct-ready platforms, schematics, software and middle- – Clock gearing enables clock to be changed on the fly ware available

■ Applications

Office Appliances: Laser printers, video printers, Network/Communication: Low-cost Internet appliances, scanners, bar code scanners, fax machines, TV electronic dictionaries, personal organizers, Handheld conference systems PCs, PDAs, point-of-sale terminals, IP telephony, mobile phones, multimedia terminals, portable information Industrial: Postage meters, industrial control terminals, devices, web cameras, routers, cable modems medical equipment Consumer: Digital still cameras, digital video cameras, Web phones

SH-3 Series Selector Guide

Package

Family Series Device Number RAM (Kbytes) Vcc min Vcc max Vcc max max MHz @ Timer Watchdog A/D 10-bit resolution D/A 8-bit resolution Serial (Sync/Async) DMA Channels External Interrupts GPIO Special Features Code SH-3 7705 HD6417705BP100BV - 1.4 1.6 100 1 4 - 2 4 7 106 CMT, TPU, USB Function, SDRAM TBP-208AV 7705 HD6417705BP133BV - 1.4 1.6 133 1 4 - 2 4 7 106 CMT, TPU, USB Function, SDRAM TBP-208AV 7705 HD6417705F100BV - 1.4 1.6 100 1 4 - 2 4 7 106 CMT, TPU, USB Function, SDRAM FP-208CV 7705 HD6417705F133BV - 1.4 1.6 133 1 4 - 2 4 7 106 CMT, TPU, USB Function, SDRAM FP-208CV 7706 HD6417706BP133V - 1.75 2.05 133 14224767 TPU, PCMCIA, SDRAM TBP-208AV 7706 HD6417706F133V - 1.75 2.05 133 14224767 TPU, PCMCIA, SDRAM FP-176CV 7706 HD6417706F120DV - 1.75 2.05 120 14224767 TPU, PCMCIA, SDRAM FP-176CV 7709S HD6417709SBP100BV - 1.55 1.95 100 182342396 TPU, PCMCIA, SDRAM BP-240AV 7709S HD6417709SF100BV - 1.55 1.95 100 182342396 TPU, PCMCIA, SDRAM FP-208CV 7709S HD6417709SBP133BV - 1.65 2.05 133 182342396 TPU, PCMCIA, SDRAM BP-240AV 7709S HD6417709SF133BV - 1.65 2.05 133 182342396 TPU, PCMCIA, SDRAM FP-208CV 7709S HD6417709SBP167BV - 1.75 2.05 167 182342396 TPU, PCMCIA, SDRAM BP-240AV 7709S HD6417709SF167BV - 1.75 2.05 167 182342396 TPU, PCMCIA, SDRAM FP-208CV 7709S HD6417709SHF200BV - 1.85 2.15 200 182342396 TPU, PCMCIA, SDRAM FP-208EV SH3-DSP 7641 HD6417641BP100 144 1.71 1.89 100 1 8 - 3 4 9 144 CMT, USB Function, I2C, SDRAM BP-256V 7720 HD6417720BP133CV 16 1.4 1.6 133 142267117TMU, USB Host & Function, LCDC, PCMCIA, MMC, SSL, SDRAM BP-256HV 7720 HD6417720BL133CV 16 1.4 1.6 133 142267117TMU, USB Host & Function, LCDC, PCMCIA, MMC, SSL, SDRAM BP-256CV 7729R HD6417729RBP100B 16 1.55 1.95 100 18234796 TMU, PCMCIA, SDRAM BP-240A 7729R HD6417729RF100BV 16 1.55 1.95 100 18234796 TMU, PCMCIA, SDRAM FP-208CV 7729R HD6417729RBP133BV 16 1.65 2.05 133 182347 96 TMU, PCMCIA, SDRAM BP-240AV 7729R HD6417729RF133BV 16 1.65 2.05 133 18234796 TMU, PCMCIA, SDRAM FP-208CV 7729R HD6417729RBP167B 16 1.75 2.05 167 18234796 TMU, PCMCIA, SDRAM BP-240A 7729R HD6417729RF167BV 16 1.75 2.05 167 18234796 TMU, PCMCIA, SDRAM FP-208CV 7729R HD6417729RHF200BV 16 1.85 2.15 200 18234796 TMU, PCMCIA, SDRAM FP-208EV SH-3 and SH-4 Series (continued) 30

■ SH-4 Features ■ Applications

• Two-way superscalar support – • Optimized cache architecture: double Networking/ top performance per MHz size and 4-way associative to reduce Communications: – Harvard architecture, RISC and FPU cache misses and minimize latency Handheld PCs, instructions executed in parallel • Highly-integrated peripherals on point-of-sale devices, – Up to 600MHz 32-bit RISC engine @ device: e.g., SH7763 includes FPU, Internet appliances, 1080 MIPS (32-bit registers, USB Host and function, built-in VoIP/webphones, 16-bit instructions) LCD controller, Gigabit Ethernet home gateways, routers – Can access four instructions per controller, PCI, etc. Computing: memory access (64-bit external bus) • The SH-4 and SH-4A cores High-performance • Integrated IEEE754-compliant feature an advanced power-saving multimedia terminals, FPU co-processor mechanism with built-in digital TVs, set-top boxes, – High-speed single-precision and power-down modes game machines, fingerprint double-precision operations • On-chip hardware support for detectors, passport readers – Can process an impressive seven debugging million polygons per MHz • Widely supported by third parties • Includes DSP/SIMD instruction – and Renesas; product-ready true multimedia acceleration platforms, schematics, software – FIPR can perform 4-way dot and middleware available product in a single cycle • Investment protection: upward – FTRV can perform a 4-cycle, compatibility and long-term product 4 x 4 matrix-vector multiplication. supply and support • Direct connection to SDRAM, DDR-SDRAM, SRAM, Burst ROM, PCMCIA

SH-4 Series Selector Guide

Package

Family Series Device Number RAM (Kbytes) Vcc min Vcc max Vcc max max MHz @ Timer Watchdog A/D 10-bit resolution D/A 8-bit resolution Serial (Sync/Async) DMA Channels External Interrupts GPIO Special Features Code SH-4 7750R HD6417750RBP200V - 1.35 1.6 200 1 - - 2 8 5 20 TMU, PCMCIA, FPU, SDRAM BP-256AV 7750R HD6417750RF200V - 1.35 1.6 200 1 - - 2 8 5 20 TMU, PCMCIA, FPU, SDRAM FP-208EV 7750R HD6417750RBP240V - 1.4 1.6 240 1 - - 2 8 5 20 TMU, PCMCIA, FPU, SDRAM BP-256AV 7750R HD6417750RF240V - 1.4 1.6 240 1 - - 2 8 5 20 TMU, PCMCIA, FPU, SDRAM FP-208EV 7751R HD6417751RBP200V - 1.35 1.6 200 1 - - 2 8 5 32 TMU, PCMCIA, FPU, PCI, SDRAM BP-256AV 7751R HD6417751RF200V - 1.35 1.6 200 1 - - 2 8 5 32 TMU, PCMCIA, FPU, PCI, SDRAM FP-256GV 7751R HD6417751RBP240V - 1.4 1.6 240 1 - - 2 8 5 32 TMU, PCMCIA, FPU, PCI, SDRAM BP-256AV 7751R HD6417751RF240V - 1.4 1.6 240 1 - - 2 8 5 32 TMU, PCMCIA, FPU, PCI, SDRAM FP-256GV 7760 HD6417760BP200ADV - 1.4 1.6 200 1 4 - 3 8 9 70 USB Host, LCDC, AC97, SSI, PCMCIA, FPU, CAN, SDRAM BP-256FV 7760 HD6417760BL200AV - 1.4 1.6 200 1 4 - 3 8 9 70 USB Host, LCDC, AC97, SSI, PCMCIA, FPU, CAN, SDRAM BP-256BV 7760 HD6417760BL200ADV - 1.4 1.6 200 1 4 - 3 8 9 70 USB Host, LCDC, AC97, SSI, PCMCIA, FPU, CAN, SDRAM BP-256BV SH-4A 7780 R8A77800NBGV 48 1.15 1.35 400 1 - - 2 12 9 83 CMT, TMU, NAND, PCMCIA, MMC, DDR, PCI, FPU, AC97, SSI BP-449V 7780 R8A77800DBGV 48 1.15 1.35 400 1 - - 2 12 9 83 CMT, TMU, NAND, PCMCIA, MMC, DDR, PCI, FPU, AC97, SSI BP-449V 7781 R8A77810NBGV 48 1.15 1.35 400 1 - - 2 12 9 83 CMT, TMU, NAND, PCMCIA, MMC, DDR, PCI, FPU, AC97, SSI, IPsec BP-449V 7781 R8A77810HBGV 48 1.15 1.35 400 1 - - 2 12 9 83 CMT, TMU, NAND, PCMCIA, MMC, DDR, PCI, FPU, AC97, SSI, IPsec BP-449V 7785 R8A77850ANBGV 1521.0 1.2 600 1 - - 6 12 9 - TMU, NAND, PCMCIA, MMC, DDR2, PCI, FPU, AC97, SSI, LCDC FC-BGA436 31 Application Examples

■ Application Example 1: AC Servo System Configuration Using SH7206

• Achieves maximum CPU performance by having programs resident in internal RAM • On-chip cache improves performance of externally installed programs • Abundant functions such as three-phase PWM output timer, 10-bit A/D converter, and more

CPU at 200 MHz Sub-MCUs SH7206 etc. PWM A/D output For various control SCI input bus 128-KB EEPROM RAM PWM output etc. I2C bus A/D input Abundant Communications 8, 16, 32 bits External bus at 66 MHz functions Motor control Possible to control On-chip 4-ch SCIF 2 types of motors and on-chip 1-ch I2C USB ASIC ROM When expanding to 32 bits, one type Directly connectable to various memory types of motor can be High-speed execution is enabled by storing controlled. the boot program to the on-chip RAM

■ Application Example 2: Multimedia Gateway Configuration using SH7763

Internet LCD Audio MPEG2 Panel Codec Decoder

Broadband Gb Ethernet LCD Sound Stream Modem Controller Interfaces Interface

USB USB PC Gb Ethernet Host Peripheral

USB USB Wi-Fi PCI SH7763 Function Host - PDA

PCMCIA PCMCIA CF I/F CF Card

DDR-SDRAM Local Bus MMC MMC Controller Controller SD I/F SD Card

DDR-SDRAM Flash Appendices 32

■ Appendix A-1: Architecture of SH-2 and SH2-DSP Series

= SH-DSP only s s s (CDB) (CAB) s bu s s ss bu bu ss ss s s s bu ss Internal X addre

Internal addre SH-2 Internal Y addre 16-bit internal Y data bu ROM Buffer 16-bit internal X data bu

32-bit internal data bu CPU 64-bit internal ROM bu Peripheral addre 16-bit peripheral data bu Interrupt Serial controller communication interface DSP Motor management timer X-RAM Timer pulse unit

Y-RAM Compare-match timer

A/D converter User break controller

D/A converter

Bus state Direct controller Watchdog timer memory access

controller (IDB) s (IAB)

s Operating mode Clock pulse controller bu generator ss

I/O ports Internal addre 32-bit internal data bu

External bus interface

LEGEND: CPG Clock Programmable Generator MTU Multifunction Timer Pulse Unit TIM 2 8-Bit Timer 2 ADC Analog to Digital Converter CMT Compare Match Timer HCAN Car Automotive Network DAC Digital to Analog Converter PWM Pulse Width Modulater HCAN2 Car Automotive Network TPU 16-Bit Timer Pulse Unit ATU Advanced Timer Unit SCI Serial Communication Interface WDT WatchDog Timer ATU-II Advanced Timer Unit-II UDI User Debug Interface MMT Motor Management Timer APC Advanced Pulse Controller DTC Data Transfer Controller PFC Pin Function Controller 33 Architecture Diagrams

■ Appendix A-2: Architecture of SH-2A Series

SH-2A CPU core

CPU instruction fetch bus (F bus) CPU bus (C bus) CPU memory access bus (M bus) (I clock)

Instruction Operand User break Cache On-chip RAM cache memory cache memory controller UBCTRG output

controller 128 Kbytes Port 8 Kbytes 8 Kbytes (UBC)

Internal bus (I bus) (B clock)

Bus state Direct memory DREQ input Peripheral controller access controller DACK output

bus controller Port (BSC) (DMAC) TEND output

Port

External bus input/output External bus width mode input Peripheral bus (P clock)

Multi-function Pin function Interrupt Multi-function Port output Compare Clock pulse timer pulse timer pulse controller unit 2 enable 2 match timer I/O ports generator (CPG) controller unit 2 (PFC) (INTC) (MTU2) subset (POE2) (CMT) (MTU2S)

Port Port Port Port Port Port

General input/output EXTAL input, RES input, Timer pulse Timer pulse POE input XTAL output, MRES input, input/output input/output CKIO input/output, NMI input, Clock mode input IRQ input, PINT input, IRQOUT output

Serial High-performance 2 Power-down I C bus communication Watchdog user debugging D/A converter A/D converter mode interface 3 interface timer interface (DAC) (ADC) control (IIC3) with FIFO (WDT) (H-UDI) (SCIF)

Port Port Port Port Port Port

JTAG input/output Analog output Analog input, I2C bus Serial input/output WDTOVF output ADTRG input input/output Appendices 34

■ Appendix A-3: Architecture of SH-3, SH3-DSP, and SH-4 Series

SH-3, SH3-DSP Architecture SH-4 Architecture

= SH3-DSP only = SH7751R only

SH-4 CPU UBC FPU

SH-3 ) XYCNT s

CPU ) s s s Lower 32-bit data tore) truction Y bu X bu tore) s s s (data) truction ss (in DSP s

XYMEM ss s 64-bit data ( 32-bit data ( 32-bit data (load) UBC Upper 32-bit data 32-bit addre L bu 32-bit data (in MMU 32-bit addre AUD SCI TLB Cache and 1 I cache O cache s ITLBTLB UTLB (16 kB) (8 kB) controller

CCN TMU Peripheral bu CACHE ss s RTC CPG I bu 32-bit data 32-bit data

ASERAM 29-bit addre

BSC INTC s bu

H-UDI IrDA ss s BSC SCI DMAC (SCIF) SCIF INTC 2 DMAC s Peripheral addre RTC ADC Peripheral data bu CPG/WDT

CMT Peripheral bu DAC TMU

External bus I/O port PCIC interface

(PCI)DMAC LEGEND: ss ADC: A/D converter ss ASERAM: ASE memory AUD: Advanced user debugger 32-bit data Addre 32-bit data Addre 32-bit data BSC: Bus state controller CACHE: Cache memory External (SH) bus CCN: Cache memory controller interface CMT: Compare match timer CPG/WDT: Clock pulse generator/watchdog timer 32-bit CPU: Central processing unit 26-bit 32-bit SH bus data PCI DAC: D/A converter SH bus (64-bit for SH7751) address/ address DMAC: Direct memory access controller data DSP: Digital signal processor INTC: Interrupt controller LEGEND: IrDA: Serial communicatiion interface (with IRDA) BSC: Bus state controller MMU: Memory management unit CPG: Clock pulse generator RTC: Realtime clock DMAC: Direct memory access controller SCI: Serial communication interface FPU: Floating-point unit (with smart card interface) INTC: Interrupt controller SCIF: Serial communication interface (with FIFO) ITLB: Instruction TLB (translation lookaside buffer) TLB: Translation look-aside buffer UTLB: Unified TLB (translation lookaside buffer) TMU: Timer unit RTC: Realtime clock UBC: User break controller SCI: Serial communication interface UDI: User debugging interface SCIF: Serial communication interface with FIFO TMU: Timer unit XYCNT: X/Y memory controller UBC: User break controller XYMEM: X/Y memory PCIC: PCI bus controller 35 Architecture Diagrams

■ Appendix A-4: Architecture of SH-4A Series

LBSC (External bus)

CPU I-cache DDRIF (External bus)

MMU PCIC (External bus) s s

FPU s O-cache DMAC TMU truction bu

UBC s SuperHyway SCIF Operand bu Operand uperHyway bu uperHyway In RAM

S channel 0

HPB I/O AUD LRAM HSPI multiplexed INTC FLCTL

SH-4A core s SuperHyway router SCIF LEGEND: channel 1 I/O AUD: Advanced user debugger multiplexed CMT: Timer/counter CPG bu Peripheral MMCIF CPG: Clock pulse generator CPU: Central processing unit DDRIF: DDR-SDRAM interface WDT SIOF DMAC: Direct memory access controller FLCTL: NAND flash memory controller FPU: Floating-point unit RTC HAC I/O GPIO: General purpose I/O multiplexed HAC: Audio codec CMT SSI HPB: Peripheral bus bridge HSPI: Serial protocol interface H-UDI: User debugging interface H-UDI GPIO I-Cache: Instruction cache INTC: Interrupt controller LBSC: Local bus state controller SCIF: Serial communication interface with FIFO LRAM: L memory SIOF: Serial I/O with FIFO MMCIF: Multimedia card interface SSI: Serial sound interface MMU: Memory management unit SuperHyway RAM: SuperHyway memory O-Cache: Operand (data) cache TMU: Timer unit PCIC: PCI controller UBC: User break controller RTC: Realtime clock WDT: Watchdog timer Appendices 36

■ Appendix B-1: Nomenclature of SuperH Part Numbers (1 of 2)

HD64 X #### X X # X V

Digital CMOS Process

On-chip memory type: 1: ROMless 3: Masked ROM 7: OTP 8: EEPROM F: Flash N: EEPROM Multi-Chip Package

Specific Series: 7XXX: SuperH

Package (one- or two-letter code)

Temperature Range: Blank: -20 to +75°C (standard temp) W/I: -40 to +85°C (industrial temp) J: -40 to +85°C (extended reliability) L: -40 to +105°C K: -40 to +125°C

Maximum Speed (MHz)

Product Version (default is blank)

V: RoHS-compliant Package Appendices

■ Appendix B-2: Nomenclature of SuperH Part Numbers (2 of 2)

R X X 7### X X # X V

Renesas LSI

4: Existing Series 5: New Series 8: SoC

3: Mask ROM F: Flash J: SiP S: ROMless/Standard Mask ROM

Device Number

0: ROMless 2: 64KB ROM 3: Mask ROM 4: 256KB ROM 5: 512KB ROM

N: Normal Temperature D: Industrial Temperature

Maximum Speed (MHz)

Package Type

V: RoHS Compliant Package Appendices

■ Appendix C: Abbreviations

AC97 AC ‘97 Audio Interface MAC Multiply Accumulate Instruction AUD Advanced User Debug MMC Multimedia Card BSC Bus State Controller MMT Motor Management Timer CAN Controller Area Network MTU Multi-function Timer pulse Unit CMT Compare Match Timer MTU2 Multi-function Timer pulse Unit 2 DDR Double Data Rate SDRAM Controller MTU2S Multi-function Timer pulse Unit 2S DDR2 Double Data Rate 2 SDRAM Controller NAND NAND Flash Controller DMA Direct Memory Access PCI PCI Bus Interface DSP Digital Signal Processor PCMCIA PCMCIA Bus Interface DTC Data Transfer Controller SDRAM SDRAM Controller Ether MAC Ethernet Media Access Control SSI Serial Sound Interface Ether PHY Ethernet Physical Layer SSL Secure Socket Layer FPU Floating Point Unit STIF Stream Interface GbE MAC Gigabit Ethernet Media Access Control TMU Timer Unit HIF Host Interface TPU Timer Pulse Unit

I2C Inter IC Bus USB Function Universal Serial Bus Function Interface IPsec Internet Protocol Security USB Host Universal Serial Bus Host Interface LCDC LCD Controller

■ Appendix D: Package Specifications

Previous Pin Nominal Body Lead Pitch Thickness Type Renesas Code Code Count Dimensions (mm) (mm) (mm) QFP Quad Flat Package PRQP0064GB-A FP-64A 64 14 x 14 0.8 3.05 LQFP Low-profile QFP PLQP0048JA-A FP-48F 48 10 x 10 0.65 1.70 PLQP0064KB-A FP-64K 64 10 x 10 0.5 1.70 PLQP0080JA-A FP-80W 80 14 x 14 0.65 1.70 PLQP0100KB-A FP-100U 100 14 x 14 0.50 1.70 PLQP0112JA-A FP-112E 112 20 x 20 0.65 1.70 PLQP0144KA-A FP-144L 144 20 x 20 0.50 1.70 PLQP0176KC-A FP-176 176 24 x 24 0.50 1.70 PLQP0176KD-A FP-176CV 176 24 x 24 0.50 1.70 PLQP0176KB-A FP-176E 176 24 x 24 0.50 1.70 PLQP0176KB-A FP-176EV 176 24 x 24 0.50 1.70 PLQP0208KA-A FP-208C 208 28 x 28 0.80 1.70 PLQP0208KA-A FP-208CV 208 28 x 28 0.80 1.70 HQFP Heat-sinked QFP PRQP0208KE-B FP-208EV 208 28 x 28 0.50 3.65 PRQP0256LA-B FP-256GV 256 28 x 28 0.40 3.95 TQFP Thin QFP PTQP0100KA-A TFP-100B 100 14 x 14 0.50 1.20 BGA Ball Grid Array PLBG0256GB-A BP-256BV 256 17 x 17 0.80 1.70 PRBG0256DE-A BP-256V 256 27 x 27 1.27 2.50 FBGA Fine-Pitch BGA PRBG0449GA-A BP-449V 449 21 x 21 0.80 2.00 LFBGA Low-Profile FBGA PLBG0176GA-A BP-176V 176 13 x 13 0.80 1.40 PLBG0240JA-A BP-240A 240 13 x 13 0.65 1.40 PLBG0240JA-A BP-240AV 240 13 x 13 0.65 1.40 PLBG0256KA-A BP-256CV 256 11 x 11 0.50 1.40 PLBG0256FA-A BP-256FV 256 21 x 21 1.00 1.70 PLBG0256GA-A BP-256HV 256 17 x 17 0.80 1.40 TBD BP-336V 336 17 x 17 0.80 1.40 TBD BP-340V 340 17 x 17 0.80 1.70 Renesas Interactive — Your Online Environment for Semiconductor Device Research, Evaluation and Application

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Flip open for Appendices. © 2006 Renesas Technology America, Inc. Renesas Technology America, Inc. is a wholly owned subsidiary of Renesas Technology Corporation. SuperH is a trademark of Renesas Technology Corporation. All other trademarks are the property of their respective holders. The information supplied by Renesas Technology America, Inc. is believed to be accurate and reliable, but in no event shall Renesas Technology America, Inc. be liable for any damages whatsoever arising out of the use or inability to use the information or any errors that may appear in this publication. The information is provided as is without any warranties of any kind, either express or implied. Renesas Technology America, Inc. reserves the right, without notice, to make changes to the information or to the design and specifications of its hardware and/or software products. Products subject to availability. Printed in U.S.A.

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