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Embedded-DSP Superh Family and Its Applications

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Embedded-DSP Superh Family and Its Applications Hitachi Review Vol. 47 (1998), No. 4 121 Embedded-DSP SuperH Family and Its Applications Toru Baji ABSTRACT: Recently sales have grown markedly in the field of mobile Hiroshi Takeyama communication terminals such as global system for mobile communications (GSM), personal digital cellular telecommunication system (PDC), personal Tetsuya Nakagawa handyphone system (PHS), and in digital consumer equipment such as car navigation systems and digital still cameras. These systems are configured with a CPU and a general-purpose digital signal processor (DSP). The CPU executes communication protocol control and system control; the general-purpose DSP performs signal processing such as speech compression and image processing. For mobile communication systems and digital consumer products for the near future, integration of the CPU and DSP is required to achieve a low-price, small-size, low-power consumption system. Hitachi, Ltd., has introduced a new-generation microcomputer SH- DSP into this market. The SH-DSP consists of a SuperH-RISC (reduced instruction set computer) microcomputer and a high-performance DSP engine. With the SH-DSP, Hitachi has enhanced its product line for a new wave of applications, such as digital still cameras, mobile communication terminals, and speech processing systems. INTRODUCTION applications are mobile communication terminals, THE SH-DSP incorporates a 32-bit RISC microcom- digital consumer equipment, and multimedia systems. puter, which is completely upward compatible with One example of digital consumer equipment is the the SH microcomputers (SH-1 and SH-2), and includes digital still camera. Hitachi has developed a digital high performance DSP functions. Examples of target camera system based on the SH-DSP (Fig. 1). SH-DSP HD6437410F Digital still camera system CPU+ DSP board Control AMP CODEC Shutter SH-DSP RS-232C PCMCIA 3.3,5 V slot IrDA PC FLASH cards ROM MP-VRAM DRAM (512 kbyte) × 4 (1 Mbyte) (16 Mbyte) Lens Camera board Y CDS Camera Y/C CCD ADC DAC AGC TG DSP mix C Monitor (TV) Video driver Sub controller CPU: central processing unit DSP: digital signal processor PCMCIA: Personal Computer Memory Card International Association IrDA: Infrared Data Association ROM: read only memory MP-VRAM: multiport video RAM CCD: charge coupled device CDS: correlated double sampling AGC: automatic gain control ADC: analog-to-digital converter TG: timing generator DAC: digital-to-analog converter Y: illuminance signal C: chrominance signal Fig. 1—SH-DSP Used in a Digital Still Camera System. SH-DSP is a compact reduced instruction set computer (RISC) microcomputer with an embedded high-performance DSP engine. Digital still cameras using this processor are also able to perform speech compression and decompression efficiently. Embedded-DSP SuperH Family and Its Applications 122 3-bus configuration SuperH RISC engine Parallel execution of 1 program Can generate three addresses for DSP fetch and 2 data accesses instructions or execute RISC insructions. Address buses DSP engine SHARED IAB General-purpose-register file, single-cycle external memories YAB 16 × 32-bit multiply-accumulate, and other DSP functions Directly connected XAB general-purpose to DRAM, EDO, register file RAM, flash, and Data register file RISC RISC (burst) ROM or or × DSP (X) 8 32 bit and DSP (V) ALU 2 × 40 bit memory memory SHARED Interrupt controller, Auxilliary ALU Control Flexible memory debugger, and clock signal Multiplier Can be accessed by both pulse generator Decoder RISC and DSP instructions. 16/32-bit prefetch ALU/Burrel shifter SHARED Peripheral module XDB YDB IDB Data buses : Enhanced functions in SH-DSP EDO: extended data output RAM: random access memory ALU: arithmetical and logical unit IAB: I address bus YAB: Y address bus XAB: X address bus IDB: I data bus YDB: Y data bus XDB: X data bus Fig. 2—SH Block Diagram and Features. SH-DSP incorporates a high-performance DSP engine and employs a 3-bus configuration for the DSP enhancement of the conventional SuperH RISC microcomputer. There are big advantages in chip size reduction and lower power consumption because memories and peripheral functions can be shared compared with a discrete CPU and DSP integrated in one chip. In the SH-DSP, in addition to CPU operation, the between CPU and DSP reduces the number of circuits RISC engine is also used to generate three addresses on the LSI. and control the DSP when executing DSP instructions. This mode of operation achieves high DSP SH-DSP PERFORMANCE performance with minimum increase in circuitry. A Fig. 3 shows a comparison of CPU and DSP 3-bus configuration is employed that enables parallel performance in each processor. SuperH has higher DSP execution of two data accesses and one program fetch performance than general RISC microcomputers for DSP operation. Fig. 2 shows the SH-DSP block because it has a 3-cycle multiply-accumulator. diagram and features. A general-purpose DSP, on the other hand, has the Besides 1-cycle multiply-accumulate, a total of 10 highest DSP performance because of its 1-cycle general-purpose data registers are incorporated in the multiply-accumulate and 3-bus configuration, but has DSP engine. For making the most of these hardware lower CPU performance because it does not support resources, 32-bit pseudo VLIW (very long instruction 8-/16-/32-bit data access and does not include so many word) instructions are introduced. versatile CPU instructions. Furthermore, functions such as zero-overhead repeat Unlike the SuperH alone or a general-purpose DSP, loop and module addressing, which are indispensable the SH-DSP has higher performance for both the DSP for DSPs, are also included. Memories and peripherals and CPU because it is perfectly upward compatible can be shared between the DSP and CPU. This enables with the SH-1 and SH-2 and executes all of the general- the use of SuperH DRAM (dynamic random access purpose DSP’s functions. CPU performance of the SH- memory) direct interface to the DSP, a function which DSP is 60 million instructions per second (MIPS), is not seen in other DSPs. This is especially effective which is the same as that of a 60-MHz SH-DSP. The for digital still cameras, which require large-capacity DSP performance is 120 million operations per second DRAM image memory. Also sharing of various circuits (MOPS), which is almost the same as that of a general- Hitachi Review Vol. 47 (1998), No. 4 123 purpose DSP. The actual benchmark test shows that has been developed. Still image compression by Joint SH-DSP performance is at the top level among general- Photographic Experts Group (JPEG) processing was purpose processors 1). executed in just 0.55 second for a Video Graphics Array (VGA) full-size image (640 × 480 pixels, Y : U : V = SH-DSP DIGITAL STILL CAMERA SYSTEM 4 : 2 : 2). For a quarter-VGA (QVGA) size image, A digital still camera system based on the SH-DSP four to seven frames can be processed in one second 200 MOPS SH-DSP 120 100 60 RISC + DSP SH-3 40 General-purpose DSP SH-2 20 SH-1 DSP performance 10 × 2 RISC + 3 multiply-accumulate × 2/3 5 RISC MOPS = MIPS Fig. 3—DSP and CPU Performance 3 of SH-DSP. MOPS = MIPS 2 SuperH shows higher DSP 1 2 3 5 10 20 30 60 100 200 performance due to a 3-cycle CPU performance multiply-accumulator. The SH-DSP MOPS (million operations per second) is a DSP performance measure, which shows the number of has 60-MIPS CPU performance as operations such as multiplications executed in one second. well as 120-MOPS DSP MIPS (million instructions per second) is a CPU performance measure, which shows the number of performance. Dhrystone benchmark instructions executed in one second. Control System controller board (DC-DS1) AMP Speaker CODEC Microphone Shutter SH-DSP 115 kbps HD64E7410 RS-232C 68 PCMCIA slot 3.3, 5 V 3.3 V IrDA 115 kbps PCMCIA ATA PC • Flash ATA card (75 Mbyte) • Compact flash card (15 Mbyte) × 16, 1 wait × 32, 0 wait × 32, 0 wait ROM MP-VRAM DRAM HN27C4096 HM538253 HB56TW433 (512 kbyte) (× 4 Mbyte) (16 Mbyte) 5 V 5 V 3.3 V Camera board (MV-DS10) Digital I/F (Y, R-Y/B-Y) Lens HA118184F HD49319F HD49811TFA Y Y/C CCD CDS/AGC ADC DAC DSP mix TG C Monitor (TV) V. Driver Microcontroller H8/300 series ATA: advanced technology attachment bus ADC: analog-to-digital converter Y: Illuminance signal C: chrominance signal Fig. 4—Block Diagram of an SH-DSP Digital Still Camera System. This digital still camera system consists of the camera board (MV-DS10) which captures the still image and converts it to a digital signal, and the system controller board (DC-DS1) that performs both image and speech compression/decompression and system control. The entire camera system can be controlled by a single SH-DSP. Embedded-DSP SuperH Family and Its Applications 124 in parallel with speech compression/decompression JPEG processing time 0.51.0 1.5 (s) processing. SH-1 Encode 1.30 20 MHz Decode 1.60 Digital Still Camera System Concept In a digital still camera system using SH-DSP, SH-2 0.83 28 MHz functions are shared between the DSP engine and the 1.02 compact RISC microcomputer. The DSP engine SH-3 0.35 executes digital signal processing, still image and 60 MHz 0.42 Operating conditions Picture size (QVGA):320×240 speech compression; the compact RISC microcomputer SH-DSP 0.13 Y:Cr:Cb=4:2:2, 24-bit full color executes the disc operating system (DOS) file 60 MHz 0.15 Compression ratio:1/10 management, communications, and camera system control. Although a dedicated LSI is also required for Code size 510 15 (kbyte) a conventional digital still camera systems, only the Com Decode SH-DSP and its software are required to configure a SH JPEG library (1) Encode (8) (6) 15 H-1,2,3 Work digital still camera system using an SH-DSP.
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