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Low Power Asynchronous Digital Signal Processing

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Low Power Asynchronous Digital Signal Processing LOW POWER ASYNCHRONOUS DIGITAL SIGNAL PROCESSING A thesis submitted to the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Science & Engineering October 2000 Michael John George Lewis Department of Computer Science 1 Contents Chapter 1: Introduction ....................................................................................14 Digital Signal Processing ...............................................................................15 Evolution of digital signal processors ....................................................17 Architectural features of modern DSPs .........................................................19 High performance multiplier circuits .....................................................20 Memory architecture ..............................................................................21 Data address generation .........................................................................21 Loop management ..................................................................................23 Numerical precision, overflows and rounding .......................................24 Architecture of the GSM Mobile Phone System ...........................................25 Channel equalization ..............................................................................28 Error correction and Viterbi decoding ...................................................29 Speech transcoding ................................................................................31 Half-rate and enhanced full-rate coding .............................................33 Summary of processing for GSM baseband functions ...........................34 Evolution towards 3rd generation systems ............................................35 Digital signal processing in 3G systems ........................................................36 Structure of thesis ..........................................................................................37 Research contribution ....................................................................................37 Chapter 2: Design for low power ......................................................................39 Sources of power consumption ......................................................................39 Dynamic power dissipation ....................................................................39 Leakage power dissipation .....................................................................40 Power reduction techniques ...........................................................................41 Reducing the supply voltage ..................................................................41 Architecture-driven voltage scaling ...................................................43 Adaptive supply voltage scaling ........................................................45 Reducing the voltage swing ...............................................................45 Adiabatic switching ............................................................................46 Reducing switched capacitance .............................................................47 Feature size scaling ............................................................................49 Transistor sizing .................................................................................50 Layout optimization ...........................................................................51 SOI CMOS technology ......................................................................51 Reducing switching activity ...................................................................52 Reducing unwanted activity ...............................................................53 Choice of number representation and signal encoding ......................54 Evaluation of number representations for DSP arithmetic .................58 Algorithmic transformations ..............................................................63 Reducing memory traffic ...................................................................63 Asynchronous design .....................................................................................65 Asynchronous circuit styles ...................................................................66 Delay insensitive design .....................................................................66 Bundled-data design ...........................................................................70 2 Asynchronous handshake circuits ......................................................71 Latch controllers for low power asynchronous circuits .........................73 Advantages of asynchronous design ......................................................78 Elimination of clock distribution network .........................................78 Automatic idle-mode ..........................................................................79 Average case computation .................................................................80 Reduced electromagnetic interference ...............................................80 Modularity of design ..........................................................................81 Disadvantages compared to clocked designs .........................................82 Lack of tool support ...........................................................................82 Reduced testability .............................................................................82 Chapter 3: CADRE: A new DSP architecture ................................................84 Specifications .................................................................................................84 Sources of power consumption ......................................................................84 Processor structure .........................................................................................85 Choice of parallel architecture ...............................................................86 FIR Filter algorithm ...........................................................................86 Fast Fourier Transform .......................................................................89 Choice of number representation .......................................................90 Supplying instructions to the functional units ........................................90 Supplying data to the functional units ....................................................92 Instruction buffering ..............................................................................95 Instruction encoding and execution control ...................................................96 Interrupt support ...................................................................................101 DSP pipeline structure .........................................................................102 Summary of design techniques ....................................................................104 Chapter 4: Design flow ....................................................................................106 Design style .................................................................................................106 High-level behavioural modelling ...............................................................106 Modelling environment ........................................................................106 Datapath model design .........................................................................108 Control model design ...........................................................................108 Combined model design .......................................................................111 Integration of simulation and design environment ..............................114 Circuit design ...............................................................................................114 Assembler design .........................................................................................114 Chapter 5: Instruction fetch and the instruction buffer ...............................118 Instruction fetch unit ....................................................................................118 Controller operation .............................................................................119 PC incrementer design .........................................................................120 Instruction buffer design ..............................................................................123 Word-slice FIFO structure ...................................................................125 Looping FIFO design ...........................................................................127 Write and read token passing ...........................................................128 Overall system design ..........................................................................130 PC latch scheme ...................................................................................131 Control datapath design .......................................................................132 3 Evaluation of design .............................................................................133 Results ..................................................................................................134 Loop counter performance ...............................................................134 Chapter 6: Instruction decode and index register substitution ...................137 Instruction decoding ....................................................................................137
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