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The Digital Signal Processor Derby SEMICONDUCTORS The newest breeds trade off speed, energy consumption, and cost to vie for The an ever bigger piece of the action Digital Signal Processor BY JENNIFER EYRE Derby Berkeley Design Technology Inc. pplications that use digital signal-processing purpose processors typically lack these specialized features and chips are flourishing, buoyed by increasing per- are not as efficient at executing DSP algorithms. formance and falling prices. Concurrently, the For any processor, the faster its clock rate or the greater the market has expanded enormously, to an esti- amount of work performed in each clock cycle, the faster it can mated US $6 billion in 2000. Vendors abound. complete DSP tasks. Higher levels of parallelism, meaning the AMany newcomers have entered the market, while established ability to perform multiple operations at the same time, have companies compete for market share by creating ever more a direct effect on a processor’s speed, assuming that its clock novel, efficient, and higher-performing architectures. The rate does not decrease commensurately. The combination of range of digital signal-processing (DSP) architectures available more parallelism and faster clock speeds has increased the is unprecedented. speed of DSP processors since their commercial introduction In addition to expanding competition among DSP proces- in the early 1980s. A high-end DSP processor available in sor vendors, a new threat is coming from general-purpose 2000 from Texas Instruments Inc., Dallas, for example, is processors with DSP enhancements. So, DSP vendors have roughly 250 times as fast as the fastest processor the company begun to adapt their architectures to stave off the outsiders. offered in 1982. Even so, some of the newest DSP applications, What follows provides a framework for understanding the such as third-generation wireless, are straining the capabilities recent developments in DSP processor architectures, includ- of current DSP processors [see figure, p. 64]. ing the increasing interchange of architectural techniques As processors pick up speed, applications evolve to exploit between DSPs and general-purpose processors. all the extra horsepower—and then some. Thus, DSP proces- sor designers continue to develop techniques for increasing Performance through parallelism parallelism and clock speeds. Digital signal processors are key components of many con- June 2001 June • sumer, communications, medical, and industrial products. Their How many instructions per clock cycle? specialized hardware and instructions make them efficient at exe- A key differentiator among processor architectures is how cuting the mathematical computations used in processing dig- many instructions are issued and executed per clock cycle. The ital signals. For example, since DSP often involves repetitive number of instructions executed in parallel, and the amount multiplications, DSP processors have fast multiplier hardware, of work accomplished by each, directly affect the processor’s IEEE SPECTRUM explicit multiply instructions, and multiple bus connections to level of parallelism, which in turn affects the processor’s speed. 62 memory to retrieve multiple data operands at once. General- Historically, DSP processors have issued only one instruction per clock cycle, and have achieved parallelism by packing sev- Two advantages of this approach are increased speed and eral operations into each instruction. A typical DSP processor compilability, which come at the cost of added architectural instruction might perform a multiply-accumulate (MAC) oper- complexity. Speeds increase because the use of simple instruc- ation, load two new data operands into registers, and incre- tions simplifies instruction decoding and execution, allowing ment the address pointers. multi-issue processors to execute at much higher clock rates In contrast, high-performance general-purpose processors, (often two to three times higher) than single-issue DSP proces- such as the Intel Pentium and Motorola PowerPC, usually sors while maintaining similar (or higher) levels of parallel achieve parallelism by issuing and executing several fairly operation. The technique has given such general-purpose simple instructions per clock cycle. Why the difference? processors as the Pentium and the PowerPC clock speeds far DSP processors were originally designed for applications higher than those seen on today’s DSP processors. sensitive to cost, power consumption, and size. They relied on This style of instruction set enables more efficient com- single-issue architectures, which are typically simpler to imple- pilers, since compilers are able to better “understand” and ment than architectures that issue more than one instruction use simple, single-operation instructions. Moreover, imple- per clock. Therefore, they consume less die area and power. menting a multi-issue architecture can be attractive because it can be used as a tech- How wide an instruction? Since the amount of memory a processor requires to store its software affects its cost, size, and power consumption, DSP processor instruction sets are designed with the goal of enabling highly compact programs. Thus, conventional DSP processors use a relatively short instruction word—typically 16 or 24 bits long—to encode each multi-operation instruction. While this approach makes efficient use of program memory, it has several drawbacks. First, packing multiple parallel operations into a single, narrow instruction word means that the instruction sets tend to be highly constrained, filled with special cases and restrictions. There are often restrictions on which registers can be used with which operations, and on which operations can be combined in a single instruction. There are simply not enough bits in the instruction word to support many different combinations of registers and operations. These complex instruction sets make it difficult to create efficient high-level language compilers for the processors. In reaction, most people who program con- ventional DSP processors (unlike those who program high- nique for upgrading the performance of an existing archi- performance central processing units, or CPUs) sacrifice the tecture while maintaining binary-level software compatibil- portability and ease of programming offered by high-level lan- ity. For example, the Pentium executes software written for the guages and instead work in assembly language, that being the earlier 486 architecture, but issues and executes two instruc- only way to harness the processor’s capabilities effectively. tions per cycle (where possible) rather than one. Accordingly, This has become a significant disadvantage for conventional customers can upgrade the performance of their systems with- DSP processors, particularly as competition from more out having to recompile their software (a critical consideration compiler-friendly general-purpose processors has grown. for PC users, who typically lack access to the source code for An alternative to packing lots of operations in a single their application software). instruction is to use a technique common among general-pur- Multi-issue processors typically require more instructions IEEE SPECTRUM pose processors: include only one operation per instruction, (and hence more program memory) to implement a given and then issue a group of instructions in parallel. This is called section of software. Since each instruction is simpler than a multi-issue approach. So, for example, the earlier multi-oper- those of conventional DSP processors, more instructions are ation instruction might be split into five single-operation required to perform the same amount of work. In addition, • instructions: a MAC, two moves, and two address pointer multi-issue architectures often use wider instructions than 2001 June updates. Each individual instruction is much simpler, but by conventional DSPs. The increased width (for instance, 32 bits executing them at the same time, the processor provides the rather than 16) primarily serves to avoid imposing limitations same level of parallelism as does a single-issue processor that on, say, which registers can be used with which operations. 63 DAVEY LIU DAVEY executes all of the operations as part of a single instruction. (The wider the instruction word, the more distinct instructions SEMICONDUCTORS can be specified, thus allowing the instruction set to support Analog Devices Inc., Norwood, Mass. The only mainstream more combinations of operations and registers.) The removal superscalar DSP processor currently available is the LSI40xx of such limitations makes it much easier to create an efficient from LSI Logic Inc., Milpitas, Calif. compiler for the processor. In a VLIW architecture, either the assembly-language pro- However, the less memory used by a processor, the better, grammer or the compiler must specify which instructions will because memory affects its die size, cost, and power con- be executed in parallel. In contrast, in a superscalar architecture, sumption. Hence, the fact that multi-issue architectures often special hardware within the processor determines which instruc- require more program memory counts against them in many tions will be executed in parallel, based on the resources—such DSP applications. as registers—that are available, data dependencies as instructions That said, where performance is the ultimate driver, DSP are executed, and other considerations. This is determined when architects have been willing to accept the penalties of a multi- the program is
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