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L02 — Asics Vs Fplds Integrated Circuits (ICs) Some Applications of ICs ! Integrated Circuit (IC) = “chip” ! Home ! General-purpose microprocessor, CPU ! Appliances, intercom, telephones, security system, garage door opener, ! Application-Specific Instruction Set answering machines, fax machines, Processor (ASIP), e.g. video processor or home computers, TVs, cable TV tuner, digital signal processor VCR, camcorder, video games, cellular ! Application-Specific IC (ASIC) or Field- phones, sewing machines, cameras, Programmable Logic Device (FPLD) exercise equipment, microwave oven ! IC package contains: ! Office ! silicon chip = “die” ! Telephones, computers, security system, fax machines, copier, printers, pagers ! Pins, wires between die and pins ! Automobile ! Trip computer, air bags, ABS, instrumentation, security system, transmission control, entertainment system, climate control, keyless entry, Figure from Application-Specific Integrated Circuits, Smith, Addison-Wesley, 1997 cellular phone, GPS ! Package may have heat sink attached List from Hardware/Software Codesign, Giovanni De Micheli, 1996. 1 Spring 2006, Lecture 02 2 Spring 2006, Lecture 02 Integrated Circuits (ICs) Integrated Circuits (ICs) (cont.) (cont.) ! A modern digital system is built out of a ! Classification, cont. collection of integrated circuits (ICs), ! VLSI (very large…) >10,000 each of which is made up of gates ! Modern microprocessors – 8086 = 29,000 ! ICs are typically classified based on the – i386DX = 275,000 number of gates they contain – i486DX = 1,200,000 ! SSI (small scale integration) < 10 – Pentium = 3,100,000 – Pentium Pro = 5,500,000 ! 4 nand gates – Pentium II = 7,500,000 ! 4 or gates ! 4 and gates – Pentium M = 77,000,000 (half are for the L2 cache) ! MSI (medium…) 10-100 ! Application-Specific Instruction Set ! simple adders, counters Processor (ASIP), e.g. video processor or ! multiplexers digital signal processor ! flip-flops ! Application-Specific IC (ASIC) ! LSI (large…) 100-10,000 – Generally cost-effective only when produced in high volume (hundreds of ! Interface devices thousands of part) ! Calculators – Also used when very high performance is ! Digital clocks needed ! Simple microprocessors ! Field-Programmable Logic Device (FPLD) – Very common, 80,000 new design starts in 2003 (vs. 4,000 for ASICs) 3 Spring 2006, Lecture 02 4 Spring 2006, Lecture 02 ASICs vs. FPLDs Full-Custom ASICs ! IC contains a chip (“die”) cut from a wafer ! Design — engineer does detailed design of logic cells, circuit, and layout ! Transistors, wires, etc. are built up on the chip in a series of layers (10-50 layers) ! Time-consuming and costly! ! A mask is used to define the components ! Primarily used if no pre-designed of a layer as they are applied to the chip modules are available (e.g., new or highly specialized circuit), or when very high ! ASICs vs. FPLDs (+ pizza equivalent) performance is needed ! Full-custom ASIC ! Fabrication — design is sent to a ! Prepare pizza sauce, toppings, dough from scratch; takes a long time fabrication facility (a “fab”), where it is etched onto wafers, each wafer ! Standard-cell-based ASIC containing 100!s of chips ! Choose from limited selection of toppings and dough; less work but still slow ! Wafers used to be 8”, now 13”, discs ! Gate-array-based ASIC ! Fabrication is expensive (huge fixed ! Add canned toppings to pre-cooked startup cost), and takes a couple of crusts; save some time and cost months ! Field-programmable logic device ! Most chips fabricated using CMOS ! Frozen pizza — limited selection, trivial to techniques (details later in the course) cook, very cheap 5 Spring 2006, Lecture 02 6 Spring 2006, Lecture 02 Standard-Cell-Based ASICs Standard-Cell-Based ASICs (cont.) ! Design — chip is built from pre-defined ! Cells fit together like bricks in a wall — modules called standard cells rows of (variable-width) cells ! Standard cells are built by someone else ! Most interconnect goes in channels using full-custom design techniques between rows, though some cells may be designated as feedthroughs (vias) ! Save time, money, and risk by using a between rows well-designed, verified cell library ! But — have to pay for the cell library ! Most metal layers provide interconnect ! Others provide power and ground ! Also use larger cells (microprocessors, etc.) called mega cells (sometimes cores) ! Fabrication remains costly and slow Figure from Application-Specific Integrated Circuits, Smith, Addison-Wesley, 1997 Figure from Application-Specific Integrated Circuits, Smith, Addison-Wesley, 1997 7 Spring 2006, Lecture 02 8 Spring 2006, Lecture 02 Gate-Array-Based ASICs Programmable Logic Devices (PLDs) ! Designed using pre-defined modules ! Standard ICs, available in standard configurations, sold in high volume ! Fabrication time reduced — transistors ! No customized cells or masks, just a are placed in a fixed pattern on the chip single large block of programmable ! Interconnect is defined by designer and interconnect fabricated using a custom mask ! Can be configured / programmed to create a specialized device ! Chip is partially fabricated (cells, power, etc. added) and then stockpiled ! Fast turn-around time ! When design is received for fabrication, ! Examples the remaining metal layers are added ! Mask-programmable ROM — ! Cheaper — everyone shares cost of programmed when ordered producing high volume of initial chip ! Programmable ROM — programmed ! Quick turn-around — days, couple weeks electrically, erased electrically or using ultraviolet light, all by customer ! Variations: ! PAL, PLA — 2-level sum-of-products ! Channeled gate arrays and/or array, programmed electrically by customer (blowing fuses in array) ! Channelless gate arrays 9 Spring 2006, Lecture 02 10 Spring 2006, Lecture 02 Field Programmable Logic Devices ASICs vs. FPLDs (FPLDs) ! Known by a variety of names: Characteristic ASIC FPLD ! "Field-Programmable Gate Array (FPGA) Time to market Long Short High volume unit cost Low High ! "Field-Programmable Logic Device (FPLD) NRE High None ! Complex Programmable Logic Device Flexibility after None High (CPLD) manufacturing Performance Very High Medium ! Similar to PLDs, but more complex Density Very High Medium ! Core is a regular array of programmable Power consumption Low High logic cells, each of which contains Minimum order High None combinational and sequential logic quantity ! Programmable interconnect surrounds Design flow Very High Medium the logic cells complexity Complexity of testing High Low ! Some method provided for programming the base logic cells and the interconnect Turnaround time Months Hours Source: Jack Horgan, EDA Weekly, Monday 8/9/04 ! Designed using pre-defined modules, with “fabrication” turn-around on the order of minutes 11 Spring 2006, Lecture 02 12 Spring 2006, Lecture 02.
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