Purdue University Purdue e-Pubs ECE Technical Reports Electrical and Computer Engineering 3-1-1992 RlSC & DSP Advanced Microprocessor System Design; Sample Projects, Fall 1991 John E. Fredine Purdue University, School of Electrical Engineering Dennis L. Goeckel Purdue University, School of Electrical Engineering David G. Meyer Purdue University, School of Electrical Engineering Stuart E. Sailer Purdue University, School of Electrical Engineering Glenn E. Schmottlach Purdue University, School of Electrical Engineering Follow this and additional works at: http://docs.lib.purdue.edu/ecetr Fredine, John E.; Goeckel, Dennis L.; Meyer, David G.; Sailer, Stuart E.; and Schmottlach, Glenn E., "RlSC & DSP Advanced Microprocessor System Design; Sample Projects, Fall 1991" (1992). ECE Technical Reports. Paper 302. http://docs.lib.purdue.edu/ecetr/302 This document has been made available through Purdue e-Pubs, a service of the Purdue University Libraries. Please contact [email protected] for additional information. RISC & DSP Advanced Microprocessor System Design Sample Projects, Fall 1991 John E. Fredine Dennis L. Goeckel David G. Meyer Stuart E. Sailer Glenn E. Schmottlach TR-EE 92- 11 March 1992 School of Electrical Engineering Purdue University West Lafayette, Indiana 47907 RlSC & DSP Advanced Microprocessor System Design Sample Projects, Fall 1991 John E. Fredine Dennis L. Goeckel David G. Meyer Stuart E. Sailer Glenn E. Schrnottlach School of Electrical Engineering Purdue University West Lafayette, Indiana 47907 Table of Contents Abstract .................................................................................................................... .ii Overview of Design Project I .....................................................................................iii Overview of Design Project II ....................................................................................v A RlSC Core Based on an Intel 860XP .....................................................................1 A RlSC Core Based on a Motorola 88000. ............................................................I04 A DSP Core Based on a Motorola 56000.. ............................................................1 63 A DSP Core Based on a Texas Instruments TMS320C30. .................................. ..212 Abstract RlSC & DSP Microprocessor System Design (EE 595M) provides students with an overview of reduced instruction set (RISC) microprocessors and digital signal process- ing (DSP) microprocessors, with emphasis on incorporating these devices in general purpose and embedded system designs, respectively. The first half of the course emphasizes design considerations for RlSC microprocessor based computer systems; a half-semester design project focuses on design principles that could be utilized in a general-purpose computer system (e.g., an engineering workstation). The second half of the course emphasizes design considerations for DSP microprocessor based com- puter systems; a half-semester design project focuses on analog I10 interfacing tech- niques and use of these devices for embedded applications (e.g., spectrum analyzer, digital equalizer). The primary objective of the course is to introduce students to the design of com- puter systems using advanced architecture microprocessors along with their related support chips as building blocks. Other objectives include providing students with experience developing complex PLD-based state machine design, performing detailed analysis of bus signal timing, performing analysis of gate electrical characteristics, and using modern programmable logic devices (e.g., EPLDs) to implement interfacelglue logic. Design experience is gained through a two comprehensive half-semester pro- jects. Technical communication skills are honed through a videotaped project summary presentation. During the Fall 1991 semester, 11 project teams completed two designs each based on a variety of RlSC and DSP advanced architecture microprocessors, including: lntel i860XR and i860XP RlSC machines, Motorola 88000 RlSC machines, Cypress SPARC RlSC machines, Motorola 56001 DSP machines, Analog Devices ADSP-21020 DSP machines, and Texas lnstruments 320625 and 320630 DSP machines. Con- tained in this Technical Report are four sample design projects, based on the following processors: (1) a RlSC design based on the lntel i860XP, (2) a RlSC design based on the Motorola 88000, (3) a DSP design based on the Motorola 56001, and (4) a DSP design based on the Texas lnstruments 320C30. Also included are specifications for the RlSC and DSP design projects. Purpose: To provide the opportunity for students to develop advanced microprocessor hardware system design skills as well as to develop technical presentation skills. Description: The basic requirement is to design the CPUIFPUICACH EIRAMIROM core for a general purpose computing platform based on an advanced architecture RlSC microprocessor (any RlSC microprocessor may be used, regardless of whether or not it is specifically discussed in class). Your design should include the following: a minimum of 4M bytes dynamic RAM, a minimum of 256K bytes bootstrap EPROM, a minimum of 32K bytes of cache memory, and floating point support (may be integrated with CPU). Fast programmable logic devices (PALS or EPLDs) should be used for address decod- ing, wait state generation, interrupt control, etc. Projects are to be done in teams of two students. Project Report: The typewritten project writeup should be clear, concise, and well- organized. In addition, the report submitted should be spiral bound. Included in this report should be the overall design rationale, a narrative describing system operation along with a system block diagram, and detailed design documentation. The design documentation, worth halfthe project grade, should include the following: a a complete address map of memory devices. a a complete set of timing diagrams for all memory devices (not copied from data books, but actual ones that you derive based on the propagation delays of the particu- lar devices used in your design) - note that the burden of proof that your design is ,free of timing problems and race conditions should be evident in your documentation (rather than buried somewhere in it). a a complete parts list, including all ICs, decoupling capacitors, pullup resistors, etc. a a series of deta.iled logical (not "chip pin") wiring diagrams, drawn with a CAD tool or, if done by hand, drawn with pencil on light-griddedpaper. a an estimate of "worst case" current consumption. a an estimate of board real estate consumption. a data sheets for a.ll components (including the CPU) you have selected. Organization: Listed below is a suggested breakdownlorganization of the project report. Use tabs or colored sheets to divide the report into sections. Note that the page lengths suggested are not "absolute." Secn 1.0 Introduction, design features, and design overview (including a block diagram). This section should be the equivalent of about 2-3 (double-spaced) typewritten pages. Secn 2.0 Design rationale - why a given design philosophy was chosen over other possibili- ties, why you chose to implement your design with a particular set of parts over other possibilities (in particular, why you chose a given CPU), tradeoffs which motivated these choices. This section should be the equivalent of 3-4 (double-space) typewrit- ten pages. Secn 3.0 Design narrative - a reasonably detailed description of how your circuit works. The functionality of each PLD should also be described. This section should be the equivalent of 6-8 (double-space) typewritten pages. Secn 4.0 Summary - what you learned from your design (a worthwhile experience or not?), things you would do differently if you had time for a "second iteration," suggestions/motivation for future work. This section should be the equivalent of 1-2 (double-space) typewritten pages. Secn 5.0 Design documentation (contents described previously); N pages, where N is large. Grading Criteria: The grade you receive on your design project will be based on the criteria listed below: CRITERION SCORE MPY. Introduction, system overview, block diagram 0 1 2 3 4 56 7 8 9 10 x2 Design rationale (choice of components) 012345678910 x3 Design narrative (how each module works) 012345678910 x5 Summary/conclusions/future work 012345678910 x2 Complete schematic 012345678910 x6 Timing diagrams 012345678910 x4 Address map 012345678910 xl Current consumption estimate 012345678910 xl Board real estate estimate 012345678910 xl Signal glossary 012345678910 xl Complete parts list 012345678910 xl Neatness, clarity, organization 01 2345678910 xl Efficiencyleleganceof design 012345678910 xl Degree of difficulty 012345678910 xl OVERVIEW OF DESIGN PROJECT II Purpose: To provide the opportunity for students to develop DSP microprocessor hardware system design skills as well as to develop technical presentation skills. Descrlptlon: The basic requirement is to design the hardware core for an application. specific computing platform based on a 24- or 32-bit DSP microprocessor (fixed- or floating-point) with sufficient bandwidth to process two 20 KHz channels of digital audio (e.g., a graphic equalizer application). Your design should include the following: a minimum of 8K bytes zero-wait-state static RAM, a minimum of 64K bytes zero-wait- state EPROM, two 16-bit AID converters with anti-aliasing (low-pass) filters, and two 16-bit DIA converters with anti-image (low-pass) filters. Fast programmable logic dev- ices (PALS or EPLDs) should