Ronics APRIL 28, 1988
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
Validated Products List, 1995 No. 3: Programming Languages, Database
NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 QC 100 NIST .056 NO. 5693 1995 NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 (Supersedes April 1995 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary TECHNOLOGY ADMINISTRATION Mary L. Good, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Arati Prabhakar, Director FOREWORD The Validated Products List (VPL) identifies information technology products that have been tested for conformance to Federal Information Processing Standards (FIPS) in accordance with Computer Systems Laboratory (CSL) conformance testing procedures, and have a current validation certificate or registered test report. The VPL also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The VPL includes computer language processors for programming languages COBOL, Fortran, Ada, Pascal, C, M[UMPS], and database language SQL; computer graphic implementations for GKS, COM, PHIGS, and Raster Graphics; operating system implementations for POSIX; Open Systems Interconnection implementations; and computer security implementations for DES, MAC and Key Management. -
Emerging Technologies Multi/Parallel Processing
Emerging Technologies Multi/Parallel Processing Mary C. Kulas New Computing Structures Strategic Relations Group December 1987 For Internal Use Only Copyright @ 1987 by Digital Equipment Corporation. Printed in U.S.A. The information contained herein is confidential and proprietary. It is the property of Digital Equipment Corporation and shall not be reproduced or' copied in whole or in part without written permission. This is an unpublished work protected under the Federal copyright laws. The following are trademarks of Digital Equipment Corporation, Maynard, MA 01754. DECpage LN03 This report was produced by Educational Services with DECpage and the LN03 laser printer. Contents Acknowledgments. 1 Abstract. .. 3 Executive Summary. .. 5 I. Analysis . .. 7 A. The Players . .. 9 1. Number and Status . .. 9 2. Funding. .. 10 3. Strategic Alliances. .. 11 4. Sales. .. 13 a. Revenue/Units Installed . .. 13 h. European Sales. .. 14 B. The Product. .. 15 1. CPUs. .. 15 2. Chip . .. 15 3. Bus. .. 15 4. Vector Processing . .. 16 5. Operating System . .. 16 6. Languages. .. 17 7. Third-Party Applications . .. 18 8. Pricing. .. 18 C. ~BM and Other Major Computer Companies. .. 19 D. Why Success? Why Failure? . .. 21 E. Future Directions. .. 25 II. Company/Product Profiles. .. 27 A. Multi/Parallel Processors . .. 29 1. Alliant . .. 31 2. Astronautics. .. 35 3. Concurrent . .. 37 4. Cydrome. .. 41 5. Eastman Kodak. .. 45 6. Elxsi . .. 47 Contents iii 7. Encore ............... 51 8. Flexible . ... 55 9. Floating Point Systems - M64line ................... 59 10. International Parallel ........................... 61 11. Loral .................................... 63 12. Masscomp ................................. 65 13. Meiko .................................... 67 14. Multiflow. ~ ................................ 69 15. Sequent................................... 71 B. Massively Parallel . 75 1. Ametek.................................... 77 2. Bolt Beranek & Newman Advanced Computers ........... -
Programming Languages, Database Language SQL, Graphics, GOSIP
b fl ^ b 2 5 I AH1Q3 NISTIR 4951 (Supersedes NISTIR 4871) VALIDATED PRODUCTS LIST 1992 No. 4 PROGRAMMING LANGUAGES DATABASE LANGUAGE SQL GRAPHICS Judy B. Kailey GOSIP Editor POSIX COMPUTER SECURITY U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 100 . U56 4951 1992 NIST (Supersedes NISTIR 4871) VALIDATED PRODUCTS LIST 1992 No. 4 PROGRAMMING LANGUAGES DATABASE LANGUAGE SQL GRAPHICS Judy B. Kailey GOSIP Editor POSIX COMPUTER SECURITY U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 October 1992 (Supersedes July 1992 issue) U.S. DEPARTMENT OF COMMERCE Barbara Hackman Franklin, Secretary TECHNOLOGY ADMINISTRATION Robert M. White, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY John W. Lyons, Director - ;,’; '^'i -; _ ^ '’>.£. ; '':k ' ' • ; <tr-f'' "i>: •v'k' I m''M - i*i^ a,)»# ' :,• 4 ie®®;'’’,' ;SJ' v: . I 'i^’i i 'OS -.! FOREWORD The Validated Products List is a collection of registers describing implementations of Federal Information Processing Standards (FTPS) that have been validated for conformance to FTPS. The Validated Products List also contains information about the organizations, test methods and procedures that support the validation programs for the FTPS identified in this document. The Validated Products List is updated quarterly. iii ' ;r,<R^v a;-' i-'r^ . /' ^'^uffoo'*^ ''vCJIt<*bjteV sdT : Jr /' i^iL'.JO 'j,-/5l ':. ;urj ->i: • ' *?> ^r:nT^^'Ad JlSid Uawfoof^ fa«Di)itbiI»V ,, ‘ isbt^u ri il .r^^iytsrH n 'V TABLE OF CONTENTS 1. -
Rlsc & DSP Advanced Microprocessor System Design
Purdue University Purdue e-Pubs ECE Technical Reports Electrical and Computer Engineering 3-1-1992 RlSC & DSP Advanced Microprocessor System Design; Sample Projects, Fall 1991 John E. Fredine Purdue University, School of Electrical Engineering Dennis L. Goeckel Purdue University, School of Electrical Engineering David G. Meyer Purdue University, School of Electrical Engineering Stuart E. Sailer Purdue University, School of Electrical Engineering Glenn E. Schmottlach Purdue University, School of Electrical Engineering Follow this and additional works at: http://docs.lib.purdue.edu/ecetr Fredine, John E.; Goeckel, Dennis L.; Meyer, David G.; Sailer, Stuart E.; and Schmottlach, Glenn E., "RlSC & DSP Advanced Microprocessor System Design; Sample Projects, Fall 1991" (1992). ECE Technical Reports. Paper 302. http://docs.lib.purdue.edu/ecetr/302 This document has been made available through Purdue e-Pubs, a service of the Purdue University Libraries. Please contact [email protected] for additional information. RISC & DSP Advanced Microprocessor System Design Sample Projects, Fall 1991 John E. Fredine Dennis L. Goeckel David G. Meyer Stuart E. Sailer Glenn E. Schmottlach TR-EE 92- 11 March 1992 School of Electrical Engineering Purdue University West Lafayette, Indiana 47907 RlSC & DSP Advanced Microprocessor System Design Sample Projects, Fall 1991 John E. Fredine Dennis L. Goeckel David G. Meyer Stuart E. Sailer Glenn E. Schrnottlach School of Electrical Engineering Purdue University West Lafayette, Indiana 47907 Table of Contents Abstract ................................................................................................................... -
SCALP: a Superscalar Asynchronous Low-Power Processor Philip Brian
SCALP: A Superscalar Asynchronous Low-Power Processor A thesis submitted to the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Science and Engineering Philip Brian Endecott Department of Computer Science 1996 Contents Contents . 2 List of Figures. 6 List of Tables . 8 Abstract. 10 Declaration . 12 Copyright and Intellectual Property Rights . 12 Acknowledgements. 13 The Author . 13 Chapter 1: SCALP: A Superscalar Asynchronous Low-Power Processor. 14 1.1 The Importance of Power Efficiency . 15 1.2 Low Power Design Techniques . 16 1.2.1 Low-Level Power Efficiency . 16 Process Technology. 16 Transistor Level Design . 17 Charge Recovery and Adiabatic Systems . 17 Logic Optimisation . 18 Supply Voltage Adjustment . 18 Parallelism. 19 Precomputation . 19 Clocking Schemes and Asynchronous Logic . 19 1.2.2 Higher-Level Power Efficiency: Microprocessors . 20 External Memory Bandwidth . 20 Cache Characteristics . 20 Datapath Arrangement . 21 1.3 Previous Low Power Processors. 21 1.4 Overview of the Thesis. 22 Chapter 2: Reducing Transitions . 24 2.1 Code Density . 24 2.1.1 Variable Length Instructions . 27 2.1.2 Register Specifiers . 29 2.1.3 Previous High Code Density Processors . 31 D16 . 31 Thumb . 32 Transputer . 32 2.2 Datapath Activity . 33 Chapter 3: Parallelism . 35 3.1 Parallelism and Power . 35 3.2 Power, Parallelism and Cost . 37 3.3 Parallelism in Special Purpose Processors . 38 3.4 Parallelism in General Purpose Processors. 39 3.5 Pipelining . 40 3.5.1 Branch Instructions. 43 3.5.2 Dependencies . 45 3.5.3 Different Pipeline Arrangements . 48 - 2 - Shorter Pipelines . -
Alphaserver 4100 System
I ALPHASERVER 4100 SYSTEM ORACLE AND SYBASE DATABASE PRODUCTS Digital FOR VLM Technical INSTRUCTION EXECUTION ON ALPHA PROCESSORS Journal • Volume 8 Number 4 1996 Editorial The Digital Technicaljournal is a refereed The following arc trademarks of Digital Jane C. Blake, Managing Editor journal published quarterly by Digital Equipment Corporation: AlphaServer, Kathleen M. Stetson, Editor Equipment Corporation, 50 Nagog Park, AlphaStation, DEC, DECnet, DIGITAL, Helen L. Patterson, Editor AK02-3/B3, Acton, MA 017 20-9843. the DIGITAL logo,VAX, VMS, and ULTIUX. Hard-copy subscriptions can be ordered by Circulation sending a check in U.S. funds (made payable AIM is a trademark of AIM Technology, Inc. Catherine M. Phillips, Administrator to Digital Equipment Corporation) to the CCT is a registered trademark of Cooper Dorothea B. Cassady, Secretary published-by address. General subscription and Chyan Te chnologies, Inc. CHALLENGE rates are $40.00 (non-U.S. $60) for four and Silicon Graphics are registered a-ademarks Production issues and $75.00 (non-U.S. $115) for and POWER CHALLENGE is a trademark Christa W. Jessica, Production Editor eight issues. University and college profes of Silicon Graphics, Inc. Compaq is a regis Anne S. Katzcff, Typographer sors and Ph.D. students in the electrical tered trademark and ProLiant is a trademark Peter R. Wo odbury, lllustrator engineering and computer science fields of Compaq Computer Corporation. HP is receive complimentary subscriptions upon a registered trademark of Hewlett-Packard Advisory Board request. DIGITAL's customers may qualifY Company. HSPICE is a registered a·ade Samuel H. Fuller, Chairman for gifi: subscriptions and are encouraged mark of Metasoftware Corporation. -
Validated Products List: Programming Languages, Database Language
NISTIR 469 (Supersedes NISTIR 4623) VALIDATED PRODUCTS LIST 1991 No. 4 Programming Languages Database Language SQL Graphics ®OSIP Judy B. Kailey POSIX Editor U.S. DEPARTMENT OF COMMERCE National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 October 1991 (Supersedes July 1991 issue) U.S. DEPARTMENT OF COMMERCE Robert A. Mosbacher, Secretary NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY John W. Lyons, Director — QC 100 .U56 NIST //4690 1991 V C.2 NISTIR 4690 (Supersedes NISTIR 4623) - ' J JF VALIDATED PRODUCTS LIST 1991 No. 4 Programming Languages Database Langucige SQL Graphics GOSIP Judy B. Kailey POSIX Editor U.S. DEPARTMENT OF COMMERCE National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 October 1991 (Supersedes July 1991 issue) U.S. DEPARTMENT OF COMMERCE Robert A. Mosbacher, Secretary NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY John W. Lyons, Director FOREWORD The Validated Products List (formerly called the Validated Processor List) is a collection of registers describing implementations of Federal Information Processing Standards (FIPS) that have been tested for conformance to FIPS. The Validated Products List also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The Validated Products List is updated quarterly. TABLE OF CONTENTS 1. INTRODUCTION 1-1 1.1 Purpose 1-1 1.2 Document Organization 1-1 1.2.1 Programming Languages 1-1 1.2.2 Database Language SQL 1-2 1.2.3 Graphics 1-2 1.2.4 GOSIP 1-2 1.2.5 POSIX 1-2 1.2.6 FIPS Conformance Testing Products 1-2 2. -
ETHERNET and the FIFTH GENERATION Gordon Bell Vice
THE ENGINEERING OF THE VAX-11 COMPUTING ENVIRONMENT The VAX-11 architectural design and implementation began in 1975 with the goals of a wide range of system sizes and different styles of use. While much of the implementation has been "as planned", various nodes (eg. computers, disk servers) and combined structures (eg. clusters) have evolved in response to the technology forces, user requirements and constraints. The future offers even more possibilities for interesting structures. ETHERNET AND THE FIFTH GENERATION Gordon Bell Vice President, Engineering Digital Equipment Corporation In the Fifth Computer Generation, a wide variety of computers will communicate with one another. No one argues about this. The concern is about how to do it and what form the computers will take. A standard communications language is the key. I believe Ethernet is this unifying key to the 5th computer generation because it interconnects all sizes and types of computers in a passive, tightly-coupled, high performance fashion, permiting the formation of local-area networks. HOW THE JAPANESE HAVE CONVERTED WORLD INDUSTRY INTO DISTRIBUTORSHIPS -- CONCERN NOW FOR SEMICONDUCTORS AND COMPUTERS Gordon Bell Vice President Digital Equipment Corporation Abstract We all must be impressed with the intense drive, technical and manufacturing ability of the Japanese. As an island with few natural resources, and only very bright, hard working people they have set about and accomplished the market domination of virtually all manufactured consumer goods and the components and processes to make these goods (i.e., vertical integration). Currently the U.S. has a dominant position in computers and semiconductors. However, there's no fundamental reason why the Japanese won't attain a basic goal to dominate these industries, given their history in other areas and helped by our governments. -
Comparative Architectures
Comparative Architectures CST Part II, 16 lectures Lent Term 2005 Ian Pratt [email protected] Course Outline 1. Comparing Implementations Developments fabrication technology • Cost, power, performance, compatibility • Benchmarking • 2. Instruction Set Architecture (ISA) Classic CISC and RISC traits • ISA evolution • 3. Microarchitecture Pipelining • Super-scalar • { static & out-of-order Multi-threading • Effects of ISA on µarchitecture and vice versa • 4. Memory System Architecture Memory Hierarchy • 5. Multi-processor systems Cache coherent and message passing • Understanding design tradeoffs 2 Reading material OHP slides, articles • Recommended Book: • John Hennessy & David Patterson, Computer Architecture: a Quantitative Approach (3rd ed.) 2002 Morgan Kaufmann MIT Open Courseware: • 6.823 Computer System Architecture, by Krste Asanovic The Web • http://bwrc.eecs.berkeley.edu/CIC/ http://www.chip-architect.com/ http://www.geek.com/procspec/procspec.htm http://www.realworldtech.com/ http://www.anandtech.com/ http://www.arstechnica.com/ http://open.specbench.org/ comp.arch News Group • 3 Further Reading and Reference M Johnson • Superscalar microprocessor design 1991 Prentice-Hall P Markstein • IA-64 and Elementary Functions 2000 Prentice-Hall A Tannenbaum, • Structured Computer Organization (2nd ed.) 1990 Prentice-Hall A Someren & C Atack, • The ARM RISC Chip, 1994 Addison-Wesley R Sites, • Alpha Architecture Reference Manual, 1992 Digital Press G Kane & J Heinrich, • MIPS RISC Architecture 1992 Prentice-Hall H Messmer, • The Indispensable -
Unit 1 Evolution of the Microprocessor Structure 1.1 Introduction
Subject Code : DEL34 Subject Title : Microprocessor Structure of the Course Content BLOCK 1 Introduction Unit 1: Evolution of Microprocessors Unit 2: Advantages of Microprocessors Unit 3: Various MPU Families (SSI, LSI, VLSI, SLSI) BLOCK 2 8085 Unit 1: Introduction Unit 2: Architecture of 8085 Unit 3: Block and Pin Diagram of 80851 and it’s functions Unit 4: BUS Details BLOCK 3 8085 Programming Unit 1: Instruction formats & Addressing Modes Unit 2: Instruction Set and It’s Cycle Unit 3: Timing Diagrams and Status Signals Unit 4: Simple Programs BLOCK 4 8085 Interfacing Unit 1: Memory mapping Unit 2: Interrupts Unit 3: I/O Peripheral Interfacing BLOCK 5 16 bit Microprocessor Unit 1: Introduction to 8086 Unit 2: Architecture of 8086 Unit 3: Block and Pin Diagram of 8086 and it’s functions Unit 4: BUS Details Books : 1. 8085 Microprocessor by Ramesh gaonkar by Penram Publishers 2. 8086 Microprocessor by Douglas hall Unit 1 Evolution of the Microprocessor Structure 1.1 Introduction 1.2 Objectives 1.3 The Breakthrough in Microprocessors 1.4 What led to the development of microprocessors? 1.5 How a microprocessor works 1.6 Archictecture of a microprocessor 1.7 Generation of microprocessors 1.8 Companies associated with microprocessors 1.9 Microprocessors Today 1.10 Where is the industry of microprocessors going? 1.11 Summary 1.12 Keywords 1.13 Exercise 1.1 Introduction The Collegiate Webster dictionary describes microprocessor as a computer processor contained on an integrated-circuit chip. In the mid-seventies, a microprocessor was defined as a central processing unit (CPU) realized on a LSI (large-scale integration) chip, operating at a clock frequency of 1 to 5 MHz and constituting an 8-bit system. -
LCSH Section Numerals
0 (Group of artists) 1c Magenta (Stamp) 2e children USE Zero (Group of artists) USE British Guiana One-Cent Magenta (Stamp) USE Twice-exceptional children 0⁰ latitude 1I (Interstellar object) 2nd Avenue (Manhattan, New York, N.Y.) USE Equator USE ʻOumuamua (Interstellar object) USE Second Avenue (Manhattan, New York, N.Y.) 0⁰ meridian 1I/2017 U1 (Interstellar object) 2nd Avenue (Seattle, Wash.) USE Prime Meridian USE ʻOumuamua (Interstellar object) USE Second Avenue (Seattle, Wash.) 0-1 Bird Dog (Reconnaissance aircraft) 1I/ʻOumuamua (Interstellar object) 2nd Avenue West (Seattle, Wash.) USE Bird Dog (Reconnaissance aircraft) USE ʻOumuamua (Interstellar object) USE Second Avenue West (Seattle, Wash.) 0th law of thermodynamics 1P/ Halley (Comet) 2nd law of thermodynamics USE Zeroth law of thermodynamics USE Halley's comet USE Second law of thermodynamics 1,000 Year Monument (Novgorod, Russia) 1st Avenue (Seattle, Wash.) 2P/Encke (Comet) USE Tysi︠a︡cheletie Rossii (Novgorod, Russia) USE First Avenue (Seattle, Wash.) USE Encke comet 1,4-beta-D-glucan cellobiohydrolase 1st Avenue West (Seattle, Wash.) 2U 2030+40 (Astronomy) USE Cellulose 1,4-beta-cellobiosidase USE First Avenue West (Seattle, Wash.) USE Cygnus X-3 1 1/2 Strutter (Military aircraft) 1st century, A.D. 3-(1-piperazino)benzotrifluoride USE Sopwith 1 1/2 Strutter (Military aircraft) USE First century, A.D. USE Trifluoromethylphenylpiperazine 1-2 Montague Place (London, England) 1st Hill Park (Seattle, Wash.) 3.1 Tongnip Sŏnŏn Kinyŏmtʻap (Seoul, Korea) BT Office buildings—England -
Thomas W. Doeppner Jr
Thomas W. Doeppner Jr. Curriculum Vitae January 2006 1. Personal Associate Professor (Research) Department of Computer Science Brown University Providence, RI 02912 [email protected] 2. Education B.S. in Computer Science (with distinction), Cornell University, May 1973 M.S.E. in Electrical Engineering, Princeton University, October 1974 M.A. in Electrical Engineering, Princeton University, June 1975 Ph.D. in Electrical Engineering and Computer Science, Princeton University, June 1977 Dissertation topic: Parallel Program Correctness Through Refinement (supervised by R. Keller) 3. Professional Appointments 1969−1976 Programmer, Atlantic Research Corporation, Alexandria, VA (summers and vacations) 1973−1976 Research and Teaching Assistantships, Princeton University 1976−1979 Assistant Professor of Computer Science and Applied Mathemat- ics, Brown University 1977−1979 Principal Software Engineer, Text Systems, Inc., Barrington, RI 1979−1981 Assistant Professor of Computer Science, Brown University 1980 Visiting Scientist, George Washington University, Washington, D.C. 1981− Associate Professor (Research), Computer Science, Brown Uni- versity Consultancies 1977−1978 Atlantic Research Corporation, Alexandria, VA 1978−1979 ONR Contract N000l4-78-C-0656, ‘‘Language Design and Eval- uation Studies’’ 1980−1984 Raytheon Corporation, Missile Systems Division, Bedford, MA 1980−1982 Raytheon Corporation, Submarine Signal Division, Portsmouth, RI 1980−1981 Summagraphics Corporation, Bridgeport, CT 1981−1982 Exxon Research and Engineering Co., Florham