SCALP: a Superscalar Asynchronous Low-Power Processor Philip Brian

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SCALP: a Superscalar Asynchronous Low-Power Processor Philip Brian

SCALP: A Superscalar Asynchronous Low-Power Processor A thesis submitted to the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Science and Engineering Philip Brian Endecott Department of Computer Science 1996 Contents Contents . 2 List of Figures. 6 List of Tables . 8 Abstract. 10 Declaration . 12 Copyright and Intellectual Property Rights . 12 Acknowledgements. 13 The Author . 13 Chapter 1: SCALP: A Superscalar Asynchronous Low-Power Processor. 14 1.1 The Importance of Power Efficiency . 15 1.2 Low Power Design Techniques . 16 1.2.1 Low-Level Power Efficiency . 16 Process Technology. 16 Transistor Level Design . 17 Charge Recovery and Adiabatic Systems . 17 Logic Optimisation . 18 Supply Voltage Adjustment . 18 Parallelism. 19 Precomputation . 19 Clocking Schemes and Asynchronous Logic . 19 1.2.2 Higher-Level Power Efficiency: Microprocessors . 20 External Memory Bandwidth . 20 Cache Characteristics . 20 Datapath Arrangement . 21 1.3 Previous Low Power Processors. 21 1.4 Overview of the Thesis. 22 Chapter 2: Reducing Transitions . 24 2.1 Code Density . 24 2.1.1 Variable Length Instructions . 27 2.1.2 Register Specifiers . 29 2.1.3 Previous High Code Density Processors . 31 D16 . 31 Thumb . 32 Transputer . 32 2.2 Datapath Activity . 33 Chapter 3: Parallelism . 35 3.1 Parallelism and Power . 35 3.2 Power, Parallelism and Cost . 37 3.3 Parallelism in Special Purpose Processors . 38 3.4 Parallelism in General Purpose Processors. 39 3.5 Pipelining . 40 3.5.1 Branch Instructions. 43 3.5.2 Dependencies . 45 3.5.3 Different Pipeline Arrangements . 48 - 2 - Shorter Pipelines . 48 Longer Pipelines . 48 3.6 Superscalar Parallelism. 49 3.6.1 Dependencies . 50 3.6.2 Branch Instructions. 54 3.6.3 Observations . 54 3.6.4 Simpler forms of Multiple Functional Unit Parallelism . 56 3.7 Speculative Execution . 57 Chapter 4: Asynchronous Logic. 59 4.1 Asynchronous Logic and Power Efficiency . 59 4.1.1 Asynchronous Circuits can be Faster . 59 4.1.2 Asynchronous Circuits can be Smaller. 61 4.1.3 Asynchronous Logic in Variable Demand Systems . 62 4.1.4 Asynchronous Logic and Dynamic Supply Voltage Adjustment. 63 4.1.5 Asynchronous Logic Doesn’t Waste Transitions . 64 4.1.6 Other benefits of Asynchronous Logic. 65 4.1.7 Tangram and the Philips DCC Error Corrector . 66 4.1.8 Conclusion . 67 4.2 Asynchronous Pipelines . 67 4.2.1 Forwarding in Asynchronous Pipelines . 69 4.2.2 Conditional Forwarding . 71 4.2.3 Explicit Forwarding . 73 4.3 Asynchronous Superscalar Parallelism. 74 4.3.1 Simple Superscalar Structures . 74 4.3.2 Superscalar Forwarding . 76 4.4 Previous Asynchronous Processors . 77 The Caltech Asynchronous Processor. 77 AMULET1 and AMULET2 . 79 NSR . 80 Fred . 81 Counterflow Pipeline Processor . 82 Hades. 83 ECSTAC . 83 TITAC . 84 ST_RISC . 84 FAM . 84 STRiP . 84 4.4.1 Observations . 85 Chapter 5: The SCALP Architecture . 87 5.1 Explicit Forwarding and Non-Global Registers . 88 5.2 Deadlocks and Determinism. 94 5.3 Other SCALP Features . 99 5.4 A SCALP Instruction Set . 100 5.5 The SCALP Programming Model . 104 5.6 Interrupts and Exceptions . 115 5.7 Related Work . 117 5.7.1 Stack Processors . 117 5.7.2 Architectural Queues . 117 - 3 - 5.7.3 Explicit Forwarding . 118 Chapter 6: Implementation . 120 6.1 Asynchronous Design Styles . 120 6.1.1 Timing Models for Control Circuits . 122 6.1.2 Timing Models for Datapaths. 122 6.1.3 Asynchronous Signalling Protocols . 123 6.2 Implementation Methodology . 125 6.3 Overview of the Design . 129 Memory Interface . 129 Fetcher. 129 FIG Fifo. 131 Issuer . ..

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