N88- 11229 : Performance Analysis of Parallel Branch and Bound Search with the Hypercube Architecture
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Validated Products List, 1995 No. 3: Programming Languages, Database
NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 QC 100 NIST .056 NO. 5693 1995 NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 (Supersedes April 1995 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary TECHNOLOGY ADMINISTRATION Mary L. Good, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Arati Prabhakar, Director FOREWORD The Validated Products List (VPL) identifies information technology products that have been tested for conformance to Federal Information Processing Standards (FIPS) in accordance with Computer Systems Laboratory (CSL) conformance testing procedures, and have a current validation certificate or registered test report. The VPL also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The VPL includes computer language processors for programming languages COBOL, Fortran, Ada, Pascal, C, M[UMPS], and database language SQL; computer graphic implementations for GKS, COM, PHIGS, and Raster Graphics; operating system implementations for POSIX; Open Systems Interconnection implementations; and computer security implementations for DES, MAC and Key Management. -
Emerging Technologies Multi/Parallel Processing
Emerging Technologies Multi/Parallel Processing Mary C. Kulas New Computing Structures Strategic Relations Group December 1987 For Internal Use Only Copyright @ 1987 by Digital Equipment Corporation. Printed in U.S.A. The information contained herein is confidential and proprietary. It is the property of Digital Equipment Corporation and shall not be reproduced or' copied in whole or in part without written permission. This is an unpublished work protected under the Federal copyright laws. The following are trademarks of Digital Equipment Corporation, Maynard, MA 01754. DECpage LN03 This report was produced by Educational Services with DECpage and the LN03 laser printer. Contents Acknowledgments. 1 Abstract. .. 3 Executive Summary. .. 5 I. Analysis . .. 7 A. The Players . .. 9 1. Number and Status . .. 9 2. Funding. .. 10 3. Strategic Alliances. .. 11 4. Sales. .. 13 a. Revenue/Units Installed . .. 13 h. European Sales. .. 14 B. The Product. .. 15 1. CPUs. .. 15 2. Chip . .. 15 3. Bus. .. 15 4. Vector Processing . .. 16 5. Operating System . .. 16 6. Languages. .. 17 7. Third-Party Applications . .. 18 8. Pricing. .. 18 C. ~BM and Other Major Computer Companies. .. 19 D. Why Success? Why Failure? . .. 21 E. Future Directions. .. 25 II. Company/Product Profiles. .. 27 A. Multi/Parallel Processors . .. 29 1. Alliant . .. 31 2. Astronautics. .. 35 3. Concurrent . .. 37 4. Cydrome. .. 41 5. Eastman Kodak. .. 45 6. Elxsi . .. 47 Contents iii 7. Encore ............... 51 8. Flexible . ... 55 9. Floating Point Systems - M64line ................... 59 10. International Parallel ........................... 61 11. Loral .................................... 63 12. Masscomp ................................. 65 13. Meiko .................................... 67 14. Multiflow. ~ ................................ 69 15. Sequent................................... 71 B. Massively Parallel . 75 1. Ametek.................................... 77 2. Bolt Beranek & Newman Advanced Computers ........... -
Programming Languages, Database Language SQL, Graphics, GOSIP
b fl ^ b 2 5 I AH1Q3 NISTIR 4951 (Supersedes NISTIR 4871) VALIDATED PRODUCTS LIST 1992 No. 4 PROGRAMMING LANGUAGES DATABASE LANGUAGE SQL GRAPHICS Judy B. Kailey GOSIP Editor POSIX COMPUTER SECURITY U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 100 . U56 4951 1992 NIST (Supersedes NISTIR 4871) VALIDATED PRODUCTS LIST 1992 No. 4 PROGRAMMING LANGUAGES DATABASE LANGUAGE SQL GRAPHICS Judy B. Kailey GOSIP Editor POSIX COMPUTER SECURITY U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 October 1992 (Supersedes July 1992 issue) U.S. DEPARTMENT OF COMMERCE Barbara Hackman Franklin, Secretary TECHNOLOGY ADMINISTRATION Robert M. White, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY John W. Lyons, Director - ;,’; '^'i -; _ ^ '’>.£. ; '':k ' ' • ; <tr-f'' "i>: •v'k' I m''M - i*i^ a,)»# ' :,• 4 ie®®;'’’,' ;SJ' v: . I 'i^’i i 'OS -.! FOREWORD The Validated Products List is a collection of registers describing implementations of Federal Information Processing Standards (FTPS) that have been validated for conformance to FTPS. The Validated Products List also contains information about the organizations, test methods and procedures that support the validation programs for the FTPS identified in this document. The Validated Products List is updated quarterly. iii ' ;r,<R^v a;-' i-'r^ . /' ^'^uffoo'*^ ''vCJIt<*bjteV sdT : Jr /' i^iL'.JO 'j,-/5l ':. ;urj ->i: • ' *?> ^r:nT^^'Ad JlSid Uawfoof^ fa«Di)itbiI»V ,, ‘ isbt^u ri il .r^^iytsrH n 'V TABLE OF CONTENTS 1. -
EOS: a Project to Investigate the Design and Construction of Real-Time Distributed Embedded Operating Systems
c EOS: A Project to Investigate the Design and Construction of Real-Time Distributed Embedded Operating Systems. * (hASA-CR-18G971) EOS: A PbCJECZ 10 187-26577 INVESTIGATE TEE CESIGI AND CCES!I&CCIXOti OF GEBL-1IIBE DISZEIEOTEO EWBEECIC CEERATIN6 SPSTEI!!S Bid-Year lieport, 1QE7 (Illinois Unclas Gniv.) 246 p Avail: AlIS BC All/!!P A01 63/62 00362E8 Principal Investigator: R. H. Campbell. Research Assistants: Ray B. Essick, Gary Johnston, Kevin Kenny, p Vince Russo. i Software Systems Research Group University of Illinois at Urbana-Champaign Department of Computer Science 1304 West Springfield Avenue Urbana, Illinois 61801-2987 (217) 333-0215 TABLE OF CONTENTS 1. Introduction. ........................................................................................................................... 1 2. Choices .................................................................................................................................... 1 3. CLASP .................................................................................................................................... 2 4. Path Pascal Release ................................................................................................................. 4 5. The Choices Interface Compiler ................................................................................................ 4 8. Summary ................................................................................................................................. 5 ABSTRACT: Project EOS is studying the problems -
Some Performance Comparisons for a Fluid Dynamics Code
NBSIR 87-3638 Some Performance Comparisons for a Fluid Dynamics Code Daniel W. Lozier Ronald G. Rehm U.S. DEPARTMENT OF COMMERCE National Bureau of Standards National Engineering Laboratory Center for Applied Mathematics Gaithersburg, MD 20899 September 1987 U.S. DEPARTMENT OF COMMERCE NATIONAL BUREAU OF STANDARDS NBSIR 87-3638 SOME PERFORMANCE COMPARISONS FOR A FLUID DYNAMICS CODE Daniel W. Lozier Ronald G. Rehm U.S. DEPARTMENT OF COMMERCE National Bureau of Standards National Engineering Laboratory Center for Applied Mathematics Gaithersburg, MD 20899 September 1987 U.S. DEPARTMENT OF COMMERCE, Clarence J. Brown, Acting Secretary NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director - 2 - 2. BENCHMARK PROBLEM In this section we describe briefly the source of the benchmark problem, the major logical structure of the Fortran program, and the parameters of three different specific instances of the benchmark problem that vary widely in the amount of time and memory required for execution. Research Background As stated in the introduction, our purpose in benchmarking computers is solely in the interest of further- ing our investigations into fundamental problems of fire science. Over a decade ago, stimulated by federal recognition of very large losses of fife and property by fires each year throughout the nation, NBS became actively involved in a national effort to reduce such losses. The work at NBS ranges from very practical to quite theoretical; our approach, which proceeds directly from basic principles, is at the theoretical end of this spectrum. Early work was concentrated on developing a mathematical model of convection arising from a prescribed source of heat in an enclosure, e.g. -
Real-Time Network Traffic Simulation Methodology with a Massively Parallel Computing Architecture
TRANSPORTATION RESEA RCH RECORD 1358 13 Advanced Traffic Management System: Real-Time Network Traffic Simulation Methodology with a Massively Parallel Computing Architecture THANAVAT }UNCHAYA, GANG-LEN CHANG, AND ALBERTO SANTIAGO The advent of parallel computing architectures presents an op of these ATMS developments would ensure optimal net portunity fo r lra nspon a tion professionals 1 imulate a large- ca le workwise performance. tra ffi c network with sufficienily fa t response time for real-time The anticipated benefits of these control methods depend opcrarion. Howeve r, ii neccssira tc ·. a fundament al change in the on the complex interactions among principal traffic system modeling algorithm LO tuke full ad va ntage of parallel computing. • uch a methodology t imulare tra ffic n twork with the Con components. These systems include driver behavior, level of nection Machine, a massively parallel computer, is described . The congestion, dynamic nature of traffic patterns, and the net basic parallel computing architectures are introdu ed, along with work's geometric configuration. It is crucial to the design of a list of commercially available parall el comput ers. This is fol these strategies that a comprehensive understanding of the lowed by an in-depth presentation of the proposed simulation complex interrelations between these key system components meth odology with a massively parallel computer. The propo ed traffic simulation model ha. an inherent path-proces ing capa be established. Because it is often difficult for theoretical bilit y to represent drivers ' roure choice behavior at the individual formulations to take all such complexities into account, traffic vehicle level. -
Alphaserver 4100 System
I ALPHASERVER 4100 SYSTEM ORACLE AND SYBASE DATABASE PRODUCTS Digital FOR VLM Technical INSTRUCTION EXECUTION ON ALPHA PROCESSORS Journal • Volume 8 Number 4 1996 Editorial The Digital Technicaljournal is a refereed The following arc trademarks of Digital Jane C. Blake, Managing Editor journal published quarterly by Digital Equipment Corporation: AlphaServer, Kathleen M. Stetson, Editor Equipment Corporation, 50 Nagog Park, AlphaStation, DEC, DECnet, DIGITAL, Helen L. Patterson, Editor AK02-3/B3, Acton, MA 017 20-9843. the DIGITAL logo,VAX, VMS, and ULTIUX. Hard-copy subscriptions can be ordered by Circulation sending a check in U.S. funds (made payable AIM is a trademark of AIM Technology, Inc. Catherine M. Phillips, Administrator to Digital Equipment Corporation) to the CCT is a registered trademark of Cooper Dorothea B. Cassady, Secretary published-by address. General subscription and Chyan Te chnologies, Inc. CHALLENGE rates are $40.00 (non-U.S. $60) for four and Silicon Graphics are registered a-ademarks Production issues and $75.00 (non-U.S. $115) for and POWER CHALLENGE is a trademark Christa W. Jessica, Production Editor eight issues. University and college profes of Silicon Graphics, Inc. Compaq is a regis Anne S. Katzcff, Typographer sors and Ph.D. students in the electrical tered trademark and ProLiant is a trademark Peter R. Wo odbury, lllustrator engineering and computer science fields of Compaq Computer Corporation. HP is receive complimentary subscriptions upon a registered trademark of Hewlett-Packard Advisory Board request. DIGITAL's customers may qualifY Company. HSPICE is a registered a·ade Samuel H. Fuller, Chairman for gifi: subscriptions and are encouraged mark of Metasoftware Corporation. -
Ronics APRIL 28, 1988
DATA GENERAL'S 88000 RISC CHIPS WILL HIT 100 MIPS/32 SMART-POWER IC SET ALL BUT ELIMINATES CIRCUIT DESIGN/93 A VNU PUBLICATION t• APRIL 28, 1988 ronics A CLOSE LOOK AT MOTOROLA'S 88000/75 CHOOSING A RISC CHIP: WHAT DRIVES CUSTOMERS?/85 This year,you'll hear alot of claims that "systems"design automation has arrived. database and user interface? This 32-bit Does it extend from design processor board At Mentor Grapimics/ definition through to was designed and PCB simulated on layout and output to manufacturing? Mentor Graphics we know better workstations by • Do you have more ASIC libraries Sequent Com- supported on your workstation than puter Systems for And so do our any other EDA vendor? Can you its multi-pro- cessor Symmetry include ASICs in board simulations? computer system. It contains over customers. Are your tools capable of manag- 175 IC compo- ing over 1000-page product docu- nents including They preach. We practice. 80386 pro- mentation projects from start to cessors, a14,000- Skeptical about "systems" elec- finish? gate standard cell and two 10,000- tronic design automation? Have you integrated mechanical gate arrays. You should be. Because in many packaging and analysis into the elec- cases, it's atriumph of form over tronic design and layout process? reason. Over 70% are repeat cus- content. In the end, there's only one Anything less than aperfect score tomers who've realized genuine practical yardstick for evaluating a is atotal loss. And aperfect score value added from our products and systems design solution. And that's does not mean just acheck in every seek to expand their competitive how many successful products it has box. -
Certification and Benchmarking of AIPS on the Convex
AIPS MEMO NO. _ 3 £ Certifioation and Benchmarking of AIPS on the Convex C-l and Alliant FX/8 Kerry C. Hilldrup, Donald C. Wells, William D. Cotton National Radio Astronomy Observatory [1] Edgemont Road, Charlottesville, VA 22903-2475 (804)296-0211, FTS=938-1271, TWX=910-997-0174 24 December 1985 [2] Abstract The 15APR85 release of AIPS has been installed on the Convex C-l vector computer and on the Alliant FX/8 vector/concurrent computer. Both have been certified using the PFT benchmarking and certification test. Although a small number of compiler bugs were encountered in each, the AIPS application code was installed with only minimal modifications, and computed results agreed well with other implementations of AIPS. In the course of the implementations, the technology of the Clark CLEAN algorithm was advanced considerably; the final vectorized CLEAN algorithm on both systems is about three times as fast as the current microcode algorithm on the FPS AP-120B array processor. Similar improvements were observed for other highly vectorized tasks. Programs which were not vectorized generally executed on both in comparable CPU times and faster real times than they achieved on the DEC VAX-8600. The FX/8 with 6 computational elements (CEs) generally outperformed the C-l by a little in CPU time, but was significantly slower in real time. The performance of the FX/8 as a function of the number of CEs is also described. [1] NRAO is operated by Associated Universities, Inc., under contract with the U. S. National Science Foundation. [2] this report entirely supersedes and replaces a previous version which was dated 18 July 1985 and was marked as "AIPS Memo No. -
Appendix G Vector Processors
G.1 Why Vector Processors? G-2 G.2 Basic Vector Architecture G-4 G.3 Two Real-World Issues: Vector Length and Stride G-16 G.4 Enhancing Vector Performance G-23 G.5 Effectiveness of Compiler Vectorization G-32 G.6 Putting It All Together: Performance of Vector Processors G-34 G.7 Fallacies and Pitfalls G-40 G.8 Concluding Remarks G-42 G.9 Historical Perspective and References G-43 Exercises G-49 G Vector Processors Revised by Krste Asanovic Department of Electrical Engineering and Computer Science, MIT I’m certainly not inventing vector processors. There are three kinds that I know of existing today. They are represented by the Illiac-IV, the (CDC) Star processor, and the TI (ASC) processor. Those three were all pioneering processors. One of the problems of being a pioneer is you always make mistakes and I never, never want to be a pioneer. It’s always best to come second when you can look at the mistakes the pioneers made. Seymour Cray Public lecture at Lawrence Livermore Laboratories on the introduction of the Cray-1 (1976) © 2003 Elsevier Science (USA). All rights reserved. G-2 I Appendix G Vector Processors G.1 Why Vector Processors? In Chapters 3 and 4 we saw how we could significantly increase the performance of a processor by issuing multiple instructions per clock cycle and by more deeply pipelining the execution units to allow greater exploitation of instruction- level parallelism. (This appendix assumes that you have read Chapters 3 and 4 completely; in addition, the discussion on vector memory systems assumes that you have read Chapter 5.) Unfortunately, we also saw that there are serious diffi- culties in exploiting ever larger degrees of ILP. -
Validated Products List: Programming Languages, Database Language
NISTIR 469 (Supersedes NISTIR 4623) VALIDATED PRODUCTS LIST 1991 No. 4 Programming Languages Database Language SQL Graphics ®OSIP Judy B. Kailey POSIX Editor U.S. DEPARTMENT OF COMMERCE National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 October 1991 (Supersedes July 1991 issue) U.S. DEPARTMENT OF COMMERCE Robert A. Mosbacher, Secretary NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY John W. Lyons, Director — QC 100 .U56 NIST //4690 1991 V C.2 NISTIR 4690 (Supersedes NISTIR 4623) - ' J JF VALIDATED PRODUCTS LIST 1991 No. 4 Programming Languages Database Langucige SQL Graphics GOSIP Judy B. Kailey POSIX Editor U.S. DEPARTMENT OF COMMERCE National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 October 1991 (Supersedes July 1991 issue) U.S. DEPARTMENT OF COMMERCE Robert A. Mosbacher, Secretary NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY John W. Lyons, Director FOREWORD The Validated Products List (formerly called the Validated Processor List) is a collection of registers describing implementations of Federal Information Processing Standards (FIPS) that have been tested for conformance to FIPS. The Validated Products List also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The Validated Products List is updated quarterly. TABLE OF CONTENTS 1. INTRODUCTION 1-1 1.1 Purpose 1-1 1.2 Document Organization 1-1 1.2.1 Programming Languages 1-1 1.2.2 Database Language SQL 1-2 1.2.3 Graphics 1-2 1.2.4 GOSIP 1-2 1.2.5 POSIX 1-2 1.2.6 FIPS Conformance Testing Products 1-2 2. -
ETHERNET and the FIFTH GENERATION Gordon Bell Vice
THE ENGINEERING OF THE VAX-11 COMPUTING ENVIRONMENT The VAX-11 architectural design and implementation began in 1975 with the goals of a wide range of system sizes and different styles of use. While much of the implementation has been "as planned", various nodes (eg. computers, disk servers) and combined structures (eg. clusters) have evolved in response to the technology forces, user requirements and constraints. The future offers even more possibilities for interesting structures. ETHERNET AND THE FIFTH GENERATION Gordon Bell Vice President, Engineering Digital Equipment Corporation In the Fifth Computer Generation, a wide variety of computers will communicate with one another. No one argues about this. The concern is about how to do it and what form the computers will take. A standard communications language is the key. I believe Ethernet is this unifying key to the 5th computer generation because it interconnects all sizes and types of computers in a passive, tightly-coupled, high performance fashion, permiting the formation of local-area networks. HOW THE JAPANESE HAVE CONVERTED WORLD INDUSTRY INTO DISTRIBUTORSHIPS -- CONCERN NOW FOR SEMICONDUCTORS AND COMPUTERS Gordon Bell Vice President Digital Equipment Corporation Abstract We all must be impressed with the intense drive, technical and manufacturing ability of the Japanese. As an island with few natural resources, and only very bright, hard working people they have set about and accomplished the market domination of virtually all manufactured consumer goods and the components and processes to make these goods (i.e., vertical integration). Currently the U.S. has a dominant position in computers and semiconductors. However, there's no fundamental reason why the Japanese won't attain a basic goal to dominate these industries, given their history in other areas and helped by our governments.