Certification and Benchmarking of AIPS on the Convex
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Validated Products List, 1995 No. 3: Programming Languages, Database
NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 QC 100 NIST .056 NO. 5693 1995 NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 (Supersedes April 1995 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary TECHNOLOGY ADMINISTRATION Mary L. Good, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Arati Prabhakar, Director FOREWORD The Validated Products List (VPL) identifies information technology products that have been tested for conformance to Federal Information Processing Standards (FIPS) in accordance with Computer Systems Laboratory (CSL) conformance testing procedures, and have a current validation certificate or registered test report. The VPL also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The VPL includes computer language processors for programming languages COBOL, Fortran, Ada, Pascal, C, M[UMPS], and database language SQL; computer graphic implementations for GKS, COM, PHIGS, and Raster Graphics; operating system implementations for POSIX; Open Systems Interconnection implementations; and computer security implementations for DES, MAC and Key Management. -
Emerging Technologies Multi/Parallel Processing
Emerging Technologies Multi/Parallel Processing Mary C. Kulas New Computing Structures Strategic Relations Group December 1987 For Internal Use Only Copyright @ 1987 by Digital Equipment Corporation. Printed in U.S.A. The information contained herein is confidential and proprietary. It is the property of Digital Equipment Corporation and shall not be reproduced or' copied in whole or in part without written permission. This is an unpublished work protected under the Federal copyright laws. The following are trademarks of Digital Equipment Corporation, Maynard, MA 01754. DECpage LN03 This report was produced by Educational Services with DECpage and the LN03 laser printer. Contents Acknowledgments. 1 Abstract. .. 3 Executive Summary. .. 5 I. Analysis . .. 7 A. The Players . .. 9 1. Number and Status . .. 9 2. Funding. .. 10 3. Strategic Alliances. .. 11 4. Sales. .. 13 a. Revenue/Units Installed . .. 13 h. European Sales. .. 14 B. The Product. .. 15 1. CPUs. .. 15 2. Chip . .. 15 3. Bus. .. 15 4. Vector Processing . .. 16 5. Operating System . .. 16 6. Languages. .. 17 7. Third-Party Applications . .. 18 8. Pricing. .. 18 C. ~BM and Other Major Computer Companies. .. 19 D. Why Success? Why Failure? . .. 21 E. Future Directions. .. 25 II. Company/Product Profiles. .. 27 A. Multi/Parallel Processors . .. 29 1. Alliant . .. 31 2. Astronautics. .. 35 3. Concurrent . .. 37 4. Cydrome. .. 41 5. Eastman Kodak. .. 45 6. Elxsi . .. 47 Contents iii 7. Encore ............... 51 8. Flexible . ... 55 9. Floating Point Systems - M64line ................... 59 10. International Parallel ........................... 61 11. Loral .................................... 63 12. Masscomp ................................. 65 13. Meiko .................................... 67 14. Multiflow. ~ ................................ 69 15. Sequent................................... 71 B. Massively Parallel . 75 1. Ametek.................................... 77 2. Bolt Beranek & Newman Advanced Computers ........... -
The Risks Digest Index to Volume 11
The Risks Digest Index to Volume 11 Search RISKS using swish-e Forum on Risks to the Public in Computers and Related Systems ACM Committee on Computers and Public Policy, Peter G. Neumann, moderator Index to Volume 11 Sunday, 30 June 1991 Issue 01 (4 February 1991) Re: Enterprising Vending Machines (Allan Meers) Re: Risks of automatic flight (Henry Spencer) Re: Voting by Phone & public-key cryptography (Evan Ravitz) Re: Random Voting IDs and Bogus Votes (Vote by Phone) (Mike Beede)) Re: Patriots ... (Steve Mitchell, Steven Philipson, Michael H. Riddle, Clifford Johnson) Re: Man-in-the-loop on SDI (Henry Spencer) Re: Broadcast local area networks ... (Curt Sampson, Donald Lindsay, John Stanley, Jerry Leichter) Issue 02 (5 February 1991) Bogus draft notices are computer generated (Jonathan Rice) People working at home on important tasks (Mike Albaugh) Predicting system reliability (Martyn Thomas) Re: Patriots (Steven Markus Woodcock, Mark Levison) Hungry copiers (another run-in with technology) (Scott Wilson) Re: Enterprising Vending Machines (Dave Curry) Broadcast LANs (Peter da Silva, Scott Hinckley) Issue 03 (6 February 1991) Tube Tragedy (Pete Mellor) New Zealand Computer Error Holds Up Funds (Gligor Tashkovich) "Inquiry into cash machine fraud" (Stella Page) Quick n' easy access to Fidelity account info (Carol Springs) Re: Enterprising Vending Machines (Mark Jackson) RISKS of no escape paths (Geoff Kuenning) A risky gas pump (Bob Grumbine) Electronic traffic signs endanger motorists... (Rich Snider) Re: Predicting system reliability (Richard P. Taylor) The new California licenses (Chris Hibbert) Phone Voting -- Really a Problem? (Michael Barnett, Dave Smith) Re: Electronic cash completely replacing cash (Barry Wright) Issue 04 (7 February 1991) Subway door accidents (Mark Brader) http://catless.ncl.ac.uk/Risks/index.11.html[2011-06-11 08:17:52] The Risks Digest Index to Volume 11 "Virus" destroys part of Mass. -
EOS: a Project to Investigate the Design and Construction of Real-Time Distributed Embedded Operating Systems
c EOS: A Project to Investigate the Design and Construction of Real-Time Distributed Embedded Operating Systems. * (hASA-CR-18G971) EOS: A PbCJECZ 10 187-26577 INVESTIGATE TEE CESIGI AND CCES!I&CCIXOti OF GEBL-1IIBE DISZEIEOTEO EWBEECIC CEERATIN6 SPSTEI!!S Bid-Year lieport, 1QE7 (Illinois Unclas Gniv.) 246 p Avail: AlIS BC All/!!P A01 63/62 00362E8 Principal Investigator: R. H. Campbell. Research Assistants: Ray B. Essick, Gary Johnston, Kevin Kenny, p Vince Russo. i Software Systems Research Group University of Illinois at Urbana-Champaign Department of Computer Science 1304 West Springfield Avenue Urbana, Illinois 61801-2987 (217) 333-0215 TABLE OF CONTENTS 1. Introduction. ........................................................................................................................... 1 2. Choices .................................................................................................................................... 1 3. CLASP .................................................................................................................................... 2 4. Path Pascal Release ................................................................................................................. 4 5. The Choices Interface Compiler ................................................................................................ 4 8. Summary ................................................................................................................................. 5 ABSTRACT: Project EOS is studying the problems -
Some Performance Comparisons for a Fluid Dynamics Code
NBSIR 87-3638 Some Performance Comparisons for a Fluid Dynamics Code Daniel W. Lozier Ronald G. Rehm U.S. DEPARTMENT OF COMMERCE National Bureau of Standards National Engineering Laboratory Center for Applied Mathematics Gaithersburg, MD 20899 September 1987 U.S. DEPARTMENT OF COMMERCE NATIONAL BUREAU OF STANDARDS NBSIR 87-3638 SOME PERFORMANCE COMPARISONS FOR A FLUID DYNAMICS CODE Daniel W. Lozier Ronald G. Rehm U.S. DEPARTMENT OF COMMERCE National Bureau of Standards National Engineering Laboratory Center for Applied Mathematics Gaithersburg, MD 20899 September 1987 U.S. DEPARTMENT OF COMMERCE, Clarence J. Brown, Acting Secretary NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director - 2 - 2. BENCHMARK PROBLEM In this section we describe briefly the source of the benchmark problem, the major logical structure of the Fortran program, and the parameters of three different specific instances of the benchmark problem that vary widely in the amount of time and memory required for execution. Research Background As stated in the introduction, our purpose in benchmarking computers is solely in the interest of further- ing our investigations into fundamental problems of fire science. Over a decade ago, stimulated by federal recognition of very large losses of fife and property by fires each year throughout the nation, NBS became actively involved in a national effort to reduce such losses. The work at NBS ranges from very practical to quite theoretical; our approach, which proceeds directly from basic principles, is at the theoretical end of this spectrum. Early work was concentrated on developing a mathematical model of convection arising from a prescribed source of heat in an enclosure, e.g. -
Programming Languages & Tools
I PROGRAMMING LANGUAGES & TOOLS Volume 10 Number 1 1998 Editorial The Digital Technicaljoumalis a refereed AlphaServer, Compaq, tl1e Compaq logo, jane C. Blake, Managing Editor journal published quarterly by Compaq DEC, DIGITAL, tl1e DIGITAL logo, 550 ULTIUX, Kathleen M. Stetson, Editor Computer Corporation, King Street, VAX,and VMS are registered 01460-1289. Hden L. Patterson, Editor LKGI-2jW7, Littleton, MA in the U.S. Patent and Trademark Office. Hard-copy subscriptions can be ordered by DIGITAL UNIX, FX132, and OpenVMS Circulation sending a check in U.S. funds (made payable arc trademarks of Compaq Computer Kristine M. Lowe, Administrator to Compaq Computer Corporation) to the Corporation. published-by address. General subscription Production rates arc $40.00 (non-U.S. $60) for four issues Intel and Pentium are registered u·ademarks $75.00 $115) Christa W. Jessica, Production Editor and (non-U.S. for eight issues. of Intel Corporation. University and college professors and Ph.D. Elizabeth McGrail, Typographer I lUX is a registered trademark of Silicon students in the elecu·icaJ engineering and com Peter R. Woodbury, Illustrator Graphics, Inc. puter science fields receive complimentary sub scriptions upon request. Compaq customers Microsoft, Visual C++, Windows, and Advisory Board may qualify tor giftsubscriptions and arc encour Windows NT are registered trademarks Thomas F. Gannon, Chairman (Acting) aged to contact tl1eir sales representatives. of Microsoft Corporation. Scott E. Cutler Donald Z. Harbert Electronic subscriptions are available at MIPS is a registered trademark of MIPS William A. Laing no charge by accessing URL Technologies, Inc. Richard F. Lary http:jjwww.digital.com/subscription. -
COMPUTATIONAL FLUID DYNAMICS: an Applications Profile from Convex Computer Corporation
COMPUTATIONAL FLUID DYNAMICS: An Applications Profile from Convex Computer Corporation This simulation. which is based on a Navier-Stokes analysis. depicts surface This simulation shows surface pressure predictions for the AV-88 Harrier II pressure predictions for the F-15 Eagle at Mach 0.9. forebody at Mach 0.8. Supercomputer simulations permit the engineer to observe phenomena that The AV-88 Harrier II can operate from small. unprepared sites and roads close wind tunnels cannot produce. to front Jines. Supercomputing performance brings large-scale simula effective resource for innovation, evaluation and enhancement tions into the aircraft designers repertoire. While not expected of aircraft design. to replace such traditional design tools as wind tunnels and test Design development using supercomputing simulation pro fiights, computer simulations offer the manufacturer a cost- ceeds from a systematic knowledge base rather than from conjecture or surmise. At the same time, computer simulation investigating the possibilities, MCAIR selected the Convex Cl, the increases the scope for design innovation and enhancement. first affordable supercomputer Its strong price/performance ratio The use of simulations makes iterative design experimentation proved decisive. cost-effective. Moreover, si mulations point the way to improve The Cl combines memory and vector processing capabilities ments in design. previously found only on large-scale supercomputers with the Supercomputer simulations also permit software and price advantages of minicom the engineer to obseNe details of fluid flow puters. MCAIR found that the Cl completed phenomena that wind tunnels cannot pro in 30 minutes runs that required hours on a duce. These include surface pressure dis "Computational fluid minicomputer tr i bu ti on s, shock wave locations and dynamics is more complex for Installed in September 1985, this 64-bit strengths, streamline paths and boundary military aircraft than for integrated scalar and vector processor with a layer behavior. -
Real-Time Network Traffic Simulation Methodology with a Massively Parallel Computing Architecture
TRANSPORTATION RESEA RCH RECORD 1358 13 Advanced Traffic Management System: Real-Time Network Traffic Simulation Methodology with a Massively Parallel Computing Architecture THANAVAT }UNCHAYA, GANG-LEN CHANG, AND ALBERTO SANTIAGO The advent of parallel computing architectures presents an op of these ATMS developments would ensure optimal net portunity fo r lra nspon a tion professionals 1 imulate a large- ca le workwise performance. tra ffi c network with sufficienily fa t response time for real-time The anticipated benefits of these control methods depend opcrarion. Howeve r, ii neccssira tc ·. a fundament al change in the on the complex interactions among principal traffic system modeling algorithm LO tuke full ad va ntage of parallel computing. • uch a methodology t imulare tra ffic n twork with the Con components. These systems include driver behavior, level of nection Machine, a massively parallel computer, is described . The congestion, dynamic nature of traffic patterns, and the net basic parallel computing architectures are introdu ed, along with work's geometric configuration. It is crucial to the design of a list of commercially available parall el comput ers. This is fol these strategies that a comprehensive understanding of the lowed by an in-depth presentation of the proposed simulation complex interrelations between these key system components meth odology with a massively parallel computer. The propo ed traffic simulation model ha. an inherent path-proces ing capa be established. Because it is often difficult for theoretical bilit y to represent drivers ' roure choice behavior at the individual formulations to take all such complexities into account, traffic vehicle level. -
Appendix G Vector Processors
G.1 Why Vector Processors? G-2 G.2 Basic Vector Architecture G-4 G.3 Two Real-World Issues: Vector Length and Stride G-16 G.4 Enhancing Vector Performance G-23 G.5 Effectiveness of Compiler Vectorization G-32 G.6 Putting It All Together: Performance of Vector Processors G-34 G.7 Fallacies and Pitfalls G-40 G.8 Concluding Remarks G-42 G.9 Historical Perspective and References G-43 Exercises G-49 G Vector Processors Revised by Krste Asanovic Department of Electrical Engineering and Computer Science, MIT I’m certainly not inventing vector processors. There are three kinds that I know of existing today. They are represented by the Illiac-IV, the (CDC) Star processor, and the TI (ASC) processor. Those three were all pioneering processors. One of the problems of being a pioneer is you always make mistakes and I never, never want to be a pioneer. It’s always best to come second when you can look at the mistakes the pioneers made. Seymour Cray Public lecture at Lawrence Livermore Laboratories on the introduction of the Cray-1 (1976) © 2003 Elsevier Science (USA). All rights reserved. G-2 I Appendix G Vector Processors G.1 Why Vector Processors? In Chapters 3 and 4 we saw how we could significantly increase the performance of a processor by issuing multiple instructions per clock cycle and by more deeply pipelining the execution units to allow greater exploitation of instruction- level parallelism. (This appendix assumes that you have read Chapters 3 and 4 completely; in addition, the discussion on vector memory systems assumes that you have read Chapter 5.) Unfortunately, we also saw that there are serious diffi- culties in exploiting ever larger degrees of ILP. -
Supercomputers: the Amazing Race Gordon Bell November 2014
Supercomputers: The Amazing Race Gordon Bell November 2014 Technical Report MSR-TR-2015-2 Gordon Bell, Researcher Emeritus Microsoft Research, Microsoft Corporation 555 California, 94104 San Francisco, CA Version 1.0 January 2015 1 Submitted to STARS IEEE Global History Network Supercomputers: The Amazing Race Timeline (The top 20 significant events. Constrained for Draft IEEE STARS Article) 1. 1957 Fortran introduced for scientific and technical computing 2. 1960 Univac LARC, IBM Stretch, and Manchester Atlas finish 1956 race to build largest “conceivable” computers 3. 1964 Beginning of Cray Era with CDC 6600 (.48 MFlops) functional parallel units. “No more small computers” –S R Cray. “First super”-G. A. Michael 4. 1964 IBM System/360 announcement. One architecture for commercial & technical use. 5. 1965 Amdahl’s Law defines the difficulty of increasing parallel processing performance based on the fraction of a program that has to be run sequentially. 6. 1976 Cray 1 Vector Processor (26 MF ) Vector data. Sid Karin: “1st Super was the Cray 1” 7. 1982 Caltech Cosmic Cube (4 node, 64 node in 1983) Cray 1 cost performance x 50. 8. 1983-93 Billion dollar SCI--Strategic Computing Initiative of DARPA IPTO response to Japanese Fifth Gen. 1990 redirected to supercomputing after failure to achieve AI goals 9. 1982 Cray XMP (1 GF) Cray shared memory vector multiprocessor 10. 1984 NSF Establishes Office of Scientific Computing in response to scientists demand and to counteract the use of VAXen as personal supercomputers 11. 1987 nCUBE (1K computers) achieves 400-600 speedup, Sandia winning first Bell Prize, stimulated Gustafson’s Law of Scalable Speed-Up, Amdahl’s Law Corollary 12. -
Shared Memory Programming on NUMA–Based Clusters Using a General and Open Hybrid Hardware / Software Approach
Shared Memory Programming on NUMA–based Clusters using a General and Open Hybrid Hardware / Software Approach Martin Schulz Institut für Informatik Lehrstuhl für Rechnertechnik und Rechnerorganisation Shared Memory Programming on NUMA–based Clusters using a General and Open Hybrid Hardware / Software Approach Martin Schulz Vollständiger Abdruck der von der Fakultät für Informatik der Technischen Universität München zur Erlangung des akademischen Grades eines Doktors der Naturwissenschaften (Dr. rer. nat.) genehmigten Dissertation. Vorsitzender: Univ.-Prof. R. Bayer, Ph.D. Prüfer der Dissertation: 1. Univ.-Prof. Dr. A. Bode 2. Univ.-Prof. Dr. H. Hellwagner, Universität Klagenfurt / Österreich Die Dissertation wurde am 24. April 2001 bei der Technischen Universität München ein- gereicht und durch die Fakultät für Informatik am 28. Juni 2001 angenommen. Abstract The widespread use of shared memory programming for High Performance Computing (HPC) is currently hindered by two main factors: the limited scalability of architectures with hardware support for shared memory and the abundance of existing programming models. In order to solve these issues, a comprehensive shared memory framework needs to be created which enables the use of shared memory on top of more scalable architectures and which provides a user–friendly solution to deal with the various different programming models. Driven by the first issue, a large number of so–called SoftWare Distributed Shared Memory (SW–DSM) systems have been developed. These systems rely solely on soft- ware components to create a transparent global virtual memory abstraction on highly scal- able, loosely coupled architectures without any direct hardware support for shared memory. However, they are often affected by inherent performance problems and, in addition, do not solve the second issue of the existence of (too) many shared memory programming models. -
Shared Memory Multiprocessor-A Brief Study
© 2014 IJIRT | Volume 1 Issue 6 | ISSN : 2349-6002 SHARED MEMORY MULTIPROCESSOR-A BRIEF STUDY Shivangi Kukreja,Nikita Pahuja,Rashmi Dewan Student,Computer Science&Engineering,Maharshi Dayanand University Gurgaon,Haryana,India Abstract- The intention of this paper is to provide an The popularity of these systems is not due simply to overview on the subject of Advanced computer the demand for high performance computing. These Architecture. The overview includes its presence in systems are excellent at providing high throughput hardware and software and different types of for a multiprocessing load, and function effectively organization. This paper also covers different part of as high-performance database servers, network shared memory multiprocessor. Through this paper we are creating awareness among the people about this servers, and Internet servers. Within limits, their rising field of multiprocessor. This paper also offers a throughput is increased linearly as more processors comprehensive number of references for each concept are added. in SHARED MEMORY MULTIPROCESSOR. In this paper we are not so interested in the performance of database or Internet servers. That is I. INTRODUCTION too passé; buy more processors, get better In the mid-1980s, shared-memory multiprocessors throughput. We are interested in pure, raw, were pretty expensive and pretty rare. Now, as unadulterated compute speed for our high hardware costs are dropping, they are becoming performance application. Instead of running hundreds commonplace. Many home computer systems in the of small jobs, we want to utilize all $750,000 worth under-$3000 range have a socket for a second CPU. of hardware for our single job.