Independent PA-RISC and Itanium Reference Book

Total Page:16

File Type:pdf, Size:1020Kb

Independent PA-RISC and Itanium Reference Book OpenPA The book of PA-RISC Paul Weissmann Bonn This document and its content are Copyright © 1999-2021 Paul Weissmann, Bonn, Germany, unless otherwise noted. Berlin, Bonn, Palo Alto, San Francisco No parts of this document may be reproduced or copied without prior written permission. Commercial use of the content is prohibited. OpenPA.net, the information resource on PA-RISC. Second edition Release 2.8 Bonn, May 2021 Other editions: Second edition 2.7: July 2020 Second edition 2.6: January 2018 Second edition 2.5: January 2016 Second edition 2.4: July 2012 Second edition 2.3: July 2009 Second edition 2.2: January 2009 Second edition 2.1: October 2008 Second edition 2.0: May 2008 First edition 1.2: December 2007 First edition 1.1: November 2007 First edition 1.0: July 2006 OpenPA.net (online) is a registered serial publication, ISSN 1866-2757. Paul Weissmann can be reached by e-mail: [email protected]. and online at Insignals Cyber Security and OpenKRITIS. Preface This is the print edition of the OpenPA.net website from Spring 2021. OpenPA is a resource for HP PA-RISC and Itanium computers with technical descriptions of workstations, servers, their hardware architecture and supported operating systems This project is independent of and does not represent The Hewlett Packard Company in any way. This is the Second Edition 2.8. Set with LATEX. Changes in Second Edition 2.8 since the last edition (2020): ê Many revisions and corrections (thanks!) ê Text and language in all chapters ê TeX backend update All other changes are listed in chapter 5.1. For the most current version of the OpenPA print edition please refer to http://www.openpa.net/print.html. i Contents Contents iii List of Tables v 1 Introduction 1 2 PA-RISC Design 4 2.1 Overview . 5 2.2 Overview . 8 2.3 PA-RISC Architecture . 42 2.4 PA-RISC Chipsets . 50 2.5 PA-RISC Buses . 68 2.6 PA-RISC Graphics Adapters . 75 2.7 PA-RISC SCSI . 78 3 PA-RISC Computer Systems 80 3.1 Overview . 81 3.2 HP 9000 and PA-RISC Story . 92 3.3 HP 9000/705 and 710 . 102 3.4 HP 9000/712 . 105 3.5 HP 9000/715 . 109 3.6 HP 9000/720, 730 and 750 . 113 3.7 HP 9000/725 . 116 3.8 HP 9000/735 and 755 . 119 3.9 HP 9000/742i VME Workstation . 123 3.10 HP 9000/743i and 744 VME Workstation . 125 3.11 HP 9000/745 VME Workstations . 129 3.12 HP 9000/745i and 747i VME Workstations . 132 3.13 HP 9000/748i and 748 VME Workstations . 135 3.14 HP 9000 74x Expansion . 138 3.15 HP 16600 and 16700 Agilent Logic Analyzers . 140 3.16 HP 9000/A180 . 145 3.17 HP A400, A500 (rp2400) . 148 3.18 HP Visualize B132L, B160L, B180L . 151 3.19 HP Visualize B1000, C3000, C3600 . 155 3.20 HP Visualize B2000 and B2600 . 158 3.21 HP 9000/C100 and C110 . 161 3.22 HP Visualize C132L, C160L . 164 3.23 HP Visualize C160, C180 . 168 3.24 HP Visualize C200, C240, C360 . 172 ii CONTENTS CONTENTS 3.25 HP C8000 . 176 3.26 HP 9000/D-Class and R-Class . 179 3.27 HP 9000/E-Class . 183 3.28 HP 9000 500 FOCUS . 186 3.29 Early PA-RISC Systems . 191 3.30 HP 9000 Series 800 Nova Servers . 195 3.31 HP i2000 . 198 3.32 HP Visualize J200, J210, J280, J2240 . 201 3.33 HP Visualize J5000, J5600, J7000, J7600 . 206 3.34 HP Visualize J6000, J6700 . 209 3.35 HP 9000/K-Class . 212 3.36 HP L1000 and L2000 (rp5400/rp5450) . 217 3.37 HP L1500 and L3000 (rp5430/rp5470) . 221 3.38 HP N4000 (rp7400) . 225 3.39 HP N4000 (rp7405/rp7410) . 228 3.40 HP 9000 rp3410 and rp3440 . 231 3.41 HP 9000 rp4410 and rp4440 . 235 3.42 HP Integrity rx1600 and rx1620 . 238 3.43 HP Integrity rx2600 and rx2620 . 242 3.44 HP Integrity rx4610 . 246 3.45 HP Integrity rx4640 . 250 3.46 HP Integrity rx5670 . 254 3.47 Convex Exemplar SPP1000, SPP1200 & SPP1600 . 258 3.48 HP/Convex SPP2000 (S-Class/X-Class) . 263 3.49 HP 9000/T500, T520, T600 and 890 . 267 3.50 HP V2200 and V2250 . 272 3.51 HP V2500 and V2600 . 275 3.52 HP zx2000 . 279 3.53 HP zx6000 . 282 3.54 RDI PrecisionBook . 285 3.55 SAIC Galaxy 1100 . 289 3.56 Stratus Continuum . 292 3.57 PA-RISC Third Party Systems . 300 3.58 PA-RISC Timeline from 1982 . 304 4 PA-RISC Operating Systems 312 4.1 Overview . 313 4.2 HP-UX . 315 4.3 PA-RISC Linux . 319 4.4 NetBSD/hppa . 322 4.5 NeXTSTEP on PA-RISC . 324 4.6 OpenBSD/hppa . 326 4.7 Research Operating Systems . 329 4.8 PA-RISC Operating Systems History . 335 5 Appendix 338 5.1 Print History . 339 5.2 PA-RISC Benchmarks . 343 iii List of Tables 2.1 PA-RISC hardware period table . 5 2.2 HP PA-RISC processors overview . 8 2.3 Other PA-RISC processors overview . 36 2.4 PA-RISC superscalar instruction classes . 46 2.5 PA-7100 allowed instruction bundles . 46 2.6 PA-7100LC/PA-7300LC allowed instruction bundles . 46 2.7 PA-7100LC/PA-7300LC allowed instruction bundles . 47 2.8 Chipsets used in PA-RISC computers . 50 2.9 Buses used in PA-RISC computers overview . 68 2.10 PCI buses used in PA-RISC computers overview . 74 2.11 HP CRX graphics adapters . 75 2.12 HP HCRX graphics adapters . 75 2.13.
Recommended publications
  • R&S®BBA100 Broadband Amplifier Open
    R&S®BBA100 Broadband Amplifier Open Source Acknowledgment 5353.8300.00 – 01 /RL/1/EN 01.00 / Broadcasting 3575.4620.02 M: - T - PAD Open Source Acknowledgment R&S BBA100 Introduction Contents 1 Introduction ......................................................................................... 3 1.1 Disclaimer ..................................................................................................................... 3 1.2 How to obtain the source code .................................................................................. 3 2 Software packages ............................................................................. 4 3 Verbatim license texts ........................................................................ 7 3.1 Apache License 2.0 ..................................................................................................... 7 3.2 GNU Library General Public License, Version 2.0 (LGPL 2.0) ..............................10 3.3 Boost Software License ............................................................................................18 3.4 GNU General Public License, Version 2.0 (GPL 2.0) ..............................................18 3.5 GNU Lesser General Public License, Version 2.1 (LGPL 2.1) ...............................24 3.6 Mozilla Public License, Version 1.1 (MPL 1.1) ........................................................32 3.7 MIT ...............................................................................................................................40 3.8 JDOM License
    [Show full text]
  • (12) Patent Application Publication (10) Pub
    US 20140.095539A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2014/0095539 A1 Smit et al. (43) Pub. Date: Apr. 3, 2014 (54) SYSTEMAND METHOD FOR tinuation of application No. 09/933,493, filed on Aug. ASYNCHRONOUS CLIENT SERVER SESSION 20, 2001, now Pat. No. 8,112,529. COMMUNICATION Publication Classification (71) Applicant: MasterObjects, Inc., Zeist (NL) (51) Int. Cl. (72) Inventors: Mark Hans Smit, Maarssen (NL); G06F 7/30 (2006.01) Stefan M. van den Oord, Best (NL) (52) U.S. Cl. CPC ................................ G06F 17/30696 (2013.01) (73) Assignee: MasterObjects, Inc., Zeist (NL) USPC .......................................................... 707/772 (57) ABSTRACT (21) Appl. No.: 14/027,645 The invention provides a session-based bi-directional multi tier client-server asynchronous information database search (22) Filed: Sep. 16, 2013 and retrieval system for sending a character-by-character string of data to an intelligent server that can be configured to Related U.S. Application Data immediately analyze the lengthening string character-by (63) Continuation of application No. 13/366,905, filed on character and return to the client increasingly appropriate Feb. 6, 2012, now Pat. No. 8,539,024, which is a con database information as the client sends the string. Arif ... is A i is Kerstriler listick: ersistent {}:s: Sters is: ritesic sig: liais: lagi Sistisic's Sife fertiei stees Mediate C3:::::::::::::::: issisi Eisik Patent Application Publication Apr. 3, 2014 Sheet 1 of 17 US 2014/0095539 A1 Questobjects {ssrt Ouest(bjecis Server its - {tiestfijects Series: FIG. Patent Application Publication Apr. 3, 2014 Sheet 2 of 17 US 2014/0095539 A1 iii.;; 'ersistent Q38: Store Freferencelas:g&f Sissistic'st Sisyre Sviciikai: -- - .
    [Show full text]
  • A Political History of X Or How I Stopped Worrying and Learned to Love the GPL
    A Political History of X or How I Stopped Worrying and Learned to Love the GPL Keith Packard SiFive [email protected] Unix in !"# ● $SD Everywhere – $'t not actually BS% ● )*+* want, to make Sy,tem V real – S'rely they still matter ● .o Free So/tware Anywhere The 0rigins of 1 ● $rian Reid and Pa'l Asente at Stan/ord – - kernel → VGTS → W window system – Ported to VS100 at Stan/ord ● $o4 Scheifler started hacking W→ X – Working on Argus with Barbara Liskov at LCS – 7ade it more Unix friendly (async9, renamed X -AXstation 00 (aka v, 339 Unix Workstation Market ● Unix wa, closed source ● Most vendors ,hipped a proprietary 0S 4ased on $SD #.x ● S'n: HP: Digita(: )po((o: *ektronix: I$7 ● ;congratu(ation,: yo'<re not running &'nice=. – Stil(: so many gratuito', di/ference, -AXstation II S'n >?@3 Early Unix Window Systems ● S'n-iew dominated (act'al commercial app,A De,ktop widget,A9 ● %igital had -WS/UIS (V7S on(y9 ● )pollo had %omain ● *ektronix demon,trating Sma((*alk 1 B1@ ● .onB/ree so/tware ● U,ed internally at MIT ● Shared with friend, in/ormally 1 3 ● )(mo,t u,able ● %elivered by Digital on V)1,tation, ● %i,trib'tion was not all free ,o/tware – Sun port relied on Sun-iew kernel API – %igital provided binary rendering code – IB7 PC?2T support act'ally complete (C9 Why 1 C ● 1 0 had wart, – rendering model was pretty terrible ● ,adly, X1 wa,n't m'ch better... – External window management witho't borders ● Get everyone involved – Well, at lea,t every workstation vendor willing to write big checks X as Corporate *ool ● Dim Gettys and Smokey
    [Show full text]
  • On the Hardware Reduction of Z-Datapath of Vectoring CORDIC
    On the Hardware Reduction of z-Datapath of Vectoring CORDIC R. Stapenhurst*, K. Maharatna**, J. Mathew*, J.L.Nunez-Yanez* and D. K. Pradhan* *University of Bristol, Bristol, UK **University of Southampton, Southampton, UK [email protected] Abstract— In this article we present a novel design of a hardware wordlength larger than 18-bits the hardware requirement of it optimal vectoring CORDIC processor. We present a mathematical becomes more than the classical CORDIC. theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z- In this particular work we propose a formulation to eliminate datapath. Using this technique it is possible to achieve three and 1.5 all the arithmetic operations along the z-datapath for conventional times reduction in the number of registers and adder respectively two-sided vector rotation and thereby reducing the hardware compared to classical CORDIC. Following this, a 16-bit vectoring while increasing the accuracy. Also the resulting architecture CORDIC is designed for the application in Synchronizer for IEEE shows significant hardware saving as the wordlength increases. 802.11a standard. The total area and dynamic power consumption Although we stick to the 2’s complement number system, without of the processor is 0.14 mm2 and 700μW respectively when loss of generality, this formulation can be adopted easily for synthesized in 0.18μm CMOS library which shows its effectiveness redundant arithmetic and higher radix formulation. A 16-bit as a low-area low-power processor. processor developed following this formulation requires 0.14 mm2 area and consumes 700 μW dynamic power when synthesized in 0.18μm CMOS library.
    [Show full text]
  • VOLUME V INFORMATIQUE NON AMERICAINE Première Partie Par L' Ingénieur Général De L'armement BOUCHER Henri TABLE
    VOLUME V INFORMATIQUE NON AMERICAINE Première partie par l' Ingénieur Général de l'Armement BOUCHER Henri TABLE DES MATIERES INFORMATIQUE NON AMERICAINE Première partie 731 Informatique européenne (statistiques, exemples) 122 700 Histoire de l'Informatique allemande 1 701 Petits constructeurs 5 702 Les facturières de Kienzle Data System 16 703 Les minis de gestion de Nixdorf 18 704 Siemens & Halske AG 23 705 Systèmes informatiques d'origine allemande 38 706 Histoire de l'informatique britannique 40 707 Industriels anglais de l'informatique 42 708 Travaux des Laboratoires d' Etat 60 709 Travaux universitaires 63 710 Les coeurs synthétisables d' ARM 68 711 Computer Technology 70 712 Elliott Brothers et Elliott Automation 71 713 Les machines d' English Electric Company 74 714 Les calculateurs de Ferranti 76 715 Les études de General Electric Company 83 716 La patiente construction de ICL 85 Catalogue informatique – Volume E - Ingénieur Général de l'Armement Henri Boucher Page : 1/333 717 La série 29 d' ICL 89 718 Autres produits d' ICL, et fin 94 719 Marconi Company 101 720 Plessey 103 721 Systèmes en Grande-Bretagne 105 722 Histoire de l'informatique australienne 107 723 Informatique en Autriche 109 724 Informatique belge 110 725 Informatique canadienne 111 726 Informatique chinoise 116 727 Informatique en Corée du Sud 118 728 Informatique à Cuba 119 729 Informatique danoise 119 730 Informatique espagnole 121 732 Informatique finlandaise 128 733 Histoire de l'informatique française 130 734 La période héroïque : la SEA 140 735 La Compagnie
    [Show full text]
  • Chapter 1: Computer Abstractions and Technology 1.6 – 1.7: Performance and Power
    Chapter 1: Computer Abstractions and Technology 1.6 – 1.7: Performance and power ITSC 3181 Introduction to Computer Architecture https://passlaB.githuB.io/ITSC3181/ Department of Computer Science Yonghong Yan [email protected] https://passlab.github.io/yanyh/ Lectures for Chapter 1 and C Basics Computer Abstractions and Technology • Lecture 01: Chapter 1 – 1.1 – 1.4: Introduction, great ideas, Moore’s law, aBstraction, computer components, and program execution • Lecture 02: C Basics; Memory and Binary Systems • Lecture 03: Number System, Compilation, Assembly, Linking and Program Execution ☛• Lecture 04: Chapter 1 – 1.6 – 1.7: Performance, power and technology trends • Lecture 05: – 1.8 - 1.9: Multiprocessing and Benchmarking 2 § 1.6 Performance 1.6 Defining Performance • Which airplane has the best performance? Boeing 777 Boeing 777 Boeing 747 Boeing 747 BAC/Sud BAC/Sud Concorde Concorde Douglas Douglas DC- DC-8-50 8-50 0 100 200 300 400 500 0 2000 4000 6000 8000 10000 Passenger Capacity Cruising Range (miles) Boeing 777 Boeing 777 Boeing 747 Boeing 747 BAC/Sud BAC/Sud Concorde Concorde Douglas Douglas DC- DC-8-50 8-50 0 500 1000 1500 0 100000 200000 300000 400000 Cruising Speed (mph) Passengers x mph 3 Response Time and Throughput • Response time çè Latency – How long it takes to do a task • Throughput çè Bandwidth – Total work done per unit time • e.g., tasks/transactions/… per hour • How are response time and throughput affected by – Replacing the processor with a faster version? – Adding more processors? • We’ll focus on response time for now… 4 Relative Performance • Define Performance = 1/Execution Time • “X is n time faster than Y”, i.e.
    [Show full text]
  • Emerging Technologies Multi/Parallel Processing
    Emerging Technologies Multi/Parallel Processing Mary C. Kulas New Computing Structures Strategic Relations Group December 1987 For Internal Use Only Copyright @ 1987 by Digital Equipment Corporation. Printed in U.S.A. The information contained herein is confidential and proprietary. It is the property of Digital Equipment Corporation and shall not be reproduced or' copied in whole or in part without written permission. This is an unpublished work protected under the Federal copyright laws. The following are trademarks of Digital Equipment Corporation, Maynard, MA 01754. DECpage LN03 This report was produced by Educational Services with DECpage and the LN03 laser printer. Contents Acknowledgments. 1 Abstract. .. 3 Executive Summary. .. 5 I. Analysis . .. 7 A. The Players . .. 9 1. Number and Status . .. 9 2. Funding. .. 10 3. Strategic Alliances. .. 11 4. Sales. .. 13 a. Revenue/Units Installed . .. 13 h. European Sales. .. 14 B. The Product. .. 15 1. CPUs. .. 15 2. Chip . .. 15 3. Bus. .. 15 4. Vector Processing . .. 16 5. Operating System . .. 16 6. Languages. .. 17 7. Third-Party Applications . .. 18 8. Pricing. .. 18 C. ~BM and Other Major Computer Companies. .. 19 D. Why Success? Why Failure? . .. 21 E. Future Directions. .. 25 II. Company/Product Profiles. .. 27 A. Multi/Parallel Processors . .. 29 1. Alliant . .. 31 2. Astronautics. .. 35 3. Concurrent . .. 37 4. Cydrome. .. 41 5. Eastman Kodak. .. 45 6. Elxsi . .. 47 Contents iii 7. Encore ............... 51 8. Flexible . ... 55 9. Floating Point Systems - M64line ................... 59 10. International Parallel ........................... 61 11. Loral .................................... 63 12. Masscomp ................................. 65 13. Meiko .................................... 67 14. Multiflow. ~ ................................ 69 15. Sequent................................... 71 B. Massively Parallel . 75 1. Ametek.................................... 77 2. Bolt Beranek & Newman Advanced Computers ...........
    [Show full text]
  • 18-447 Computer Architecture Lecture 6: Multi-Cycle and Microprogrammed Microarchitectures
    18-447 Computer Architecture Lecture 6: Multi-Cycle and Microprogrammed Microarchitectures Prof. Onur Mutlu Carnegie Mellon University Spring 2015, 1/28/2015 Agenda for Today & Next Few Lectures n Single-cycle Microarchitectures n Multi-cycle and Microprogrammed Microarchitectures n Pipelining n Issues in Pipelining: Control & Data Dependence Handling, State Maintenance and Recovery, … n Out-of-Order Execution n Issues in OoO Execution: Load-Store Handling, … 2 Reminder on Assignments n Lab 2 due next Friday (Feb 6) q Start early! n HW 1 due today n HW 2 out n Remember that all is for your benefit q Homeworks, especially so q All assignments can take time, but the goal is for you to learn very well 3 Lab 1 Grades 25 20 15 10 5 Number of Students 0 30 40 50 60 70 80 90 100 n Mean: 88.0 n Median: 96.0 n Standard Deviation: 16.9 4 Extra Credit for Lab Assignment 2 n Complete your normal (single-cycle) implementation first, and get it checked off in lab. n Then, implement the MIPS core using a microcoded approach similar to what we will discuss in class. n We are not specifying any particular details of the microcode format or the microarchitecture; you can be creative. n For the extra credit, the microcoded implementation should execute the same programs that your ordinary implementation does, and you should demo it by the normal lab deadline. n You will get maximum 4% of course grade n Document what you have done and demonstrate well 5 Readings for Today n P&P, Revised Appendix C q Microarchitecture of the LC-3b q Appendix A (LC-3b ISA) will be useful in following this n P&H, Appendix D q Mapping Control to Hardware n Optional q Maurice Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Manchester Univ.
    [Show full text]
  • The Risks Digest Index to Volume 11
    The Risks Digest Index to Volume 11 Search RISKS using swish-e Forum on Risks to the Public in Computers and Related Systems ACM Committee on Computers and Public Policy, Peter G. Neumann, moderator Index to Volume 11 Sunday, 30 June 1991 Issue 01 (4 February 1991) Re: Enterprising Vending Machines (Allan Meers) Re: Risks of automatic flight (Henry Spencer) Re: Voting by Phone & public-key cryptography (Evan Ravitz) Re: Random Voting IDs and Bogus Votes (Vote by Phone) (Mike Beede)) Re: Patriots ... (Steve Mitchell, Steven Philipson, Michael H. Riddle, Clifford Johnson) Re: Man-in-the-loop on SDI (Henry Spencer) Re: Broadcast local area networks ... (Curt Sampson, Donald Lindsay, John Stanley, Jerry Leichter) Issue 02 (5 February 1991) Bogus draft notices are computer generated (Jonathan Rice) People working at home on important tasks (Mike Albaugh) Predicting system reliability (Martyn Thomas) Re: Patriots (Steven Markus Woodcock, Mark Levison) Hungry copiers (another run-in with technology) (Scott Wilson) Re: Enterprising Vending Machines (Dave Curry) Broadcast LANs (Peter da Silva, Scott Hinckley) Issue 03 (6 February 1991) Tube Tragedy (Pete Mellor) New Zealand Computer Error Holds Up Funds (Gligor Tashkovich) "Inquiry into cash machine fraud" (Stella Page) Quick n' easy access to Fidelity account info (Carol Springs) Re: Enterprising Vending Machines (Mark Jackson) RISKS of no escape paths (Geoff Kuenning) A risky gas pump (Bob Grumbine) Electronic traffic signs endanger motorists... (Rich Snider) Re: Predicting system reliability (Richard P. Taylor) The new California licenses (Chris Hibbert) Phone Voting -- Really a Problem? (Michael Barnett, Dave Smith) Re: Electronic cash completely replacing cash (Barry Wright) Issue 04 (7 February 1991) Subway door accidents (Mark Brader) http://catless.ncl.ac.uk/Risks/index.11.html[2011-06-11 08:17:52] The Risks Digest Index to Volume 11 "Virus" destroys part of Mass.
    [Show full text]
  • HP 9000 Rp4410-4 and Rp4440-8 Servers Data Sheet
    HP 9000 rp4410-4 and rp4440-8 Servers Data sheet From entry-class 2-processor systems up to the high-end, 128-way HP 9000 Superdome, the HP 9000 server family delivers world-class, high- performance computing to the Adaptive Enterprise. Powered by the new PA-8900 processor with increased performance—and running the HP-UX 11i operating environment—HP 9000 servers add greater strength to HP’s industry-leading server portfolio by integrating seamlessly into your existing IT infrastructure and providing the type of longevity that’s crucial to protecting your investment. HP introduces new 1-, 2-, and 4-way systems to its the high-availability features you’d expect in an enterprise HP 9000 family with the HP 9000 rp4410-4 Server, application server, and its elegant server design makes while offering improved 8-way scalability in the HP 9000 for easy installation, upgrading, and service. With rp4440-8 Server. Each server offers up to 128 GB of excellent performance scalability and dense form factor, memory, runs the rock-solid HP-UX 11i operating system, the HP 9000 rp4410-4 and rp4440-8 Servers deliver the and is powered by the new PA-8900 processor, which performance required for critical business applications delivers improved performance and larger memory cache such as ERP, CRM, and e-commerce—while conserving IT than before. The HP 9000 rp4400 server series has all of funds and data-center space. Key features: Key benefits: HP 9000 rp4410-4 and rp4440-8 HP 9000 rp4410-4 and rp4440-8 Servers Servers • Latest generation of PA-RISC PA-8900
    [Show full text]
  • SIMD Extensions
    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
    [Show full text]
  • Historical Perspective and Further Reading 162.E1
    2.21 Historical Perspective and Further Reading 162.e1 2.21 Historical Perspective and Further Reading Th is section surveys the history of in struction set architectures over time, and we give a short history of programming languages and compilers. ISAs include accumulator architectures, general-purpose register architectures, stack architectures, and a brief history of ARMv7 and the x86. We also review the controversial subjects of high-level-language computer architectures and reduced instruction set computer architectures. Th e history of programming languages includes Fortran, Lisp, Algol, C, Cobol, Pascal, Simula, Smalltalk, C+ + , and Java, and the history of compilers includes the key milestones and the pioneers who achieved them. Accumulator Architectures Hardware was precious in the earliest stored-program computers. Consequently, computer pioneers could not aff ord the number of registers found in today’s architectures. In fact, these architectures had a single register for arithmetic instructions. Since all operations would accumulate in one register, it was called the accumulator , and this style of instruction set is given the same name. For example, accumulator Archaic EDSAC in 1949 had a single accumulator. term for register. On-line Th e three-operand format of RISC-V suggests that a single register is at least two use of it as a synonym for registers shy of our needs. Having the accumulator as both a source operand and “register” is a fairly reliable indication that the user the destination of the operation fi lls part of the shortfall, but it still leaves us one has been around quite a operand short. Th at fi nal operand is found in memory.
    [Show full text]