VOLUME V INFORMATIQUE NON AMERICAINE Première Partie Par L' Ingénieur Général De L'armement BOUCHER Henri TABLE

Total Page:16

File Type:pdf, Size:1020Kb

VOLUME V INFORMATIQUE NON AMERICAINE Première Partie Par L' Ingénieur Général De L'armement BOUCHER Henri TABLE VOLUME V INFORMATIQUE NON AMERICAINE Première partie par l' Ingénieur Général de l'Armement BOUCHER Henri TABLE DES MATIERES INFORMATIQUE NON AMERICAINE Première partie 731 Informatique européenne (statistiques, exemples) 122 700 Histoire de l'Informatique allemande 1 701 Petits constructeurs 5 702 Les facturières de Kienzle Data System 16 703 Les minis de gestion de Nixdorf 18 704 Siemens & Halske AG 23 705 Systèmes informatiques d'origine allemande 38 706 Histoire de l'informatique britannique 40 707 Industriels anglais de l'informatique 42 708 Travaux des Laboratoires d' Etat 60 709 Travaux universitaires 63 710 Les coeurs synthétisables d' ARM 68 711 Computer Technology 70 712 Elliott Brothers et Elliott Automation 71 713 Les machines d' English Electric Company 74 714 Les calculateurs de Ferranti 76 715 Les études de General Electric Company 83 716 La patiente construction de ICL 85 Catalogue informatique – Volume E - Ingénieur Général de l'Armement Henri Boucher Page : 1/333 717 La série 29 d' ICL 89 718 Autres produits d' ICL, et fin 94 719 Marconi Company 101 720 Plessey 103 721 Systèmes en Grande-Bretagne 105 722 Histoire de l'informatique australienne 107 723 Informatique en Autriche 109 724 Informatique belge 110 725 Informatique canadienne 111 726 Informatique chinoise 116 727 Informatique en Corée du Sud 118 728 Informatique à Cuba 119 729 Informatique danoise 119 730 Informatique espagnole 121 732 Informatique finlandaise 128 733 Histoire de l'informatique française 130 734 La période héroïque : la SEA 140 735 La Compagnie des Machines Bull 148 736 Autres sociétés françaises avant le Plan Calcul 153 737 Les Administrations 162 738 Le rôle des Armées 170 739 La Compagnie Internationale pour l' Informatique 182 740 La Télémécanique 185 741 La Thomson / CSF, structure d'accueil 186 742 La CII / HB puis Bull 194 743 Autres sociétés françaises d'informatique 203 744 Logabax, imprimantes et ordinateurs de bureau 221 745 Quelques systèmes français à caractère civil 223 Catalogue informatique – Volume E - Ingénieur Général de l'Armement Henri Boucher Page : 2/333 700 - Histoire de l' Informatique allemande L'Allemagne est un des rares pays à avoir abordé l'informatique avant la guerre, avec les travaux de l'ingénieur Konrad Züse, dont la première réalisation était mécanique. Züse avait compris la nécessité d'une véritable programmation, et prèvu à cet effet un bloc de commande exploitant des trous dans un support commode, carte ou ruban. Cependant , l'absence d'un soutien industriel, ainsi que le souci d'indépendance de l'auteur, empéchèrent cette étude de déboucher sur un produit, malgré un modeste soutien de Hitler. A la fin de la guerre, Züse a réussi à sauver un de ses prototypes et entreprend, avant tout autre organisme du pays, de construire une machine à relais commercialisable qui sera la Z4 ; l' inspiration semble être venue des machines des laboratoires Bell, et une trentaine de ces très petites machines, programmées par bandes perforées et travaillant au rythme très lent de quelques instructions par seconde, verront le jour avant que Züse n'aborde l' électronique avec le Z22 de 1950. Züse construira et vendra plusieurs machines petites et moyennes, sans jamais déboucher sur une production de masse, sans doute à cause de son refus de perdre son indépendance, mais aussi parce que personne en Allemagne à cette époque ne croit à l'avenir de l'informatique. Dans l'immédiat après-guerre, ce n'est cependant pas le travail de Züse qui introduit l'informatique en Allemagne, mais celui des Universités qui, soutenues par le Plan Marshall à partir de 1949, se lancent, comme leurs homologues américaines, dans des constructions expérimentales . On peut citer : - l' Université de Berlin Ouest, qui s'inspire du Z22 de Züse. Voir fiche - la Technische Hochschule de Darmstadt, où le Professeur Dr A. Walther construit DERA, dans le cadre de l' Institut de Mathématiques Pratiques. Il s'agit d'une machine à tambour magnétique et tubes. Voir fiche. On peut noter que cet institut avait largement débuté le calcul analogique avant la guerre, et que cette tradition s'était poursuivie ; en 1948, le même institut avait présenté dans un congrès un analyseur différentiel mécanique, probablement réalisé pendant la guerre, et déjà dépassé. En 1954, ce même Institut se modernise avec ELARD, un analyseur différentiel électronique fonctionnant sur le mode itératif. Un matériel analogue, EARI, existe à la Technische Hochschule d' Ilmenau. - la Technische Hochschule de Dresde, en Allemagne de l' Est cette fois, construira dès 1956 la D1, une machine scientifique à tambour magnétique et tubes, qui sera suivie d' une D2, puis d'une D4 transistorisée. Voir trois fiches. - l' Institut Max Planck de Göttingen réalisera dès 1952 une très modeste machine à tubes et tambour, la G1, qui sera un symbole du relèvement scientifique de l' Allemagne, probablement à cause du dynamisme avec lequel l' institut, transporté assez vite à Munich, développera ses idées avec un G1A (1958), un G2 en 1954 et un G3 en 1959. Ce dernier comporte une mémoire à tores. Voir quatre fiches. Catalogue informatique – Volume E - Ingénieur Général de l'Armement Henri Boucher Page : 3/333 Plus tard, l' Institut réalisera en 1969 BRUSH, un calculateur spécialisé pour l'exploitation des photos de chambre à bulles. L'unité centrale comprend 16 registres à décalage où l'on introduit les images numérisées, et 48 unités de traitement qui y recherchent des alignements ; elle est reliée à la mémoire de travail, tores 8K * 18 bits, 1 µs plus 64 registres 18 bits, 30 ns ; et à l'écran lecteur de photos, à travers un tampon de 64 mots 18 bits, 0,2 µs. Addition en 70 ns, multiplication 600 ns, division et racine carrée. Sortie sur bande. Logiciel spécialisé dans une mémoire de programme séparée, 2K * 18 bits, 100 ns. - la Technische Hochschule de Munich construira en 1956 PERM, une machine nettement plus puissante, elle aussi avec des tores magnétiques en plus du tambour. Voir fiche. - on peut aussi évoquer le travail accompli à la Technische Hochschule du Brunswick sur une additionneuse à introduction phonétique des opérandes. Voir document. Ces diverses machines furent les supports techniques d'un important investissement intellectuel qui devait conduire les chercheurs allemands à prendre, vers 1956, l'initiative d'un effort international sur les langages et en conséquence, sur les compilateurs, effort qui déboucha sur la création d' Algol. Ces chercheurs n'ont pas prétendu être les inventeurs des concepts, et ont d'emblée invité à participer les meilleurs théoriciens américains ; mais ce sont eux, et leurs collègues hollandais et danois, qui ont orienté les travaux du groupe vers l' abstraction et, après la perte d'intérêt des américains, soutenu l'ambitieux projet Algol 68 jusqu'à son abandon. Les universités cessent tout effort de construction dès l'apparition de machines commerciales, essentiellement américaines, sur lesquelles il était possible de poursuivre ces recherches. Très occupés à simplement renaître, les industriels allemands ne s'intéressent pas à l'informatique, leurs besoins étant satisfaits par leurs productions de machines comptables et de mécanographie. Ce sont donc les étrangers, l' américain IBM et le français Bull, déjà implantés en Allemagne avant guerre, qui vont introduire les premières machines industrielles à tubes, respectivement la 650 et le Gamma 3. L'apparition du transistor, qui permet des réalisations à moindre risque, suscite enfin quelques efforts nationaux. En plus de Züse, qui avance à petits pas, il s'agit de : Telefunken, un fabricant de postes radio, qui réalise quelques machines pour des projets des administra- tions : TR4 scientifique, TR5 pour les postes, TR10 de gestion. Siemens, qui crée sa propre architecture avec le 2002, puis le 3003. De plus, un nouvel étranger s'implante à Francfort : Univac, tenu hors de France par des accords avec Bull concernant les cartes perforées, s'installe en Allemagne pour commercialiser les machines de gestion de Bluebell, et d'autre part propose à l' OTAN les machines à succès qu'il a étudiées pour la Marine américaine, en offrant de les faire fabriquer chez Telefunken. Cette dernière tentative échouera. L'arrivée de la série S/360 d' IBM, dont l'usine de Sindelfingen produit le modèle 30 pour l' Europe, change le point de vue allemand. Si le gouvernement n'est toujours pas intéressé, les industriels prennent conscience qu'il y a un marché et Catalogue informatique – Volume E - Ingénieur Général de l'Armement Henri Boucher Page : 4/333 commencent à investir, alors que le parc est presque entièrement étranger. C'est Siemens qui prend la position la plus nette et, faute d'expertise nationale, choisit de prendre la license de RCA pour une famille 4004 qui n'est autre que la mise en boitiers allemands des logiques Spectra 70, compatibles IBM. Quantitativement, cela reste un succès modeste. Par contre, l'essor de l'ordinateur de bureau en Allemagne est supérieur en valeur relative à celui de tout autre pays. En dehors des spécialistes américains Burroughs et NCR, et de sociétés à capitaux mixtes comme Triumph Adler et Litton ABS, il y a des créations nationales : Siemag, filiale de Philips, Kienzle, et surtout le nouveau venu Nixdorf, qui n'hésitera pas à attaquer le marché américain. Ce n'est que vers 1967, cependant, après l'affaire Bull en France et le démarrage d'un plan informatique français, que le gouvernement allemand s'émeut et commence à envisager une politique nationale, qui va prendre la forme d'un mportant soutien financier à Siemens, complèté par des achats à Telefunken de petites machines militaires TR 86. Vers cette époque, la foire de Hanovre prend progressivement une importance mondiale, européenne à tout le moins, et ses pavillons informatiques mettent en évidence le dynamisme de petits constructeurs de mini-machines de gestion qui se créent dans le sillage de Nixdorf, Wagner, CTM, DDC, etc..
Recommended publications
  • SIMD Extensions
    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
    [Show full text]
  • Computer Hardware
    Computer Hardware MJ Rutter mjr19@cam Michaelmas 2014 Typeset by FoilTEX c 2014 MJ Rutter Contents History 4 The CPU 10 instructions ....................................... ............................................. 17 pipelines .......................................... ........................................... 18 vectorcomputers.................................... .............................................. 36 performancemeasures . ............................................... 38 Memory 42 DRAM .................................................. .................................... 43 caches............................................. .......................................... 54 Memory Access Patterns in Practice 82 matrixmultiplication. ................................................. 82 matrixtransposition . ................................................107 Memory Management 118 virtualaddressing .................................. ...............................................119 pagingtodisk ....................................... ............................................128 memorysegments ..................................... ............................................137 Compilers & Optimisation 158 optimisation....................................... .............................................159 thepitfallsofF90 ................................... ..............................................183 I/O, Libraries, Disks & Fileservers 196 librariesandkernels . ................................................197
    [Show full text]
  • Validated Products List, 1993 No. 2
    mmmmm NJST PUBLICATIONS NISTIR 5167 (Supersedes NISTIR 5103) Validated Products List 1993 No. 2 Programming Languages Database Language SQL Graphics GOSIP POSIX Judy B. Kailey Computer Security Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 April 1993 (Supersedes January 1993 issue) —QC 100 NIST . U56 #5167 1993 NISTIR 5167 (Supersedes NISTIR 5103) Validated Products List 1993 No. 2 Programming Languages Database Language SQL Graphics GOSIP POSIX Judy B. Kailey Computer Security Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 April 1993 (Supersedes January 1993 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Raymond Kammer, Acting Director FOREWORD The Validated Products List is a collection of registers describing implementations of Federal Information Processing Standards (FIPS) that have been validated for conformance to FTPS. The Validated Products List also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The Validated Products List is updated quarterly. iii iv TABLE OF CONTENTS 1. INTRODUCTION 1 1.1 Purpose 1 1.2 Document Organization 2 1.2.1 Programming Languages 2 1.2.2 Database
    [Show full text]
  • Processor Design:System-On-Chip Computing For
    Processor Design Processor Design System-on-Chip Computing for ASICs and FPGAs Edited by Jari Nurmi Tampere University of Technology Finland A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN 978-1-4020-5529-4 (HB) ISBN 978-1-4020-5530-0 (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com Printed on acid-free paper All Rights Reserved © 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. To Pirjo, Lauri, Eero, and Santeri Preface When I started my computing career by programming a PDP-11 computer as a freshman in the university in early 1980s, I could not have dreamed that one day I’d be able to design a processor. At that time, the freshmen were only allowed to use PDP. Next year I was given the permission to use the famous brand-new VAX-780 computer. Also, my new roommate at the dorm had got one of the first personal computers, a Commodore-64 which we started to explore together. Again, I could not have imagined that hundreds of times the processing power will be available in an everyday embedded device just a quarter of century later.
    [Show full text]
  • Social Construction and the British Computer Industry in the Post-World War II Period
    The rhetoric of Americanisation: Social construction and the British computer industry in the Post-World War II period By Robert James Kirkwood Reid Submitted to the University of Glasgow for the degree of Doctor of Philosophy in Economic History Department of Economic and Social History September 2007 1 Abstract This research seeks to understand the process of technological development in the UK and the specific role of a ‘rhetoric of Americanisation’ in that process. The concept of a ‘rhetoric of Americanisation’ will be developed throughout the thesis through a study into the computer industry in the UK in the post-war period . Specifically, the thesis discusses the threat of America, or how actors in the network of innovation within the British computer industry perceived it as a threat and the effect that this perception had on actors operating in the networks of construction in the British computer industry. However, the reaction to this threat was not a simple one. Rather this story is marked by sectional interests and technopolitical machination attempting to capture this rhetoric of ‘threat’ and ‘falling behind’. In this thesis the concept of ‘threat’ and ‘falling behind’, or more simply the ‘rhetoric of Americanisation’, will be explored in detail and the effect this had on the development of the British computer industry. What form did the process of capture and modification by sectional interests within government and industry take and what impact did this have on the British computer industry? In answering these questions, the thesis will first develop a concept of a British culture of computing which acts as the surface of emergence for various ideologies of innovation within the social networks that made up the computer industry in the UK.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Dynamicsilicon Gilder Publishing, LLC
    Written by Published by Nick Tredennick DynamicSilicon Gilder Publishing, LLC Vol. 2, No. 9 The Investor's Guide to Breakthrough Micro Devices September 2002 Lessons From the PC he worldwide market for personal computers has grown to 135 million units annually. Personal com- puters represent half of the worldwide revenue for semiconductors. In July of this year, PC makers Tshipped their billionth PC. I trace the story of the personal computer (PC) from its beginning. The lessons from the PC apply to contemporary products such as switches, routers, network processors, microprocessors, and cell phones. The story doesn’t repeat exactly because semiconductor-process advances change the rules. PC beginnings Intel introduced the first commercial microprocessor in 1971. The first microprocessors were designed solely as cost-effective substitutes for numerous chips in bills of material. But it wasn’t long before micro- processors became central processing units in small computer systems. The first advertisement for a micro- processor-based computer appeared in March 1974. Soon, companies, such as Scelbi Computer Consulting, MITS, and IMSAI, offered kit computers. Apple Computer incorporated in January 1977 and introduced the Apple II computer in April. The Apple II came fully assembled, which, together with the invention of the spreadsheet, changed the personal computer from a kit hobby to a personal business machine. In 1981, IBM legitimized personal computers by introducing the IBM Personal Computer. Once endorsed by IBM, many businesses bought personal computers. Even though it came out in August, IBM sold 15,000 units that year. Apple had a four-year head start. When IBM debuted its personal computer, the Apple II dom- inated the market.
    [Show full text]
  • Extracting and Mapping Industry 4.0 Technologies Using Wikipedia
    Computers in Industry 100 (2018) 244–257 Contents lists available at ScienceDirect Computers in Industry journal homepage: www.elsevier.com/locate/compind Extracting and mapping industry 4.0 technologies using wikipedia T ⁎ Filippo Chiarelloa, , Leonello Trivellib, Andrea Bonaccorsia, Gualtiero Fantonic a Department of Energy, Systems, Territory and Construction Engineering, University of Pisa, Largo Lucio Lazzarino, 2, 56126 Pisa, Italy b Department of Economics and Management, University of Pisa, Via Cosimo Ridolfi, 10, 56124 Pisa, Italy c Department of Mechanical, Nuclear and Production Engineering, University of Pisa, Largo Lucio Lazzarino, 2, 56126 Pisa, Italy ARTICLE INFO ABSTRACT Keywords: The explosion of the interest in the industry 4.0 generated a hype on both academia and business: the former is Industry 4.0 attracted for the opportunities given by the emergence of such a new field, the latter is pulled by incentives and Digital industry national investment plans. The Industry 4.0 technological field is not new but it is highly heterogeneous (actually Industrial IoT it is the aggregation point of more than 30 different fields of the technology). For this reason, many stakeholders Big data feel uncomfortable since they do not master the whole set of technologies, they manifested a lack of knowledge Digital currency and problems of communication with other domains. Programming languages Computing Actually such problem is twofold, on one side a common vocabulary that helps domain experts to have a Embedded systems mutual understanding is missing Riel et al. [1], on the other side, an overall standardization effort would be IoT beneficial to integrate existing terminologies in a reference architecture for the Industry 4.0 paradigm Smit et al.
    [Show full text]
  • Comparison Between CISC and RISC
    ComparisonbetweenCISCandRISC YiGao,ShilangTang,ZhongliDing {ygao1,stang2,zding1}@cs.umbc.edu ABSTRACT PerformancecomparisonbetweenRISC(ReducedInstructionSetComputer)andCISC (ComplexInstructionSetComputer)isaquitepopulartopic,andmanyconclusionsaremadein previouswork.Thispapercomparesthesetwodifferentarchitecturesinacomprehensiveway, trytocapturethepurelyarchitecturaladvantagesofRISCandCISC,andthedevelopmenttrends ofthefuturearchitectures.Ourcomparisonisnotonlybasedontheoreticalpointofview,but alsobasedonexperimentalresultstosupportourconclusions.WechooseMIPSR2000(RISC) andIntel80386(CISC)asthecomparisonmicroprocessors,wecomparethemonseveralinteger andfloating-pointbenchmarkstoverifyanddrawconclusions. 1.Introduction RISCandCISCstandfortwodifferentcompetingphilosophiesindesigningmoderncomputer architecture.Thedebatebetweenthemhasbeengoingonforalongtimeandwilllikely continue.ThedifferencebetweenRISCandCISCcanlaysonmanylevels,lotsofplausible argumentsareputforwardbybothsides,suchascodedensity,transistorcounts,memory bottlenecks,compileranddecodecomplexityetc.Thispaperintendstocomparethesetwo differentideasindetail,theirdistinctcharacters,theirpossiblespecificapplicationdomains,their currentscopeandtheirfuturedevelopmenttotheCPUdesign. TheexperimentismainlybasedontheMIPSR2000andIntel80386instructionsets,MIPS R2000isatypicalproductofpureRISCwhileIntel80386isatypicalkindofpureCISCchip. Theyappearedalmostatthesametime(mid80's),also,theyareboth32-bitprocessors,sowe choosethemasourtargets.Weselectaseriesofintegerandfloat-pointingbenchmarks,use
    [Show full text]
  • MMX™ Technology Architecture Overview
    MMX™ Technology Architecture Overview Millind Mittal, MAP Group, Santa Clara, Intel Corp. Alex Peleg, IDC Architecture Group, Israel, Intel Corp. Uri Weiser, IDC Architecture Group, Israel, Intel Corp. Index words: MMX™ technology, SIMD, IA compatibility, parallelism, media applications Abstract The definition of MMX technology evolved from earlier work in the i860™ architecture [3]. The i860 architecture Media (video, audio, graphics, communication) was the industry’s first general purpose processor to applications present a unique opportunity for provide support for graphics rendering. The i860 performance boost via use of Single Instruction Multiple processor provided instructions that operated on multiple Data (SIMD) techniques. While several of the compute- adjacent data operands in parallel, for example, four intensive parts of media applications benefit from SIMD adjacent pixels of an image. techniques, a significant portion of the code still is best suited for general purpose instruction set architectures. After the introduction of the i860 processor, Intel MMX™ technology extends the Intel Architecture (IA), explored extending the i860 architecture in order to the industry’s leading general purpose processor deliver high performance for other media applications, for architecture, to provide the benefits of SIMD for media example, image processing, texture mapping, and audio applications. and video decompression. Several of these algorithms naturally lent themselves to SIMD processing. This effort MMX technology adopts the SIMD approach in a way laid the foundation for similar support for Intel’s that makes it coexist synergistically and compatibly with mainstream general purpose architecture, IA. the IA. This makes the technology suitable for providing a boost for a large number of media applications on the The MMX technology extension was the first major leading computer platform.
    [Show full text]
  • Initial Experience with the Intel I860 Microprocessor
    Version 2.1/UPR-0184E Initial Experience with the Intel i860 Microprocessor L.D. Gladney, P.T. Keener, N.S. Lockyer, K.J. Ragan David Rittenhouse Laboratory, University of Pennsylvania, Philadelphia, PA, 19104 J.G. Heinrich, K.T. McDonald Joseph Henry Laboratories, Princeton University, Princeton, NJ, 08544 March 12, 1990 Abstract Scalar performance of the 33Mhz Intel i860 microprocessor is presented. Standard High Energy Physics programs have been ported to the i860 environment. Benchmarks have been performed and the problems encountered are discussed. Testing of the vector features of the i860 has recently started. Introduction The Intel i8601 microprocessor utilizes VLSI hardware design (> 106 transistors) with 64-bit RISC architecture to provide high computational throughput. This is the first in a family of processors being developed by Intel that is expected to achieve 200 MIPS per processor by the year 1998. 2 Our interest in the i860 is enhanced by an ongoing project at Intel Scientific Computers to produce a processor-farm architecture using the i860 with 200 Mbyte/sec data paths between nodes.3 Such an architecture, based on an array of high performance processors interconnected with high bandwidth data paths, is well suited to both online and offline computing needs of the next generation4 of High Energy Physics (HEP) experiments. 1i860, 386, and 387 are trademarks of Intel Corporation. 2L.D. Gladney et al., Proposal to the SSC Laboratory for Research and Development of a Parallel Computing Farm (Oct. 1989). 3see, for example, Federal Computer Week, Vol. 3, No. 15 (April 10, 1989). 4 The BCD Collaboration, An Intermediate and Low pT Dectector for the SSC, SSC-240.
    [Show full text]
  • 1 Predication and Speculation a Brief History of Computer Architecture
    Predication and Speculation Last time – Instruction scheduling – Profile-guided optimizations – How can we increase our scheduling window? – How can we move excepting instructions (loads) above splits? A Today – Brief history of computer architecture B s1 C – Predication and speculation move code above a split – Compiling for IA-64 CS553 Lecture Predication and Speculation 2 A Brief History of Computer Architecture The Early Years: CISC – Programmed by humans – Feature bloat: – Provide many instructions – Provide many addressing modes – Variable length instructions – Complex instructions – VAX: REMQHI, EDITPC, POLYF Problem – Difficult to implement efficiently – Difficult to pipeline – Difficult to generate good code for CS553 Lecture Predication and Speculation 3 1 A Brief History of Computer Architecture (cont) The Early 1980s: RISC – Simplify the ISA to facilitate pipelining – Uniform instruction format simplifies decoding – Uniform instructions easier to pipeline – Pipelining improves clock speeds Uniform ISA Simplifies Compilation – Stanford: Produce an architecture that leverages their strong compiler group – Berkeley: Produce an architecture that does not require heroic compilation Problems – Uncertain latency – No binary compatibility CS553 Lecture Predication and Speculation 4 A Brief History of Computer Architecture (cont) The 1990’s: Dynamic Superscalar – Simplified pipelining and more transistors enable hardware scheduling – Re-order instructions – Hardware speculation (branch prediction) – Increased issue width Note – We’re
    [Show full text]