DOCSLIB.ORG

System-On-A-Chip

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
System-On-A-Chip System-on-a-chip From Wikipedia, the free encyclopedia Jump to: navigation, search System-on-a-chip or system on chip (SoC or SOC) is an idea of integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions – all on one chip. A typical application is in the area of embedded systems. If it is not feasible to construct an SoC for a particular application, an alternative is a system in package (SiP) comprising a number of chips in a single package. SoC is believed to be more cost effective since it increases the yield of the fabrication and because its packaging is simpler. Contents [hide] • 1 Structure • 2 Design flow • 3 Fabrication • 4 See also • 5 External links [edit] Structure y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Microcontroller-based System-on-a-Chip A typical SoC consists of: • One or more microcontroller, microprocessor or DSP core(s). • Memory blocks including a selection of ROM, RAM, EEPROM and Flash. • Timing sources including oscillators and phase-locked loops. • Peripherals including counter-timers, real-time timers and power-on reset generators. • External interfaces including industry standards such as USB, FireWire, Ethernet, USART, SPI. • Analog interfaces including ADCs and DACs. • Voltage regulators and power management circuits. These blocks are connected by either a proprietary or industry-standard bus such as the AMBA bus from ARM. DMA controllers route data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC. [edit] Design flow y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 System-on-a-Chip Design Flow A SoC consists of the hardware described above, and the software that controls the microcontroller, microprocessor or DSP cores, peripherals and interfaces. The design flow for an SoC aims to develop this hardware and software in parallel. Most SoCs are developed from pre-qualified blocks for the hardware elements described above, together with the software drivers that control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB. The hardware blocks are put together using CAD tools; the software modules are integrated using a software development environment. A key step in the design flow is emulation: the hardware is mapped onto an emulation platform based on a field programmable gate array (FPGA) that mimics the behavior of the SoC, and the software modules are loaded into the memory of the emulation platform. Once programmed, the emulation platform enables the hardware and software of the SoC to be tested and debugged at close to its full operational speed. After emulation the hardware of the SoC follows the place and route phase of the design of an integrated circuit before it is fabricated. Chips are verified for logical correctness before being sent to foundry. The process is called ASIC verification. Verilog and VHDL are the Hardware Descriptive languages used for verification. With growing complexity of Chips HVLs like SystemVerilog, SystemC, e, Vera are used. The bugs found in the verification stage are reported to the y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 designer. Traditionally, 70% of time and energy in chip design life cycle are spent on verification. [citation needed] [edit] Fabrication SoCs can be fabricated by several technologies, including: • Full-custom • Standard cell • FPGA SoC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well. However, like most VLSI designs, the total cost is higher for one large chip than for the same functionality distributed over several smaller chips, because of lower yields and higher NRE costs. [edit] See also • List of system-on-a-chip suppliers • PSoC • ASIC • Microcontroller • Electronic design automation • NES-on-a-chip [edit] External links • SoC Article Series • TSC electric power meter IC- a typical mixed-signal system on chip • MIPS-based SoCs at linux-mips.org • Embedded Processor and System-on-Chip Quick Reference Guide • System-on-a-Chip by www.SiliconFarEast.com • Navarre AsyncArt. Asynchronous System-on-Programmable-Chip Research & Services. Public University of Navarre • HybridThreads(Hthreads) Programmatically building semi-custom multiprocessor systems-on-chip using hybrid CPU/FPGA components. • Systems-on-chip using hybrid CPU/FPGA components. y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Microcontroller From Wikipedia, the free encyclopedia Jump to: navigation, search It has been suggested that this article or section be merged with embedded microprocessor. (Discuss) The integrated circuit from an Intel 8742, an 8-bit microcontroller that includes a CPU running at 12 MHz, 128 bytes of RAM, 2048 bytes of EPROM, and I/O in the same chip. A microcontroller (or MCU) is a computer-on-a-chip. It is a type of microprocessor emphasizing self-sufficiency and cost-effectiveness, in contrast to a general-purpose microprocessor (the kind used in a PC). The only difference between a microcontroller and a microprocessor is that a microprocessor has three parts - ALU, Control Unit and registers (like memory), but the microcontroller has additional elements like ROM, RAM etc. Contents [hide] • 1 Embedded design • 2 Higher Integration • 3 Large Volumes • 4 Programming Environments • 5 Interrupt Latency • 6 History • 7 Development platforms for hobbyists o 7.1 Arduino o 7.2 Platforms from Parallax, Inc. o 7.3 PICAXE o 7.4 A-WIT Technologies, Inc. o 7.5 Comfile Technology Inc. y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 o 7.6 Coridium ARMexpress o 7.7 ZX-24, ZX-40, ZX-44 • 8 Notes • 9 See also • 10 External links • 11 External links [edit] Embedded design The maJority of computer systems in use today are embedded in other machinery, such as telephones, clocks, appliances, vehicles, and infrastructure. An embedded system usually has minimal requirements for memory and program length and may require simple but unusual input/output systems. For example, most embedded systems lack keyboards, screens, disks, printers, or other recognizable I/O devices of a personal computer. They may control electric motors, relays or voltages, and read switches, variable resistors or other electronic devices. Often, the only I/O device readable by a human is a single light- emitting diode, and severe cost or power constraints can even eliminate that. [edit] Higher Integration In contrast to general-purpose CPUs, microcontrollers may not implement an external address or data bus, because they integrate RAM and non-volatile memory on the same chip as the CPU. Because they need fewer pins, the chip can be placed in a much smaller, cheaper package. Integrating the memory and other peripherals on a single chip and testing them as a unit increases the cost of that chip, but often results in decreased net cost of the embedded system as a whole. (Even if the cost of a CPU that has integrated peripherals is slightly more than the cost of a CPU + external peripherals, having fewer chips typically allows a smaller and cheaper circuit board, and reduces the labor required to assemble and test the circuit board). A microcontroller is a single integrated circuit, commonly with the following features: • central processing unit - ranging from small and simple 4-bit processors to sophisticated 32- or 64-bit processors • input/output interfaces such as serial ports (UARTs) • other serial communications interfaces like I²C, Serial Peripheral Interface and Controller Area Network for system interconnect • peripherals such as timers and watchdog • RAM for data storage • ROM, EPROM, EEPROM or Flash memory for program storage • clock generator - often an oscillator for a quartz timing crystal, resonator or RC circuit y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • many include analog-to-digital converters This integration drastically reduces the number of chips and the amount of wiring and PCB space that would be needed to produce equivalent systems using separate chips and have proved to be highly popular in embedded systems since their introduction in the 1970s. Some microcontrollers can afford to use a Harvard architecture: separate memory buses for instructions and data, allowing accesses to take place concurrently. The decision of which peripheral to integrate is often difficult. The Microcontroller vendors often trade operating frequencies and system design flexibility against time-to- market requirements from their customers and overall lower system cost. Manufacturers have to balance the need to minimize the chip size against additional functionality. Microcontroller architectures are available from many different vendors in so many varieties that each instruction set architecture could rightly belong to a category of their own. Chief among these are the 8051, Z80 and ARM derivatives.[citation needed] [edit] Large Volumes Microcontrollers take the largest share of sales in the wider microprocessor market. Over 50% are "simple" controllers, and another 20% are more specialized digital signal processors (DSPs) [citation needed]. A typical home in a developed country is likely to have only one or two general-purpose microprocessors but somewhere between one and two dozen microcontrollers. A typical mid range automobile has as many as 50 or more microcontrollers. They can also be found in almost any electrical device: washing machines, microwave ovens, telephones etc. A PIC 18F8720 microcontroller in an 80-pin TQFP package. Manufacturers have often produced special versions of their microcontrollers in order to help the hardware and software development of the target system.
Load more

Recommended publications
  • DRAM EMAIL GIM Teams!!!/Teaming Issues •Memories in Verilog •Memories on the FPGA
    Memories & More •Overview of Memories •External Memories •SRAM (async, sync) •Flash •DRAM EMAIL GIM teams!!!/teaming Issues •Memories in Verilog •Memories on the FPGA 10/18/18 6.111 Fall 2018 1 Memories: a practical primer • The good news: huge selection of technologies • Small & faster vs. large & slower • Every year capacities go up and prices go down • Almost cost competitive with hard disks: high density, fast flash memories • Non-volatile, read/write, no moving parts! (robust, efficient) • The bad news: perennial system bottleneck • Latencies (access time) haven’t kept pace with cycle times • Separate technology from logic, so must communicate between silicon, so physical limitations (# of pins, R’s and C’s and L’s) limit bandwidths • New hopes: capacitive interconnect, 3D IC’s • Likely the limiting factor in cost & performance of many digital systems: designers spend a lot of time figuring out how to keep memories running at peak bandwidth • “It’s the memory - just add more faster memory” 10/18/18 6.111 Fall 2018 2 How do we Electrically Remember Things? • We can convey/transfer information with voltages that change over time • How can we store information in an electrically accessible manner? • Store in either: • Electric Field • Magnetic Field 10/18/18 6.111 Fall 2018 3 Mostly focus on rewritable • Punched Cards have existed as electromechanical program storage since ~1800s • We’re mostly concerned with rewritable storage mechanisms today (cards were true Computer program in punched card format ROMs) https://en.wiKipedia.org/wiKi/Computer_programming_in_the_
    [Show full text]
  • VOLUME V INFORMATIQUE NON AMERICAINE Première Partie Par L' Ingénieur Général De L'armement BOUCHER Henri TABLE
    VOLUME V INFORMATIQUE NON AMERICAINE Première partie par l' Ingénieur Général de l'Armement BOUCHER Henri TABLE DES MATIERES INFORMATIQUE NON AMERICAINE Première partie 731 Informatique européenne (statistiques, exemples) 122 700 Histoire de l'Informatique allemande 1 701 Petits constructeurs 5 702 Les facturières de Kienzle Data System 16 703 Les minis de gestion de Nixdorf 18 704 Siemens & Halske AG 23 705 Systèmes informatiques d'origine allemande 38 706 Histoire de l'informatique britannique 40 707 Industriels anglais de l'informatique 42 708 Travaux des Laboratoires d' Etat 60 709 Travaux universitaires 63 710 Les coeurs synthétisables d' ARM 68 711 Computer Technology 70 712 Elliott Brothers et Elliott Automation 71 713 Les machines d' English Electric Company 74 714 Les calculateurs de Ferranti 76 715 Les études de General Electric Company 83 716 La patiente construction de ICL 85 Catalogue informatique – Volume E - Ingénieur Général de l'Armement Henri Boucher Page : 1/333 717 La série 29 d' ICL 89 718 Autres produits d' ICL, et fin 94 719 Marconi Company 101 720 Plessey 103 721 Systèmes en Grande-Bretagne 105 722 Histoire de l'informatique australienne 107 723 Informatique en Autriche 109 724 Informatique belge 110 725 Informatique canadienne 111 726 Informatique chinoise 116 727 Informatique en Corée du Sud 118 728 Informatique à Cuba 119 729 Informatique danoise 119 730 Informatique espagnole 121 732 Informatique finlandaise 128 733 Histoire de l'informatique française 130 734 La période héroïque : la SEA 140 735 La Compagnie
    [Show full text]
  • SIMD Extensions
    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
    [Show full text]
  • HELLAS: a Specialized Architecture for Interactive Deformable Object Modeling
    HELLAS: A Specialized Architecture for Interactive Deformable Object Modeling Shrirang Yardi Benjamin Bishop Thomas Kelliher Department of Electrical and Department of Computing Department of Mathematics Computer Engineering Sciences and Computer Science Virginia Tech University of Scranton Goucher College Blacksburg, VA Scranton, PA Baltimore, MD [email protected] [email protected] [email protected] ABSTRACT more realistic models, it is likely that the computational Applications involving interactive modeling of deformable resources required by these simulations may continue to ex- objects require highly iterative, floating-point intensive nu- ceed those provided by the incremental advances in general- merical simulations. As the complexity of these models in- purpose systems [12]. This has created an interest in the creases, the computational power required for their simula- use of specialized hardware that provides high performance tion quickly grows beyond the capabilities of current gen- computational engines to accelerate such floating-point in- eral purpose systems. In this paper, we present the design tensive applications [6, 7]. of a low–cost, high–performance, specialized architecture to Our research focuses on the design of such specialized sys- accelerate these simulations. Our aim is to use such special- tems. However, our approach has several important differ- ized hardware to allow complex interactive physical model- ences as compared to previous work in this area: (i) we ing even on consumer-grade PCs. In this paper, we present specifically target algorithms that are numerically stable, details of the target algorithms, the HELLAS architecture, but are much more computationally intensive than those simulation results and lessons learned from our implemen- used by existing hardware implementations [3,6]; (ii) we aim tation.
    [Show full text]
  • Pwny Documentation Release 0.9.0
    pwny Documentation Release 0.9.0 Author Nov 19, 2017 Contents 1 pwny package 3 2 pwnypack package 5 2.1 asm – (Dis)assembler..........................................5 2.2 bytecode – Python bytecode manipulation..............................7 2.3 codec – Data transformation...................................... 11 2.4 elf – ELF file parsing.......................................... 16 2.5 flow – Communication......................................... 36 2.6 fmtstring – Format strings...................................... 41 2.7 marshal – Python marshal loader................................... 42 2.8 oracle – Padding oracle attacks.................................... 43 2.9 packing – Data (un)packing...................................... 44 2.10 php – PHP related functions....................................... 46 2.11 pickle – Pickle tools.......................................... 47 2.12 py_internals – Python internals.................................. 49 2.13 rop – ROP gadgets........................................... 50 2.14 shellcode – Shellcode generator................................... 50 2.15 target – Target definition....................................... 79 2.16 util – Utility functions......................................... 80 3 Indices and tables 83 Python Module Index 85 i ii pwny Documentation, Release 0.9.0 pwnypack is the official CTF toolkit of Certified Edible Dinosaurs. It aims to provide a set of command line utilities and a python library that are useful when playing hacking CTFs. The core functionality of pwnypack
    [Show full text]
  • Magnetic Recording and Readout Memory
    SNS college of Technology Coimbatore-641 035 MAGNETIC RECORDING AND READOUT MEMORY Nowadays, large number of information are stored in (or) retrieved from the storage devices, by using devices is magnetic recording heads and they function according to the principle of magnetic induction. Generally Ferro or Ferrimagnetic materials are used in the storage devices because in this type of materials only the magnetic interaction between only two dipoles align themselves parallel to each other. Due to this parallel alignment even if we apply small amount of magnetic field, a large value of magnetization is produced. By using this property information are stored in storage devices. In the storage devices, the recording of digital data (0‟s and 1‟s) depends upon the direction of magnetization in the medium. Magnetic parameters for Recording 1. When current is passed through a coil, a magnetic field is induced. This principle called “Electromagnetic Induction” is used in storage devices. 2. The case with which the material can be magnetized is another parameter. 3. We know the soft magnetic materials are the materials which can easily be magnetized and demagnetized. Hence a data can be stored and erased easily. Such magnetic materials are used in temporary storage devices. 4. Similarly, we know hard magnetic materials cannot be easily magnetized and demagnetized. So such magnetic materials are used in permanent storage devices. 5. In soft magnetic materials, the electrical resistance varies with respect to the magnetization and this effect is called magneto-resistance. This parameter is used in specific thin film systems. 19PYB102 & PHYSICS OF MATERIALS AND PHOTONICS D.SENGOTTAIYAN /AP/PHYSICS Page 1 SNS college of Technology Coimbatore-641 035 The magnetic medium is made of magnetic materials (Ferro or Ferric oxide) deposited on this plastic.
    [Show full text]
  • Metal Ultrasonic Delay Lines
    Research Paper 2453 rOOmOI of R~eo"h of The NO tiO ~;;:if ~;=asoni;l~~i~;~~~:: Russell W . Mebs, John H. Darr, and John D. Grimsley A study was made of the applicability of a number of metals and a lloys for therm all y stable ultrasonic delay lin es. A preliminary iavestigation was made of different types of pressure holders and ad­ hesi ves for use in crystal t ransducer attachments and of the iafluence of specimen length on attenuation for valious m etals and alloy. The effect of cold-work, annealing, and specimen cross section on attenuation was a lso determined for a representati ve isoelastic alloy. Measurements of temperature variation of signal attenuation, distort ion, a nd delay t im e on a number of assembled delay lines indicated t hat an isoelastic a lloy employing over cured epoxy-resin crystal attachments gave best over-all t ransmission characteristics. No correlation was obtainable between strength and SOLl nd-transmission characteristics with varioLls cemented joints. 1. Introduction variations in pulse attenuation and distortion with acceleration or change of temperature. The ultrasonic delay line has come into wide use Only a general survey will be given of the basic in recent years with the development of radar, com­ theory of ultrasonic transmission as related to delay ~uters , and other electronic devices [1 , 2, 3, 4V It lines of 50 tLsec or less. More comprehensive 's a means for delaying a signal for a predetermined treatments have been given elsewhere [2, 4, and 5]. ~hort period to be accurately reproduced for use at _tn appropriate later instant.
    [Show full text]
  • Ece585 Lec2.Pdf
    ECE 485/585 Microprocessor System Design Lecture 2: Memory Addressing 8086 Basics and Bus Timing Asynchronous I/O Signaling Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F. Basic I/O – Part I ECE 485/585 Outline for next few lectures Simple model of computation Memory Addressing (Alignment, Byte Order) 8088/8086 Bus Asynchronous I/O Signaling Review of Basic I/O How is I/O performed Dedicated/Isolated /Direct I/O Ports Memory Mapped I/O How do we tell when I/O device is ready or command complete? Polling Interrupts How do we transfer data? Programmed I/O DMA ECE 485/585 Simplified Model of a Computer Control Control Data, Address, Memory Data Path Microprocessor Keyboard Mouse [Fetch] Video display [Decode] Printer [Execute] I/O Device Hard disk drive Audio card Ethernet WiFi CD R/W DVD ECE 485/585 Memory Addressing Size of operands Bytes, words, long/double words, quadwords 16-bit half word (Intel: word) 32-bit word (Intel: doubleword, dword) 0x107 64-bit double word (Intel: quadword, qword) 0x106 Note: names are non-standard 0x105 SUN Sparc word is 32-bits, double is 64-bits 0x104 0x103 Alignment 0x102 Can multi-byte operands begin at any byte address? 0x101 Yes: non-aligned 0x100 No: aligned. Low order address bit(s) will be zero ECE 485/585 Memory Operand Alignment …Intel IA speak (i.e. word = 16-bits = 2 bytes) 0x107 0x106 0x105 0x104 0x103 0x102 0x101 0x100 Aligned Unaligned Aligned Unaligned Aligned Unaligned word word Double Double Quad Quad address address word word word word -----0 address address address address -----00 ----000 ECE 485/585 Memory Operand Alignment Why do we care? Unaligned memory references Can cause multiple memory bus cycles for a single operand May also span cache lines Requiring multiple evictions, multiple cache line fills Complicates memory system and cache controller design Some architectures restrict addresses to be aligned Even in architectures without alignment restrictions (e.g.
    [Show full text]
  • DSP56303 Product Brief, Rev
    Freescale Semiconductor DSP56303PB Product Brief Rev. 2, 2/2005 DSP56303 24-Bit Digital Signal Processor 16 6 6 3 Memory Expansion Area The DSP56303 is intended Triple X Data HI08 ESSI SCI PrograM Y Data for use in telecommunication Timer RAM RAM RAM 4096 × 24 2048 × 24 2048 × 24 applications, such as multi- bits bits bits line voice/data/ fax (default) (default) (default) processing, video Peripheral Expansion Area conferencing, audio PM_EB XM_EB PIO_EB YAB YM_EB applications, control, and Address External 18 Generation XAB Address general digital signal Unit PAB Bus Address Six-Channel DAB Switch processing. DMA Unit External 24-Bit Bus 13 Bootstrap DSP56300 Interface ROM and Inst. Core Cache Control Control DDB 24 Internal YDB External Data XDB Data Bus Bus PDB Switch Data Switch GDB EXTAL Power Clock Management Data ALU 5 Generator Program Program Program × + → XTAL Interrupt Decode Address 24 24 56 56-bit MAC JTAG PLL Two 56-bit Accumulators Controller Controller Generator 56-bit Barrel Shifter OnCE™ DE 2 MODA/IRQA MODB/IRQB RESET MODC/IRQC PINIT/NMI MODD/IRQD Figure 1. DSP56303 Block Diagram The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56303 offers 100 million multiply-accumulates per second (MMACS) using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable wireless, telecommunications, and multimedia products.
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • Magnetic Storage- Magnetic-Core Memory, Magnetic Tape,RAM
    Magnetic storage- From magnetic tape to HDD Juhász Levente 2016.02.24 Table of contents 1. Introduction 2. Magnetic tape 3. Magnetic-core memory 4. Bubble memory 5. Hard disk drive 6. Applications, future prospects 7. References 1. Magnetic storage - introduction Magnetic storage: Recording & storage of data on a magnetised medium A form of „non-volatile” memory Data accessed using read/write heads Widely used for computer data storage, audio and video applications, magnetic stripe cards etc. 1. Magnetic storage - introduction 2. Magnetic tape 1928 Germany: Magnetic tape for audio recording by Fritz Pfleumer • Fe2O3 coating on paper stripes, further developed by AEG & BASF 1951: UNIVAC- first use of magnetic tape for data storage • 12,7 mm Ni-plated brass-phosphorus alloy tape • 128 characters /inch data density • 7000 ch. /s writing speed 2. Magnetic tape 2. Magnetic tape 1950s: IBM : patented magnetic tape technology • 12,7 mm wide magnetic tape on a 26,7 cm reel • 370-730 m long tapes 1980: 1100 m PET –based tape • 18 cm reel for developers • 7, 9 stripe tapes (8 bit + parity) • Capacity up to 140 MB DEC –tapes for personal use 2. Magnetic tape 2014: Sony & IBM recorded 148 Gbit /squareinch tape capacity 185 TB! 2. Magnetic tape Remanent structural change in a magnetic medium Analog or digital recording (binary storage) Longitudinal or perpendicular recording Ni-Fe –alloy core in tape head 2. Magnetic tape Hysteresis in magnetic recording 40-150 kHz bias signal applied to the tape to remove its „magnetic history” and „stir” the magnetization Each recorded signal will encounter the same magnetic condition Current in tape head proportional to the signal to be recorded 2.
    [Show full text]
  • Department of Electrical Engineering
    Display of digitally processed data Item Type text; Thesis-Reproduction (electronic) Authors Jurich, Samuel, 1929- Publisher The University of Arizona. Rights Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. Download date 23/09/2021 17:48:33 Link to Item http://hdl.handle.net/10150/551403 DISPLAY OP DIGITALLY PROCESSED DATA ■ v : ' hJ Sarauel Jurlch A Thesis Submitted to the Faculty of the : - ‘ DEPARTMENT OF ELECTRICAL ENGINEERING In Partial Fulfillment of the Requirements For the Degree of : o ' MASTER OF SCIENCE : ' In the Graduate College A UNIVERSITY OF ARIZONA 1 9 5 9 This thesis has been submitted in partial fulfillment of requirements for an advanced degree at the University of Arizona and is deposited in the University Library to be made available to borrowers under rules of the Library. Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgment of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in their judgment the proposed use of the material is in the interests of scholarship. In all other instances, however, permission must be obtained from the author. SIGNED: This thesis has been approved on the date shown below: 6 4f/?y /9S~<7 John R.
    [Show full text]