System-on-a-chip
From Wikipedia, the free encyclopedia
Jump to: navigation, search
System-on-a-chip or system on chip (SoC or SOC) is an idea of integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed signal, and often radio frequency functions – all on one chip. A typical application is in the area of embedded systems.
If it is not feasible to construct an SoC for a particular application, an alternative is a system in package (SiP) comprising a number of chips in a single package. SoC is believed to be more cost effective since it increases the yield of the fabrication and because its packaging is simpler.
Contents
[hide]
• 1 Structure • 2 Design flow • 3 Fabrication • 4 See also • 5 External links
[edit] Structure
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007
Microcontroller based System on a Chip
A typical SoC consists of:
• One or more microcontroller, microprocessor or DSP core(s). • Memory blocks including a selection of ROM, RAM, EEPROM and Flash. • Timing sources including oscillators and phase locked loops. • Peripherals including counter timers, real time timers and power on reset generators. • External interfaces including industry standards such as USB, FireWire, Ethernet, USART, SPI. • Analog interfaces including ADCs and DACs. • Voltage regulators and power management circuits.
These blocks are connected by either a proprietary or industry standard bus such as the AMBA bus from ARM. DMA controllers route data directly between external interfaces and memory, by passing the processor core and thereby increasing the data throughput of the SoC. [edit] Design flow
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007
System on a Chip Design Flow
A SoC consists of the hardware described above, and the software that controls the microcontroller, microprocessor or DSP cores, peripherals and interfaces. The design flow for an SoC aims to develop this hardware and software in parallel.
Most SoCs are developed from pre qualified blocks for the hardware elements described above, together with the software drivers that control their operation. Of particular importance are the protocol stacks that drive industry standard interfaces like USB. The hardware blocks are put together using CAD tools; the software modules are integrated using a software development environment.
A key step in the design flow is emulation: the hardware is mapped onto an emulation platform based on a field programmable gate array (FPGA) that mimics the behavior of the SoC, and the software modules are loaded into the memory of the emulation platform. Once programmed, the emulation platform enables the hardware and software of the SoC to be tested and debugged at close to its full operational speed.
After emulation the hardware of the SoC follows the place and route phase of the design of an integrated circuit before it is fabricated.
Chips are verified for logical correctness before being sent to foundry. The process is called ASIC verification. Verilog and VHDL are the Hardware Descriptive languages used for verification. With growing complexity of Chips HVLs like SystemVerilog, SystemC, e, Vera are used. The bugs found in the verification stage are reported to the
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 designer. Traditionally, 70% of time and energy in chip design life cycle are spent on verification. [citation needed] [edit] Fabrication
SoCs can be fabricated by several technologies, including:
• Full custom • Standard cell • FPGA
SoC designs usually consume less power and have a lower cost and higher reliability than the multi chip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well.
However, like most VLSI designs, the total cost is higher for one large chip than for the same functionality distributed over several smaller chips, because of lower yields and higher NRE costs. [edit] See also
• List of system on a chip suppliers • PSoC • ASIC • Microcontroller • Electronic design automation • NES on a chip [edit] External links
• SoC Article Series • TSC electric power meter IC a typical mixed signal system on chip • MIPS based SoCs at linux mips.org • Embedded Processor and System on Chip Quick Reference Guide • System on a Chip by www.SiliconFarEast.com • Navarre AsyncArt. Asynchronous System on Programmable Chip Research & Services. Public University of Navarre • HybridThreads(Hthreads) Programmatically building semi custom multiprocessor systems on chip using hybrid CPU/FPGA components. • Systems on chip using hybrid CPU/FPGA components.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Microcontroller
From Wikipedia, the free encyclopedia
Jump to: navigation, search
It has been suggested that this article or section be merged with embedded microprocessor. (Discuss)
The integrated circuit from an Intel 8742, an 8 bit microcontroller that includes a CPU running at 12 MHz, 128 bytes of RAM, 2048 bytes of EPROM, and I/O in the same chip.
A microcontroller (or MCU) is a computer on a chip. It is a type of microprocessor emphasizing self sufficiency and cost effectiveness, in contrast to a general purpose microprocessor (the kind used in a PC). The only difference between a microcontroller and a microprocessor is that a microprocessor has three parts ALU, Control Unit and registers (like memory), but the microcontroller has additional elements like ROM, RAM etc.
Contents
[hide]
• 1 Embedded design • 2 Higher Integration • 3 Large Volumes • 4 Programming Environments • 5 Interrupt Latency • 6 History • 7 Development platforms for hobbyists o 7.1 Arduino o 7.2 Platforms from Parallax, Inc. o 7.3 PICAXE o 7.4 A WIT Technologies, Inc. o 7.5 Comfile Technology Inc.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 o 7.6 Coridium ARMexpress o 7.7 ZX 24, ZX 40, ZX 44 • 8 Notes • 9 See also • 10 External links • 11 External links
[edit] Embedded design
The majority of computer systems in use today are embedded in other machinery, such as telephones, clocks, appliances, vehicles, and infrastructure. An embedded system usually has minimal requirements for memory and program length and may require simple but unusual input/output systems. For example, most embedded systems lack keyboards, screens, disks, printers, or other recognizable I/O devices of a personal computer. They may control electric motors, relays or voltages, and read switches, variable resistors or other electronic devices. Often, the only I/O device readable by a human is a single light emitting diode, and severe cost or power constraints can even eliminate that. [edit] Higher Integration
In contrast to general purpose CPUs, microcontrollers may not implement an external address or data bus, because they integrate RAM and non volatile memory on the same chip as the CPU. Because they need fewer pins, the chip can be placed in a much smaller, cheaper package.
Integrating the memory and other peripherals on a single chip and testing them as a unit increases the cost of that chip, but often results in decreased net cost of the embedded system as a whole. (Even if the cost of a CPU that has integrated peripherals is slightly more than the cost of a CPU + external peripherals, having fewer chips typically allows a smaller and cheaper circuit board, and reduces the labor required to assemble and test the circuit board).
A microcontroller is a single integrated circuit, commonly with the following features:
• central processing unit ranging from small and simple 4 bit processors to sophisticated 32 or 64 bit processors • input/output interfaces such as serial ports (UARTs) • other serial communications interfaces like I²C, Serial Peripheral Interface and Controller Area Network for system interconnect • peripherals such as timers and watchdog • RAM for data storage • ROM, EPROM, EEPROM or Flash memory for program storage • clock generator often an oscillator for a quartz timing crystal, resonator or RC circuit
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • many include analog to digital converters
This integration drastically reduces the number of chips and the amount of wiring and PCB space that would be needed to produce equivalent systems using separate chips and have proved to be highly popular in embedded systems since their introduction in the 1970s.
Some microcontrollers can afford to use a Harvard architecture: separate memory buses for instructions and data, allowing accesses to take place concurrently.
The decision of which peripheral to integrate is often difficult. The Microcontroller vendors often trade operating frequencies and system design flexibility against time to market requirements from their customers and overall lower system cost. Manufacturers have to balance the need to minimize the chip size against additional functionality.
Microcontroller architectures are available from many different vendors in so many varieties that each instruction set architecture could rightly belong to a category of their own. Chief among these are the 8051, Z80 and ARM derivatives.[citation needed] [edit] Large Volumes
Microcontrollers take the largest share of sales in the wider microprocessor market. Over 50% are "simple" controllers, and another 20% are more specialized digital signal processors (DSPs) [citation needed]. A typical home in a developed country is likely to have only one or two general purpose microprocessors but somewhere between one and two dozen microcontrollers. A typical mid range automobile has as many as 50 or more microcontrollers. They can also be found in almost any electrical device: washing machines, microwave ovens, telephones etc.
A PIC 18F8720 microcontroller in an 80 pin TQFP package.
Manufacturers have often produced special versions of their microcontrollers in order to help the hardware and software development of the target system. These have included EPROM versions that have a "window" on the top of the device through which program memory can be erased by ultra violet light, ready for reprogramming after a programming
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 ("burn") and test cycle. Other versions may be available where the ROM is accessed as an external device rather than as internal memory. A simple EPROM programmer, rather than a more complex and expensive microcontroller programmer, may then be used, however there is a potential loss of functionality through pin outs being tied up with external memory addressing rather than for general input/output. These kind of devices usually carry a cost up in part prices but if the target production quantities are small, certainly in the case of a hobbyist, they can be the most economical option compared with the set up charges involved in mask programmed devices. A more rarely encountered development microcontroller is the "piggy back" version. This device has no internal ROM memory; instead pin outs on the top of the microcontroller form a socket into which a standard EPROM program memory device may be installed. The benefit of this approach is the release of microcontroller pins for input and output use rather than program memory. These kinds of devices are normally expensive and are impractical for anything but the development phase of a project. [edit] Programming Environments
Originally, microcontrollers were only programmed in assembly language, or later in C code. Recent microcontrollers integrated with on chip debug circuitry accessed by In circuit emulator via JTAG enables a programmer to debug the software of an embedded system with a debugger.
Some microcontrollers have begun to include a built in high level programming language interpreter for greater ease of use. The Intel 8052 and Zilog Z8 were available with BASIC very early on, and BASIC is more recently used in the popular BASIC Stamp MCUs.
Some microcontrollers such as Analog Device's Blackfin processors can be programmed using LabVIEW, which is a high level programming language. [edit] Interrupt Latency
In contrast to general purpose computers, microcontrollers used in embedded systems often seek to minimize interrupt latency over instruction throughput.
When an electronic device causes an interrupt, the intermediate results, the registers, have to be saved before the software responsible for handling the interrupt can run, and then must be put back after it is finished. If there are more registers, this saving and restoring process takes more time, increasing the latency.
Low latency CPUs generally have relatively few registers in their central processing units, or they have "shadow registers" that are only used by the interrupt software. [edit] History
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 This short section requires expansion.
First microcontroller was Intel 8048 released in 1976. [edit] Development platforms for hobbyists
This article or section is written like an advertisement. Please help rewrite this article from a neutral point of view per Wikipedia policy. Mark blatant advertising for speedy deletion with {{db spam}}. (help, talk)
For almost every manufacturer of bare microcontrollers, there are a dozen little companies repacking its products into more hobbyist friendly packages. Their product is often an MCU preloaded with a BASIC or similar interpreter, soldered onto a Dual Inline Pin board along with a power regulator and other goodies. PICmicros seem to be very popular here, possibly due to good static protection. More powerful examples (e.g. faster execution, more RAM and code space) seem to be based on Atmel AVR or Hitachi chips and now ARM.
[edit] Arduino
Arduino is an open source physical computing platform based on a simple input/output board and a development environment that implements the Processing/Wiring language. Arduino can be used to develop stand alone interactive objects or can be connected to software on your computer (e.g. Flash, Processing, MaxMSP). The boards can be assembled by hand or purchased preassembled; the open source IDE can be downloaded for free. Arduino uses an ATmega8 or ATmega168 microcontroller from Atmel's Atmel AVR series.
[edit] Platforms from Parallax, Inc.
BASIC Stamp by Parallax, is the 'big name' in BASIC microcontrollers.[citation needed] They are Microchip PIC micros programmed with an interpreter that processes the program stored in an external EEPROM. Several different modules are available of varying processing speeds, RAM, and EEPROM sizes. Most popular is the original BASIC Stamp 2 module. The BASIC Stamp is used by Parallax as a platform for introductory programming and robotic kits.
SX Key, Parallax's development tool for the SX line of microcontrollers, supporting every SX chip commercially available. Using free SX Key software (Assembly language), or the SX/B Compiler (BASIC style language) from Parallax, the SX Key programming tool can program SX chips in system and perform in circuit source level debugging.
Propeller, A multi core microcontroller developed by Parallax, Inc. It features eight 32bit cores and 32 I/O pins in the currently released version. Each core operates independently
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 at 80Mhz, it is programmed in a language named SPIN(tm) which was developed by Parallax to support this unique micro.
[edit] PICAXE
This PICAXE range of controllers from Revolution Education Limited[1] are based upon Microchip PICmicro's programmed with a BASIC interpreter. Using internal EEPROM or Flash to store the user's program they deliver a single chip solution and are quite inexpensive. A PICAXE programmer is simply a serial plug plus two resistors. Complete development software, comprehensive documentation and application notes are all available free of charge.
The BASIC like programming language is almost identical to that used by Parallax's Basic Stamp 1 (BS1) but has been enhanced to support on chip hardware and additional functionality. In common with the BS1 programming language, the PICAXE has support only for a limited number of variables, but allows access to internal RAM for storage which helps overcome that limitation.
The 5.0.X versions of the Visual IDE ( the Programming Editor ) introduced 'enhanced compilers' which support block structured programming constructs plus conditional compilation and other directives.
Initially targeted at the UK educational sector, use of the PICAXE has spread to hobbyists, semi professionals and it can also be found inside commercial products. With its user base in many countries, the PICAXE has steadily gained a good international reputation.
[edit] A-WIT Technologies, Inc.
A WIT Technologies, Inc.[2] has a microcontroller module named the C STAMP, along with support boards, kits, and software tools and infrastructure. The C STAMP is designed around a PIC microcontroller, and is programmed in a very user friendly subset of the standard C language called WC that is easy and powerful, because it relies on A WIT's supplied software infrastructure. This microcontroller module is very affordable, and it has 48 pins, 35 KiB of memory, and runs at 40 MHz. The C STAMP also has a vast array of accessories and components, which are supported by A WIT's software interfaces that enables seamless connectivity. This, in turn, enhances the ease of complete system development.
[edit] Comfile Technology Inc.
Comfile Technology Inc.[3] produces a series of microcontrollers branded as CUBLOC and CuTOUCH, using the Atmel ATmega128 processor. They are very price competitive, being aimed at industrial applications, and include features such as Ladder Logic in addition to BASIC, a 80 kB program memory, and hardware pulse width modulation. Their focus is on developing industrial controllers which are fast, easy to use, and
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 versatile. Comfile Technology's CuTOUCH is a visual Touch screen controller that can be programmed in BASIC and Ladder Logic.
[edit] Coridium ARMexpress
ARMexpress[4] is the first of a new family of DIP 24 (stamp sized) controllers that combine a 60 MHz ARM CPU with a builtin BASIC compiler to achieve new levels of performance in this form factor. This combination makes this simple to use but very fast controller a good choice for the prototype builder or system integrator. 40K of code and 40K of data are available to the user, and code speed rivals that of programs written in C. The dialect of BASIC conforms more to Visual BASIC, but has hardware extensions like PBASIC.
[edit] ZX-24, ZX-40, ZX-44
The ZX series[5] MCUs are based on the Atmel ATmega32 and ATmega644 processors. The devices run a field upgradable Virtual Machine that features built in multi tasking, 32 bit floating point math and 1.5K to 3.5K of RAM for user's programs. Multi tasking facilitates a more structured approach to coding for interface devices that require prompt service, e.g. serial devices, infrared remotes, etc.
The programming language for the ZX series is ZBasic, a modern dialect of Basic modeled after Microsoft's Visual Basic. The biggest improvement over the typical MCU Basic dialect is the availability of parameterized subroutines/functions that support local variables. Strong type checking is another improvement that aids in writing correct programs more quickly. User defined types (structures) are also supported along with aliases, based variables, sub byte data types (Bit and Nibble) and other advanced capabilities. [edit] Notes
1. ^ Revolution Education Limited 2. ^ A WIT Technologies, Inc. 3. ^ Comfile Technology Inc. 4. ^ ARMexpress 5. ^ Official ZBasic and ZX website [edit] See also
• Embedded system • Microarchitecture • In circuit emulator (ICE) • List of common microcontrollers • Microbotics
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • Contiki – A small footprint open source, yet fully featured, operating system developed for use on a number of smallish to large industrial systems ranging from 8 bit computers to embedded microcontrollers. [edit] External links
• Michael Barr's Embedded Systems Glossary • Embedded Systems Design magazine
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Microprocessor
From Wikipedia, the free encyclopedia
Jump to: navigation, search Microprocessor
Die of an Intel 80486DX2 microprocessor (actual size: 12×6.75 mm) in its packaging Late 1960s/Early 1970s Date (see article for Invented: explanation) Connects to:
• Motherboard via one of o Socket o Integration o DIP o Others
Architectures:
• x86 • x64 • Others
Common Manufacturers:
• Intel • AMD
A microprocessor is a programmable digital electronic component that incorporates the functions of a central processing unit (CPU) on a single semiconducting integrated circuit (IC). The microprocessor was born by reducing the word size of the CPU from 32 bits to 4 bits, so that the transistors of its logic circuits would fit onto a single part. One or more
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 microprocessors typically serve as the CPU in a computer system, embedded system, or handheld device.
Microprocessors made possible the advent of the microcomputer in the mid 1970s. Before this period, electronic CPUs were typically made from bulky discrete switching devices (and later small scale integrated circuits) containing the equivalent of only a few transistors. By integrating the processor onto one or a very few large scale integrated circuit packages (containing the equivalent of thousands or millions of discrete transistors), the cost of processor power was greatly reduced. Since the advent of the IC in the mid 1970s, the microprocessor has become the most prevalent implementation of the CPU, nearly completely replacing all other forms. See History of computing hardware for pre electronic and early electronic computers.
The evolution of microprocessors has been known to follow Moore's Law when it comes to steadily increasing performance over the years. This law suggests that the complexity of an integrated circuit, with respect to minimum component cost, doubles every 24 months. This dictum has generally proven true since the early 1970s. From their humble beginnings as the drivers for calculators, the continued increase in power has led to the dominance of microprocessors over every other form of computer; every system from the largest mainframes to the smallest handheld computers now uses a microprocessor at its core.
Contents
[hide]
• 1 History o 1.1 First types o 1.2 Notable 8 bit designs o 1.3 16 bit designs o 1.4 32 bit designs o 1.5 64 bit designs in personal computers o 1.6 Multicore designs o 1.7 RISC • 2 Special purpose designs • 3 Market statistics • 4 Architectures • 5 See also o 5.1 Major designers • 6 External links o 6.1 General o 6.2 Historical documents
[edit] History
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Main article: History of general purpose CPU
[edit] First types
The 4004 with cover removed (left) and as actually used (right).
Three projects arguably delivered a complete microprocessor at about the same time, namely Intel's 4004, Texas Instruments' TMS 1000, and Garrett AiResearch's Central Air Data Computer.
In 1968, Garrett AiResearch, with designer Ray Holt and Andre Gata, were invited to produce a digital computer to compete with electromechanical systems then under development for the main flight control computer in the US Navy's new F 14 Tomcat fighter. The design was complete by 1970, and used a MOS based chipset as the core CPU. The design was significantly (approx 20 times) smaller and much more reliable than the mechanical systems it competed against, and was used in all of the early Tomcat models. This system contained a "a 20 bit, pipelined, parallel multi microprocessor". However, the system was considered so advanced that the Navy refused to allow publication of the design until 1997. For this reason the CADC, and the MP944 chipset it used, are fairly unknown even today. see First Microprocessor Chip Set
TI developed the 4 bit TMS 1000 and stressed pre programmed embedded applications, introducing a version called the TMS1802NC on September 17, 1971, which implemented a calculator on a chip. The Intel chip was the 4 bit 4004, released on November 15, 1971, developed by Federico Faggin and Marcian Hoff.
TI filed for the patent on the microprocessor. Gary Boone was awarded U.S. Patent 3,757,306 for the single chip microprocessor architecture on September 4, 1973. It may never be known which company actually had the first working microprocessor running on the lab bench. In both 1971 and 1976, Intel and TI entered into broad patent cross licensing agreements, with Intel paying royalties to TI for the microprocessor patent. A nice history of these events is contained in court documentation from a legal dispute between Cyrix and Intel, with TI as intervenor and owner of the microprocessor patent.
Interestingly, a third party (Gilbert Hyatt) was awarded a patent which might cover the "microprocessor". See a webpage claiming an invention pre dating both TI and Intel, describing a "microcontroller". According to a rebuttal and a commentary, the patent was later invalidated, but not before substantial royalties were paid out.
A computer on a chip is a variation of a microprocessor which combines the microprocessor core (CPU), some memory, and I/O (input/output) lines, all on one chip. The computer on a chip patent, called the "microcomputer patent" at the time, U.S.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Patent 4,074,351 , was awarded to Gary Boone and Michael J. Cochran of TI. Aside from this patent, the standard meaning of microcomputer is a computer using one or more microprocessors as its CPU(s), while the concept defined in the patent is perhaps more akin to a microcontroller.
According to A History of Modern Computing, (MIT Press), pp. 220–21, Intel entered into a contract with Computer Terminals Corporation, later called Datapoint, of San Antonio TX, for a chip for a terminal they were designing. Datapoint later decided not to use the chip, and Intel marketed it as the 8008 in April, 1972. This was the world's first 8 bit microprocessor. It was the basis for the famous "Mark 8" computer kit advertised in the magazine Radio Electronics in 1974. The 8008 and its successor, the world famous 8080, opened up the microprocessor component marketplace.
[edit] Notable 8-bit designs
The 4004 was later followed in 1972 by the 8008, the world's first 8 bit microprocessor. These processors are the precursors to the very successful Intel 8080 (1974), Zilog Z80 (1976), and derivative Intel 8 bit processors. The competing Motorola 6800 was released August 1974. Its architecture was cloned and improved in the MOS Technology 6502 in 1975, rivaling the Z80 in popularity during the 1980s.
Both the Z80 and 6502 concentrated on low overall cost, through a combination of small packaging, simple computer bus requirements, and the inclusion of circuitry that would normally have to be provided in a separate chip (for instance, the Z80 included a memory controller). It was these features that allowed the home computer "revolution" to take off in the early 1980s, eventually delivering machines that sold for US$99.
The Western Design Center, Inc. (WDC) introduced the CMOS 65C02 in 1982 and licensed the design to several companies which became the core of the Apple IIc and IIe personal computers, medical implantable grade pacemakers and defibrilators, automotive, industrial and consumer devices. WDC pioneered the licensing of microprocessor technology which was later followed by ARM and other microprocessor Intellectual Property (IP) providers in the 1990’s.
Motorola trumped the entire 8 bit world by introducing the MC6809 in 1978, arguably one of the most powerful, orthogonal, and clean 8 bit microprocessor designs ever fielded – and also one of the most complex hardwired logic designs that ever made it into production for any microprocessor. Microcoding replaced hardwired logic at about this point in time for all designs more powerful than the MC6809 – specifically because the design requirements were getting too complex for hardwired logic.
Another early 8 bit microprocessor was the Signetics 2650, which enjoyed a brief flurry of interest due to its innovative and powerful instruction set architecture.
A seminal microprocessor in the world of spaceflight was RCA's RCA 1802 (aka CDP1802, RCA COSMAC) (introduced in 1976) which was used in NASA's Voyager
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 and Viking spaceprobes of the 1970s, and onboard the Galileo probe to Jupiter (launched 1989, arrived 1995). RCA COSMAC was the first to implement C MOS technology. The CDP1802 was used because it could be run at very low power,* and because its production process (Silicon on Sapphire) ensured much better protection against cosmic radiation and electrostatic discharges than that of any other processor of the era. Thus, the 1802 is said to be the first radiation hardened microprocessor.
[edit] 16-bit designs
The first multi chip 16 bit microprocessor was the National Semiconductor IMP 16, introduced in early 1973. An 8 bit version of the chipset was introduced in 1974 as the IMP 8. During the same year, National introduced the first 16 bit single chip microprocessor, the National Semiconductor PACE, which was later followed by an NMOS version, the INS8900.
Other early multi chip 16 bit microprocessors include one used by Digital Equipment Corporation (DEC) in the LSI 11 OEM board set and the packaged PDP 11/03 minicomputer, and the Fairchild Semiconductor MicroFlame 9440, both of which were introduced in the 1975 to 1976 timeframe.
The first single chip 16 bit microprocessor was TI's TMS 9900, which was also compatible with their TI 990 line of minicomputers. The 9900 was used in the TI 990/4 minicomputer, the TI 99/4A home computer, and the TM990 line of OEM microcomputer boards. The chip was packaged in a large ceramic 64 pin DIP package package, while most 8 bit microprocessors such as the Intel 8080 used the more common, smaller, and less expensive plastic 40 pin DIP. A follow on chip, the TMS 9980, was designed to compete with the Intel 8080, had the full TI 990 16 bit instruction set, used a plastic 40 pin package, moved data 8 bits at a time, but could only address 16 KiB. A third chip, the TMS 9995, was a new design. The family later expanded to include the 99105 and 99110.
The Western Design Center, Inc. (WDC) introduced the CMOS 65816 16 bit upgrade of the WDC CMOS 65C02 in 1984. The 65816 16 bit microprocessor was the core of the Apple IIgs and later the Super Nintendo Entertainment System, making it one of the most popular 16 bit designs of all time.
Intel followed a different path, having no minicomputers to emulate, and instead "upsized" their 8080 design into the 16 bit Intel 8086, the first member of the x86 family which powers most modern PC type computers. Intel introduced the 8086 as a cost effective way of porting software from the 8080 lines, and succeeded in winning much business on that premise. The 8088, a version of the 8086 that used an external 8 bit data bus, was the microprocessor in the first IBM PC, the model 5150. Following up their 8086 and 8088, Intel released the 80186, 80286 and, in 1985, the 32 bit 80386, cementing their PC market dominance with the processor family's backwards compatibility.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 The integrated microprocessor memory management unit (MMU) was developed by Childs et al. of Intel, and awarded US patent number 4,442,484.
[edit] 32-bit designs
Upper interconnect layers on an Intel 80486DX2 die.
16 bit designs were in the market only briefly when full 32 bit implementations started to appear.
The most famous of the 32 bit designs is the MC68000, introduced in 1979. The 68K, as it was widely known, had 32 bit registers but used 16 bit internal data paths, and a 16 bit external data bus to reduce pin count, and supported only 24 bit addresses. Motorola generally described it as a 16 bit processor, though it clearly has 32 bit architecture. The combination of high speed, large (16 mebibytes) memory space and fairly low costs made it the most popular CPU design of its class. The Apple Lisa and Macintosh designs made use of the 68000, as did a host of other designs in the mid 1980s, including the Atari ST and Commodore Amiga.
The world's first single chip fully 32 bit microprocessor, with 32 bit data paths, 32 bit buses, and 32 bit addresses, was the AT&T Bell Labs BELLMAC 32A, with first samples in 1980, and general production in 1982 (See this bibliographic reference and this general reference). After the divestiture of AT&T in 1984, it was renamed the WE 32000 (WE for Western Electric), and had two follow on generations, the WE 32100 and WE 32200. These microprocessors were used in the AT&T 3B5 and 3B15 minicomputers; in the 3B2, the world's first desktop supermicrocomputer; in the "Companion", the world's first 32 bit laptop computer; and in "Alexander", the world's first book sized supermicrocomputer, featuring ROM pack memory cartridges similar to today's gaming consoles. All these systems ran the UNIX System V operating system.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Intel's first 32 bit microprocessor was the iAPX 432, which was introduced in 1981 but was not a commercial success. It had an advanced capability based object oriented architecture, but poor performance compared to other competing architectures such as the Motorola 68000.
Motorola's success with the 68000 led to the MC68010, which added virtual memory support. The MC68020, introduced in 1985 added full 32 bit data and address busses. The 68020 became hugely popular in the Unix supermicrocomputer market, and many small companies (e.g., Altos, Charles River Data Systems) produced desktop size systems. Following this with the MC68030, which added the MMU into the chip, the 68K family became the processor for everything that wasn't running DOS. The continued success led to the MC68040, which included an FPU for better math performance. A 68050 failed to achieve its performance goals and was not released, and the follow up MC68060 was released into a market saturated by much faster RISC designs. The 68K family faded from the desktop in the early 1990s.
Other large companies designed the 68020 and follow ons into embedded equipment. At one point, there were more 68020s in embedded equipment than there were Intel Pentiums in PCs (See this webpage for this embedded usage information). The ColdFire processor cores are derivatives of the venerable 68020.
During this time (early to mid 1980s), National Semiconductor introduced a very similar 16 bit pinout, 32 bit internal microprocessor called the NS 16032 (later renamed 32016), the full 32 bit version named the NS 32032, and a line of 32 bit industrial OEM microcomputers. By the mid 1980s, Sequent introduced the first symmetric multiprocessor (SMP) server class computer using the NS 32032. This was one of the design's few wins, and it disappeared in the late 1980s.
The MIPS R2000 (1984) and R3000 (1989) were highly successful 32 bit RISC microprocessors. They were used in high end workstations and servers by SGI, among others.
Other designs included the interesting Zilog Z8000, which arrived too late to market to stand a chance and disappeared quickly.
In the late 1980s, "microprocessor wars" started killing off some of the microprocessors. Apparently, with only one major design win, Sequent, the NS 32032 just faded out of existence, and Sequent switched to Intel microprocessors.
From 1985 to 2003, the 32 bit x86 architectures became increasingly dominant in desktop, laptop, and server markets, and these microprocessors became faster and more capable. Intel had licensed early versions of the architecture to other companies, but declined to license the Pentium, so AMD and Cyrix built later versions of the architecture based on their own designs.During this span, these processors increased in complexity (transistor count) and capability (instructions/second) by at least a factor of 1000.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 [edit] 64-bit designs in personal computers
While 64 bit microprocessor designs have been in use in several markets since the early 1990s, the early 2000s have seen the introduction of 64 bit microchips targeted at the PC market.
With AMD's introduction of the first 64 bit IA 32 backwards compatible architecture, AMD64, in September 2003, followed by Intel's own x86 64 chips, the 64 bit desktop era began. Both processors can run 32 bit legacy apps as well as the new 64 bit software. With 64 bit Windows XP, Linux and Mac OS X (to a certain extent) that run 64 bit native, the software too is geared to utilise the full power of such processors. The move to 64 bits is more than just an increase in register size from the IA 32 as it also doubles the number of general purpose registers for the aging CISC designs.
The move to 64 bits by PowerPC processors had been intended since the processors' design in the early 90s and was not a major cause of incompatibility. Existing integer registers are extended as are all related data pathways, but, as was the case with IA 32, both floating point and vector units had been operating at or above 64 bits for several years. Unlike what happened with IA 32 was extended to x86 64, no new general purpose registers were added in 64 bit PowerPC, so any performance gained when using the 64 bit mode for applications making no use of the larger address space is minimal.
[edit] Multicore designs
AMD Athlon 64 X2 3600 Dual core processor Main article: Multi-core (computing)
A different approach to improving a computer's performance is to add extra processors, as in symmetric multiprocessing designs which have been popular in servers and workstations since the early 1990s. Keeping up with Moore's Law is becoming increasingly challenging as chip making technologies approach the physical limits of the technology.
In response, the microprocessor manufacturers look for other ways to improve performance, in order to hold on to the momentum of constant upgrades in the market.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 A multi core processor is simply a single chip containing more than one microprocessor core, effectively multiplying the potential performance with the number of cores (as long as the operating system and software is designed to take advantage of more than one processor). Some components, such as bus interface and second level cache, may be shared between cores. Because the cores are physically very close they interface at much faster clock speeds compared to discrete multiprocessor systems, improving overall system performance.
In 2005, the first mass market dual core processors were announced and as of 2007 dual core processors are widely used in servers, workstations and PCs while quad core processors are now available for high end applications in both the home and professional environments.
[edit] RISC
In the mid 1980s to early 1990s, a crop of new high performance RISC (reduced instruction set computer) microprocessors appeared, which were initially used in special purpose machines and Unix workstations, but have since become almost universal in all roles except the Intel standard desktop.
The first commercial design was released by MIPS Technologies, the 32 bit R2000 (the R1000 was not released). The R3000 made the design truly practical, and the R4000 introduced the world's first 64 bit design. Competing projects would result in the IBM POWER and Sun SPARC systems, respectively. Soon every major vendor was releasing a RISC design, including the AT&T CRISP, AMD 29000, Intel i860 and Intel i960, Motorola 88000, DEC Alpha and the HP PA.
Market forces have "weeded out" many of these designs, leaving the PowerPC as the main desktop RISC processor, with the SPARC being used in Sun designs only. MIPS continues to supply some SGI systems, but is primarily used as an embedded design, notably in Cisco routers. The rest of the original crop of designs have either disappeared, or are about to. Other companies have attacked niches in the market, notably ARM, originally intended for home computer use but since focussed at the embedded processor market. Today RISC designs based on the MIPS, ARM or PowerPC core power the vast majority of computing devices.
As of 2006, several 64 bit architectures are still produced. These include x86 64, MIPS, SPARC, Power Architecture, and Itanium. [edit] Special-purpose designs
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007
A 4 bit, 2 register, six assembly language instruction computer made entirely of 74 series chips.
Though the term "microprocessor" has traditionally referred to a single or multi chip CPU or system on a chip (SoC), several types of specialized processing devices have followed from the technology. The most common examples are microcontrollers, digital signal processors (DSP) and graphics processing units (GPU). Many examples of these are either not programmable, or have limited programming facilities. For example, in general GPUs through the 1990s were mostly non programmable and have only recently gained limited facilities like programmable vertex shaders. There is no universal consensus on what defines a "microprocessor", but it is usually safe to assume that the term refers to a general purpose CPU of some sort and not a special purpose processor unless specifically noted.
The RCA 1802 had what is called a static design, meaning that the clock frequency could be made arbitrarily low, even to 0 Hz, a total stop condition. This let the Voyager/Viking/Galileo spacecraft use minimum electric power for long uneventful stretches of a voyage. Timers and/or sensors would awaken/speed up the processor in time for important tasks, such as navigation updates, attitude control, data acquisition, and radio communication. [edit] Market statistics
In 2003, about $44 billion (USD) worth of microprocessors were manufactured and sold. [1] Although about half of that money was spent on CPUs used in desktop or laptop personal computers, those count for only about 0.2% of all CPUs sold. [edit] Architectures
• 65xx • IBM POWER, parent of PowerPC o MOS Technology 6502 family, with 88000 o Western Design Center 65xx o PowerPC family, G3, G4, G5 • ARM family • NSC 320xx • Altera Nios, Nios II • OpenCores OpenRISC architecture • Atmel AVR architecture (purely • PA RISC family microcontrollers) • National Semiconductor SC/MP
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • EISC ("scamp") • RCA 1802 (aka RCA COSMAC, • Signetics 2650 CDP1802) • SPARC • DEC Alpha • SuperH family • Intel • Transmeta Crusoe, Efficeon (VLIW o Intel 4004, 4040 architectures, IA 32 32 bit Intel x86 o Intel 8080, 8085, Zilog Z80 emulator) o Intel Itanium • INMOS Transputer o Intel i860 • x86 architecture o Intel i960 o Intel 8086, 8088, 80186, • LatticeMico32 80188 (16 bit real mode only • M32R architecture x86 architecture) • MIPS architecture o Intel 80286 (16 bit real mode • Motorola and protected mode x86 o Motorola 6800 architecture) o Motorola 6809 o IA 32 32 bit x86 architecture o Motorola 68000 family, o x86 64 64 bit x86 ColdFire architecture o Motorola 88000 (parent of • XAP processor from Cambridge PowerPC family, with Consultants POWER) • Xilinx o MicroBlaze soft processor o PowerPC405 embedded hard processor in Virtex FPGAs
[edit] See also
• Central processing unit • Firmware • Computer architecture • Floating point unit • Addressing mode • Front side bus • Digital signal processor • Instruction pipeline • Microcontroller • Instruction set • List of microprocessors • Microarchitecture • Arithmetic and logical unit • Microcode • CISC / RISC • microcontroller • Clock rate • Microprocessor Chronicles • Computer bus (documentary film) • Computer engineering • Motherboard • CPU cooling • Pipeline • CPU core voltage • Superscalar • CPU design • Superpipelined • CPU locking • Wait state • CPU power consumption • Scratchpad RAM
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 [edit] Major designers
• Intel • Advanced Micro Devices (AMD) • IBM Microelectronics • AMCC • Freescale Semiconductor • ARM Holdings • MIPS Technologies • Texas Instruments Semiconductors • Renesas Technology • Western Design Center • STMicroelectronics • Sun Microsystems [edit] External links
Wikimedia Commons has media related to: Microprocessors
[edit] General
• Great Microprocessors of the Past and Present – By John Bayko • Microprocessor history – Hosted by IBM • Microprocessor instruction set cards – By Jonathan Bowen • CPU Collection — An extensive archive of photographs and information, with hundreds of microprocessors from 1974 to the present day • CPU World – Extensive CPU/MCU/FPU data • Gecko's CPU Library – The Gecko's CPU/FPU collection from 4004 to today: hundreds pages of pictures and informations about processors, packages, sockets, etc. • HowStuffWorks "How Microprocessors Work" • IC Die Photography – A gallery of CPU die photographs
[edit] Historical documents
• TMS1802NC calculator chip press release – Texas Instruments, 17 September 1971 • 1973: TI Receives first patent on Single Chip Microprocessor • TI Awarded Basic Microcomputer Patent – TI, 17 February 1978 ("microcomputer" to be understood as a single chip computer; a simple C) • Important discoveries in microprocessors during 2004 – Hosted by IBM
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • Pico and General Instrument's Single Chip Calculator processor Possibly pre dating Intel and TI.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Digital signal processor
From Wikipedia, the free encyclopedia
Jump to: navigation, search
A digital signal processor (DSP) is a specialized microprocessor designed specifically for digital signal processing, generally in real time computing.
Contents
[hide]
• 1 Characteristics of typical Digital Signal Processors • 2 Architectural features of digital signal processors o 2.1 Program flow o 2.2 Memory architecture o 2.3 Data operations o 2.4 Instruction sets • 3 History • 4 DSPs in 2007 • 5 See also • 6 External links
[edit] Characteristics of typical Digital Signal Processors
• Designed for real time processing • Optimum performance with streaming data • Separate program and data memories (Harvard architecture) • Special Instructions for SIMD (Single Instruction, Multiple Data) operations • No hardware support for multitasking • The ability to act as a direct memory access device if in a host environment • Processes digital signals converted (using an Analog to digital converter (ADC)) from analog signals. Output is then converted back to analog form using a Digital to analog converter (DAC)
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007
A simple digital processing system [edit] Architectural features of digital signal processors
Digital signal processing can be done on general purpose microprocessors. However, a digital signal processor contains architectural optimizations to speed up processing. These optimizations are also important to lower costs, heat emission and power consumption.
[edit] Program flow
• Floating point unit integrated directly into the data path. • Pipelined architecture • Highly parallel accumulator and multiplier • Special looping hardware. Low overhead or Zero overhead looping capability
[edit] Memory architecture
• DSPs often use special memory architectures that are able to fetch multiple data and/or instructions at the same time: o Harvard architecture o modified von Neumann architecture • Use of direct memory access • Memory address calculation unit
[edit] Data operations
• Saturation arithmetic, in which operations that produce overflows will accumulate at the maximum (or minimum) values that the register can hold rather than wrapping around (maximum+1 doesn't overflow to minimum as in many general purpose CPUs, instead it stays at maximum). Sometimes various sticky bits operation modes are available. • Fixed point arithmetic is often used to speed up arithmetic processing. • Single cycle operations to increase the benefits of pipelining.
[edit] Instruction sets
• Multiply accumulate (MAC, aka fused multiply add, FMA) operations, which are used extensively in all kinds of matrix operations, such as convolution for filtering, dot product, or even polynomial evaluation (see Horner scheme). • Instructions to increase parallelism: SIMD, VLIW, superscalar architecture. • Specialized instructions for modulo addressing in ring buffers and bit reversed addressing mode for FFT cross referencing.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • Digital signal processors sometimes use time stationary encoding to simplify hardware and increase coding efficiency [edit] History
In 1978, Intel released the 2920 as an "analog signal processor". It had an on chip ADC/DAC with an internal signal processor, but it didn't have a hardware multiplier and was not successful in the market. In 1979, AMI released the S2811. It was designed as a microprocessor peripheral, and it had to be initialized by the host. The S2811 was likewise not successful in the market.
In 1979, Bell Labs introduced the first single chip DSP, the Mac 4 Microprocessor. Then, in 1980 the first stand alone, complete DSPs the NEC PD7720 and AT&T DSP1 were presented at the IEEE International Solid State Circuits Conference '80. Both processors were inspired by the research in PSTN telecommunications.
The Altamira DX 1 was another early DSP, utilizing quad integer pipelines with delayed branches and branch prediction.
The first DSP produced by Texas Instruments (TI), the TMS32010 presented in 1983, proved to be an even bigger success. It was based on the Harvard architecture, and so had separate instruction and data memory. It already had a special instruction set, with instructions like load and accumulate or multiply and accumulate. It could work on 16 bit numbers and needed 390ns for a multiply add operation. TI is now the market leader in general purpose DSPs. Another successful design was the Motorola 56000.
About five years later, the second generation of DSPs began to spread. They had 3 memories for storing two operands simultaneously and included hardware to accelerate tight loops, they also had an addressing unit capable of loop addressing. Some of them operated on 24 bit variables and a typical model only required about 21ns for a MAC (multiply accumulate). Members of this generation were for example the AT&T DSP16A or the Motorola DSP56001.
The main improvement in the third generation was the appearance of application specific units and instructions in the data path, or sometimes as coprocessors. These units allowed direct hardware acceleration of very specific but complex mathematical problems, like the Fourier transform or matrix operations. Some chips, like the Motorola MC68356, even included more than one processor core to work in parallel. Other DSPs from 1995 are the TI TMS320C541 or the TMS 320C80.
The fourth generation is best characterized by the changes in the instruction set and the instruction encoding/decoding. SIMD and MMX extensions were added, VLIW and the superscalar architecture appeared. As always, the clock speeds have increased, a 3ns MAC now became possible.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 [edit] DSPs in 2007
Today’s signal processors yield much greater performance. This is due in part to both technological and architectural advancements like lower design rules, fast access two level cache, (E)DMA circuit and a wider bus system. Of course, not all DSPs provide the same speed and many kinds of signal processors exist, each one of them being better suited for a specific task, ranging in price from about US$1.50 to US$300. A Texas Instruments C6000 series DSP clocks at 1 GHz and implements separate instruction and data caches as well as a 8 MiB 2nd level cache, and its I/O speed is rapid thanks to its 64 EDMA channels. The top models are capable of even 8000 MIPS (million instructions per second), use VLIW encoding, perform eight operations per clock cycle and are compatible with a broad range of external peripherals and various buses (PCI/serial/etc).
Another big signal processor manufacturer today is Analog Devices. The company provides a broad range of DSPs, but its main portfolio is multimedia processors, such as codecs, filters and digital analog converters. Its SHARC based processors range in performance from 66 MHz/198 MFLOPS (million floating point operations per second) to 400 MHz/2400MFLOPS. Some models even support multiple multipliers and ALUs, SIMD instructions and audio processing specific components and peripherals. Another product of the company is the Blackfin family of embedded digital signal processors, with models like the ADSP BF531 to ADSP BF536. These processors combine the features of a DSP with those of a general use processor. As a result, these processors can run simple operating systems like CLinux, velOSity and Nucleus RTOS while operating relatively efficiently on real time data.
Most DSPs use fixed point arithmetic, because in real world signal processing, the additional range provided by floating point is not needed, and there is a large speed benefit and cost benefit due to reduced hardware complexity. Floating point DSPs may be invaluable in applications where a wide dynamic range is required. Product developers might also use floating point DSPs to reduce the cost and complexity of software development in exchange for more expensive hardware, since it is generally easier to implement algorithms in floating point.
General purpose CPUs have borrowed concepts from digital signal processors, exemplified by many new instructions present in the MMX and SSE extensions to the Intel IA 32 architecture instruction set (ISA).
Generally, DSPs are dedicated integrated circuits, however DSP functionality can also be realized using Field Programmable Gate Array chips.
Embedded general purpose RISC processors are becoming increasingly DSP in functionality. For example, ARM Cortex A8 has a 128 bit wide SIMD unit that can have impressive 16 and 8 bit performance for industry standard benchmarks. [edit] See also
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • Microcontroller • Field programmable gate array • Cell Processor • Ageia Physics Processing Unit [edit] External links
• DSP Processor Core Based Wireless System Design • Microcontroller.com • DSP Education and Research List of Universities having DSP and other Embedded Systems Research Groups • DSP Engineering Magazine • Introduction to DSP Processor tutorial • Improv Systems Homepage • Analog Devices Homepage • DSP Discussion Groups • DSP Online Book • DSPs and VLIW • Pocket Guide to Processors for DSP Berkeley Design Technology, INC • DSP Online eBooks • Texas Instruments Homepage • CEVA, Inc. Homepage • Semiconductor Homepage • DSP FPGA.com Magazine
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Read-only memory
From Wikipedia, the free encyclopedia
Jump to: navigation, search The notion of read-only data can also refer to file system permissions. Computer memory types Read-only memory (usually known by its Volatile acronym, ROM) is a class of storage media used in computers and other electronic devices. • DRAM Because data stored in ROM cannot be • eDRAM modified (at least not very quickly or easily), it • SRAM is mainly used to distribute firmware (software • 1T SRAM that is very closely tied to specific hardware, • Upcoming and unlikely to require frequent updates). o Z RAM o TTRAM Modern semiconductor ROM chips are not • Historical immediately distinguishable from similar chips o Williams tube like RAM modules, except by the part numbers o Delay line memory printed on the package. o Selectron tube In its strictest sense, ROM refers only to mask ROM (the oldest type of solid state ROM), Non Volatile which is fabricated with the desired data permanently stored in it, and thus can never be • ROM o modified. However, more modern types such as PROM o EPROM and flash EEPROM can be erased and EAROM o re programmed multiple times; they are still EPROM o described as "read only memory" because the EEPROM o reprogramming process is generally infrequent, Flash memory comparatively slow, and often does not permit • Upcoming o random access writes to individual memory FeRAM o locations, which are possible when reading a MRAM o ROM. Despite the simplicity of mask ROM, PRAM o economies of scale and field-programmability SONOS o often make reprogrammable technologies more RRAM o flexible and inexpensive, so that mask ROM is NRAM rarely used in new products as of 2007. • Historical o Drum memory o Magnetic core memory o Bubble memory
Contents
[hide]
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • 1 History o 1.1 Use of ROM for program storage o 1.2 ROM for data storage • 2 Types of ROMs • 3 Headline text o 3.1 Semiconductor based o 3.2 Other technologies 3.2.1 Historical examples • 4 Speed of ROMs o 4.1 Reading speed o 4.2 Writing speed • 5 Endurance and data retention • 6 ROM images • 7 See also • 8 External links • 9 References
[edit] History
The simplest type of solid state ROM is as old as semiconductor technology itself: combinatorial logic gates can be joined manually to map n bit address input onto arbitrary values of m bit data output (a look up table). With the invention of the integrated circuit came mask ROM. Mask ROM consists of a grid of word lines (the address input) and bit lines (the data output), selectively joined together with transistor switches, and can represent an arbitrary look up table with a regular physical layout and predictable propagation delay.
In mask ROM, the data is physically encoded in the circuit, so it can only be programmed during fabrication. This leads to a number of serious disadvantages:
1. It is only economical to buy mask ROM in large quantities, since users must contract with a foundry to produce a custom design. 2. The turnaround time between completing the design for a mask ROM and receiving the finished product is long, for the same reason. 3. Mask ROM is impractical for R&D work since designers frequently need to modify the contents of memory as they refine a design. 4. If a product is shipped with faulty mask ROM, the only way to fix it is to recall the product and physically replace the ROM.
Subsequent developments have addressed these shortcomings. PROM, invented in 1956, allowed users to program its contents exactly once by physically altering its structure with the application of high voltage pulses. This addresses problems 1 and 2 above, since a company can simply order a large batch of fresh PROM chips and program them with the desired contents at its designers' convenience. The 1971 invention of EPROM
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 essentially solved problem 3, since EPROM (unlike PROM) can be repeatedly reset to its unprogrammed state by exposure to strong ultraviolet light. EEPROM, invented in 1983, went a long way to solving problem 4, since an EEPROM can be programmed in place if the containing device provides a means to receive the program contents from an external source (e.g. a personal computer via a serial cable). Flash memory, invented at Toshiba in the mid 1980s, and commercialized in the early 1990s, is a form of EEPROM that makes very efficient use of chip area and can be erased and reprogrammed thousands of times without damage.
All of these technologies improved the flexibility of ROM, but at a significant cost per chip, so that in large quantities mask ROM would remain an economical choice for many years. (Decreasing cost of reprogrammable devices had almost eliminated the market for mask ROM by the year 2000.) Furthermore, despite the fact that newer technologies were increasingly less "read only," most were envisioned only as replacements for the traditional use of mask ROM.
The most recent development is NAND flash, also invented by Toshiba. Its designers explicitly broke from past practice, stating plainly that "the aim of NAND Flash is to replace hard disks,"[1] rather than the traditional use of ROM as a form of non volatile primary storage. As of 2007, NAND has partially achieved this goal by offering throughput comparable to hard disks, higher tolerance of physical shock, extreme miniaturization (in the form of USB flash drives and tiny microSD memory cards, for example), and much lower power consumption.
[edit] Use of ROM for program storage
Every stored program computer requires some form of non volatile storage to store the initial program that runs when the computer is powered on or otherwise begin execution (a process known as bootstrapping). Likewise, every non trivial computer requires some form of mutable memory to record changes in its state as it executes.
Forms of read only memory were employed as non volatile storage for programs in most early stored program computers, such as ENIAC after 1948 (until then it was not a stored program computer as every problem had to be manually wired into the machine, which could take days to weeks). Read only memory was simpler to implement since it required only a mechanism to read stored values, and not to change them in place, and thus could be implemented with very crude electromechanical devices (see historical examples below). With the advent of integrated circuits in the 1960s, both ROM and its mutable counterpart static RAM were implemented as arrays of transistors in silicon chips; however, a ROM memory cell could be implemented using fewer transistors than an SRAM memory cell, since the latter requires a latch (comprising 5 20 transistors) to retain its contents, while a ROM cell might consist of a the absence (logical 0) or presence (logical 1) of a single transistor connecting a bit line to a word line.[2] Consequently, ROM could be implemented at a lower cost per bit than RAM for many years.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Many home computers of the 1980s stored a BASIC interpreter or operating system in ROM. ROM was more economical than RAM, and other forms of non volatile storage such as magnetic disk drives were too expensive to be included with every home computer. For example, the celebrated Commodore 64 included 64 KiB of RAM and 20 KiB of ROM contained a BASIC interpreter and the "KERNAL" (sic) of its operating system. Later home or office computers such as the IBM PC XT often included magnetic disk drives, and larger amounts of RAM, allowing them to load their operating systems from disk into RAM, with only a minimal hardware initialization core and bootloader remaining in ROM (known as the BIOS in IBM compatible computers). This arrangement allowed for a more complex and easily upgradeable operating system.
In modern general purpose computers, there is little reason to store any program code or data in read only memory: secondary storage devices such as hard disks are fast, ubiquitous, and rapidly decreasing in cost per bit, and large capacity dynamic RAM modules are cheaper than ROM thanks to economies of scale and more efficient designs. In modern PCs, ROM is used only to store basic bootstrapping firmware, such as the legacy BIOS which persists in most x86 based systems; even this limited "read only" memory is likely to be implemented as Flash ROM (see below) to permit in place reprogramming should the need for a firmware upgrade arise.
ROM and its successor technologies remain prevalent in embedded systems, such as MP3 players, set top boxes, and broadband routers, all of which are designed to achieve more restricted functions than general purpose computers, but which are nonetheless based on general purpose microprocessors in most cases. These devices often store all of their program code in ROM since they usually lack mass storage peripherals (e.g. hard disks) for reasons of cost, portability, and power consumption. Furthermore, since the software is usually tightly coupled to the hardware, changes to the software are rarely needed. Nonetheless, as of 2007 nearly all of these devices use Flash rather than mask ROM, and many provide some means to connect the device to a personal computer for firmware updates (for example, a digital audio player's firmware might be updated to support a new music file format). Hobbyists have taken advantage of this flexibility to reprogram such devices to new purposes; for example, the iPodLinux and OpenWRT projects have enabled users to run full featured Linux distributions on their MP3 players and wireless routers, respectively.
It is also useful for binary storage of cryptographic data, as it makes them difficult to replacement, which may be desirable in order to enhance information security.
[edit] ROM for data storage
Since ROM (at least in hard wired mask form) cannot be modified, it is really only suitable for storing data which is not expected to need modification for the life of the device. To that end, ROM has been used in many computers to store look up tables for the evaluation of mathematical and logical functions (for example, a floating point unit might tabulate the sine function in order to facilitate faster computation). This was especially effective when CPUs were slow and ROM was cheap compared to RAM.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Notably, the display adapters of early personal computers stored tables of bitmapped font characters in ROM. This usually meant that the text display font could not be changed interactively. This was the case for both the CGA and MDA adapters available with the IBM PC XT.
The use of ROM to store such small amounts of data has disappeared almost completely in modern general purpose computers. However, Flash ROM has taken over a new role as a medium for mass storage or secondary storage of files and programs, comparable to hard disks. This usage enabled by the development of NAND flash, which features high endurance, efficient use of chip area (and thus low cost per bit), and high read/write throughput. Although NAND flash developed from earlier ROM like technologies, its current use bears little resemblance to the original function of ROM. [edit] Types of ROMs [edit] Headline text
[edit] Semiconductor based
The first EPROM, an Intel 1702, with the die and wire bonds clearly visible through the erase window.
Classic mask-programmed ROM chips are integrated circuits that physically encode the data to be stored, and thus it is impossible to change their contents after fabrication. Other types of non volatile solid state memory permit some degree of modification:
• Programmable read-only memory (PROM), or one-time programmable ROM (OTP), can be written to or programmed via a special device called a PROM programmer. Typically, this device uses high voltages to permanently destroy or create internal links (fuses or antifuses) within the chip. Consequently, a PROM can only be programmed once. • Erasable programmable read-only memory (EPROM) can be erased by exposure to strong ultraviolet light (typically for 10 minutes or longer), then rewritten with a process that again requires application of higher than usual voltage. Repeated exposure to UV light will eventually wear out an EPROM, but the endurance of most EPROM chips exceeds 1000 cycles of erasing and
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 reprogramming. EPROM chip packages can often be identified by the prominent circular "window" which allows UV light to enter. After programming, the window is typically covered with a label to prevent accidental erasure. Some EPROM chips are factory programmed before they are packaged, and include no window; these are effectively PROM. • Electrically erasable programmable read-only memory (EEPROM) is based on a similar semiconductor structure to EPROM, but allows its entire contents (or selected banks) to be electrically erased, then rewritten electrically, so that they need not be removed from the computer (or camera, MP3 player, etc.). Writing or flashing an EEPROM is much slower (milliseconds per bit) than reading to a ROM or writing to a RAM (nanoseconds in both cases). o Electrically alterable read-only memory (EAROM) is a type of EEPROM that can be modified one bit at a time. Writing is a very slow process and again requires higher voltage (usually around 12 V) than is used for read access. EAROMs are intended for applications that require infrequent and only partial rewriting. EAROM may be used as non volatile storage for critical system setup information; in many applications, EAROM has been supplanted by CMOS RAM supplied by mains power and backed up with a lithium battery. o Flash memory (or simply flash) is a modern type of EEPROM invented in 1984. Flash memory can be erased and rewritten faster than ordinary EEPROM, and newer designs feature very high endurance (exceeding 1,000,000 cycles). Modern NAND flash makes efficient use of silicon chip area, resulting in individual ICs with a capacity as high as 16 GB as of 2007; this feature, along with its endurance and physical durability, has allowed NAND flash to replace magnetic in some applications (such as USB flash drives). Flash memory is sometimes called flash ROM or flash EEPROM when used as a replacement for older ROM types, but not in applications that take advantage of its ability to be modified quickly and frequently.
By applying write protection, some types of reprogrammable ROMs may temporarily become read only memory.
[edit] Other technologies
There are other types of non volatile memory which are not based on solid state IC technology, including:
• Optical storage media, such CD ROM which is read only (analogous to masked ROM). CD R is Write Once Read Many (analogous to PROM), while CD RW supports erase rewrite cycles (analogous to EEPROM); both are designed for backwards compatibility with CD ROM.
[edit] Historical examples
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007
Transformer matrix ROM (TROS), from the IBM System 360/20
• Diode matrix ROM, used in small amounts in many computers in the 1960s as well as electronic desk calculators and keyboard encoders for terminals. This ROM was programmed by installing discrete semiconductor diodes at selected locations between a matrix of word line traces and bit line traces on a printed circuit board. • Resistor, capacitor, or transformer matrix ROM, used in many computers until the 1970s. Like diode matrix ROM, it was programmed by placing components at selected locations between a matrix of word lines and bit lines. ENIAC's Function Tables were resistor matrix ROM, programmed by manually setting rotary switches. Various models of the IBM System/360 and complex peripherial devices stored their microcode in either capacitor (called BCROS for Balanced Capacitor Read Only Storage on the 360/50 & 360/65 or CCROS for Card Capacitor Read Only Storage on the 360/30) or transformer (called TROS for Transformer Read Only Storage on the 360/40 and others) matrix ROM. • Core rope, a form of transformer matrix ROM technology used where size and/or weight were critical. This was used in NASA/MIT's Apollo Spacecraft Computers, DEC's PDP 8 computers, and other places. This type of ROM was programmed by hand by weaving "word line wires" inside or outside of ferrite transformer cores. • The perforated metal character mask ("stencil") in Charactron cathode ray tubes, which was used as ROM to shape a wide electron beam to form a selected character shape on the screen either for display or a scanned electron beam to form a selected character shape as an overlay on a video signal. • Various mechanical devices used in early computing equipment. A machined metal plate served as ROM in the dot matrix printers on the IBM 026 and IBM 029 key punches. [edit] Speed of ROMs
[edit] Reading speed
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Although the relative speed of RAM vs. ROM has varied over time, as of 2007 large RAM chips can be read faster than most ROMs. Therefore, ROM content is sometimes copied to RAM or shadowed before its first use, and subsequently read from RAM.
[edit] Writing speed
For those types of ROM that can be electrically modified, writing speed is always much slower than reading speed, and it may require unusually high voltage, the movement of jumper plugs to apply write enable signals, and special lock/unlock command codes. Modern NAND Flash achieves the highest write speeds of any rewritable ROM technology, with speeds as high as 15 MiB/s (or 70 ns/bit), by allowing (indeed requiring) large blocks of memory cells to be written simultaneously. [edit] Endurance and data retention
Because they are written by forcing electrons through a layer of electrical insulation onto a floating transistor gate, rewriteable ROMs can withstand only a limited number of write and erase cycles before the insulation is permanently damaged. In the earliest EAROMs, this might occur after as few as 1,000 write cycles, while in modern Flash EEPROM the endurance may exceed 1,000,000, but it is by no means infinite. This limited endurance, as well as the higher cost per bit, means that Flash based storage is unlikely to completely supplant magnetic disk drives in the near future.
The timespan over which a ROM remains accurately readable is not limited by write cycling. The data retention of EPROM, EAROM, EEPROM, and Flash may be limited by charge leaking from the floating gates of the memory cell transistors. Leakage is exacerbated at high temperatures or in high radiation environments. Masked ROM and fuse/antifuse PROM do not suffer from this effect, as their data retention depends on physical rather than electrical permanence of the integrated circuit (although fuse re- growth was once a problem in early fused PROMs). [edit] ROM images
Main article: ROM image
The contents of ROM chips in video game console cartridges can be extracted with special software or hardware devices. The resultant memory dump files are known as ROM images, and can be used to produce duplicate cartridges, or in console emulators. The term originated when most console games were distributed on cartridges containing ROM chips, but achieved such widespread usage that it is still applied to images of newer games distributed on CD ROMs or other optical media.
ROM images of commercial games usually contain copyrighted software. The unauthorized copying and distribution of copyrighted software is usually a violation of copyright laws (in some jurisdictions duplication of ROM cartridges for backup purposes
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 may be considered fair use). Nevertheless, there is a thriving community engaged in the illegal distribution and trading of such software. In such circles, the term "ROM images" is sometimes shortened simply to "ROMs" or sometimes changed to "romz" to highlight the connection with "warez". [edit] See also
• Random access memory • PROM • EPROM • EEPROM • Flash memory [edit] External links
• Types of ROM [edit] References
1. ^ See page 6 of Toshiba's 1993 NAND Flash Applications Design Guide. 2. ^ See chapters on "Combinatorial Digital Circuits" and "Sequential Digital Circuits" in Millman & Grable, Microelectronics, 2nd ed.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Random access memory
From Wikipedia, the free encyclopedia
Jump to: navigation, search “RAM” redirects here. For other uses of the word, see Ram. Dynamic RAM (DRAM)
512 MB DRAM Modules Connects to:
• PCB or motherboard via one of o Socket o Integration
Types:
• SDRAM • DDR • RDRAM • DDR 2 • DDR 3
Common Manufacturers:
• Corsair Memory • Kingston Technology • Micron Technology • Mushkin • Samsung
Random access memory (usually known by its acronym, RAM) is a type of data storage used in computers. It takes the form of integrated circuits that allow the stored data to be accessed in any order — that is, at random and without the physical movement of the storage medium or a physical reading head.
The word "random" refers to the fact that any piece of data can be returned in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data.[1] This contrasts with storage mechanisms such as tapes, magnetic discs and optical discs, which rely on the physical movement of the recording medium or a reading
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 head. In these devices, the movement takes longer than the data transfer, and the retrieval time varies depending on the physical location of the next item.
Contents
[hide]
• 1 Terminology • 2 Overview • 3 Recent developments • 4 Memory wall • 5 Shadow RAM • 6 DRAM packaging • 7 See also • 8 Notes and references • 9 External links
[edit] Terminology
Originally, RAM referred to a type of solid state memory, and the majority of this article deals with that, but physical devices which can emulate true RAM (or, at least, are used in a similar way) can have "RAM" in their names: for example, DVD RAM.
RAM is usually writable as well as readable, so "RAM" is often used interchangeably with "read write memory". The alternative to this is "ROM", or Read Only Memory. Most types of RAM lose their data when the computer powers down. "Flash memory" is a ROM/RAM hybrid that can be written to, but which does not require power to maintain its contents. RAM is not strictly the opposite of ROM, however. The word random indicates a contrast with serial access or sequential access memory.
"Random access" is also the name of an indexing method: hence, disk storage is often called "random access" because the reading head can move relatively quickly from one piece of data to another, and does not have to read all the data in between. However the final "M" is crucial: "RAM" (provided there is no additional term as in "DVD RAM") always refers to a solid state device.
Many CPU based designs actually have a memory hierarchy consisting of registers, on die SRAM caches, DRAM, paging systems, and virtual memory or swap space on a hard drive. This entire pool of memory may be referred to as "RAM" by many developers, even though the various subsystems can have very different access times, violating the original concept behind the "random access" term in RAM. Even within a hierarchy level such as DRAM, the specific row/column/bank/rank/channel/interleave organization of the components make the access time variable, although not to the extent that rotating storage media or a tape is variable.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 [edit] Overview
The key benefit of RAM over types of storage which require physical movement is that retrieval times are short and consistent. Short because no physical movement is necessary, and consistent because the time taken to retrieve a piece of data does not depend on its current distance from a physical head; it requires practically the same amount of time to access any piece of data stored in a RAM chip. Most other technologies have inherent delays for reading a particular bit or byte. The disadvantage of RAM over physically moving media is cost, and the loss of data when power is turned off.
Because of this speed and consistency, RAM is used as 'main memory' or primary storage: the working area used for loading, displaying and manipulating applications and data. In most personal computers, the RAM is not an integral part of the motherboard or CPU—it comes in the easily upgraded form of modules called memory sticks or RAM sticks about the size of a few sticks of chewing gum. These can quickly be removed and replaced should they become damaged or too small for current purposes. A smaller amount of random access memory is also integrated with the CPU, but this is usually referred to as "cache" memory, rather than RAM.
Modern RAM generally stores a bit of data as either a charge in a capacitor, as in dynamic RAM, or the state of a flip flop, as in static RAM. Some types of RAM can detect or correct random faults called memory errors in the stored data, using RAM parity and error correction codes.
Many types of RAM are volatile, which means that unlike some other forms of computer storage such as disk storage and tape storage, they lose all data when the computer is powered down. For these reasons, nearly all PCs use disks as "secondary storage". Small PDAs and music players (up to 8 GiB in Jan 2007) may dispense with disks, but rely on flash memory to maintain data between sessions of use.
Software can "partition" a portion of a computer's RAM, allowing it to act as a much faster hard drive that is called a RAM disk. Unless the memory used is non volatile, a RAM disk loses the stored data when the computer is shut down. However, volatile memory can retain its data when the computer is shut down if it has a separate power source, usually a battery.
If a computer becomes low on RAM during intensive application cycles, the computer can resort to so called virtual memory. In this cases, the computer temporarily uses hard drive space as additional memory. Constantly relying on this type of backup memory it is called thrashing, which is generally undesirable, as virtual memory lacks the advantages of RAM. In order to reduce the dependency on virtual memory, more RAM can be installed. [edit] Recent developments
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Currently, several types of non-volatile RAM are under development, which will preserve data while powered down. The technologies used include carbon nanotubes and the magnetic tunnel effect.
In summer 2003, a 128 KiB magnetic RAM chip manufactured with 0.18 m technology was introduced. The core technology of MRAM is based on the magnetic tunnel effect. In June 2004, Infineon Technologies unveiled a 16 MiB prototype again based on 0.18 m technology.
Nantero built a functioning carbon nanotube memory prototype 10 GiB array in 2004.
In 2006, Solid state memory came of age, especially when implemented as "Solid state disks", with capacities exceeding 150 gigabytes and speeds far exceeding traditional disks. This development has started to blur the definition between traditional random access memory and disks, dramatically reducing the difference in performance. [edit] Memory wall
The "memory wall" is the growing disparity between CPU and memory speeds. From 1986 to 2000, CPU speed improved at an annual rate of 55% while memory speed only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming bottleneck in computer performance. [2]
Currently, CPU speed improvements have slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. Intel summarized these causes in their Platform 2015 documentation (PDF):
First of all, as chip geometries shrink and clock frequencies rise, the transistor leakage current increases, leading to excess power consumption and heat (more on power consumption below). Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so called Von Neumann bottleneck), further undercutting any gains that frequency increases might otherwise buy. In addition, resistance capacitance (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.
The RC delays in signal transmission were also noted in Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures which projects a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014. The data on Intel Processors clearly shows a slowdown in performance improvements in recent processors. However, Intel's new processors, Core 2 Duo (codenamed Conroe) show a significant improvement over previous Pentium 4 processors.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 [edit] Shadow RAM
Shadow RAM is RAM whose contents are copied from read only memory (ROM) to allow shorter access times, as ROM is in general slower than RAM. The original ROM is disabled and the new location in the RAM is write protected. This process is called shadowing.
As a common example, some BIOSes have a feature labeled “use shadow BIOS” or similar in the configuration options. When enabled, functionality that would rely on reading data from the BIOS’s ROM chip instead makes use of the RAM installed in the system. Depending on the system, this may or may not lead to a performance boost for calls to the BIOS. With operating systems such as Microsoft Windows, such a performance difference can be unnoticeable due to the way those systems manage BIOS functionality and through their use of different ROM routines.
Shadowed memory cannot be used for any other purpose and as a result less extended memory is available to systems which have it enabled. On most modern systems, the feature can be toggled in BIOS settings.[3]
Linux does not use ROM BIOS routines, so disabling Shadow BIOS in motherboard settings will free up a small amount of RAM (about 200k) [4] [edit] DRAM packaging
Main article: DRAM packaging
For economic reasons, the large (main) memories found in personal computers, workstations, and non handheld game consoles (such as Playstation and Xbox) normally consists of dynamic RAM (DRAM). Other parts of the computer, such as cache memories and data buffers in hard disks, normally use static RAM (SRAM). [edit] See also
• CAS latency (CL) • DIMM • DVD RAM • Dual channel architecture • Error correcting code (ECC) • Registered/Buffered memory • Compact Flash • PC card • Static RAM (SRAM) • Non Volatile RAM (NVRAM) • Dynamic RAM (DRAM) o Fast Page Mode DRAM
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 o EDO RAM or Extended Data Out DRAM o XDR DRAM o SDRAM or Synchronous DRAM DDR SDRAM or Double Data Rate Synchronous DRAM; now being replaced by DDR2 SDRAM RDRAM or Rambus DRAM [edit] Notes and references
1. ^ Strictly speaking, modern types of DRAM are therefore not truly (or technically) random access, as data are read in burst; the name DRAM has stuck however. 2. ^ The term was coined in Hitting the Memory Wall: Implications of the Obvious (PDF). 3. ^ Shadow Ram (HTML). Retrieved on 2007 07 24. 4. ^ Error on call to Template:cite web: Parameters url and title must be specified (HTML). Retrieved on 2007 08 09. [edit] External links
• How RAM Works – Article by Jeff Tyson and Dave Coustan
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 EEPROM
From Wikipedia, the free encyclopedia
Jump to: navigation, search 2 An EEPROM (also called an E PROM) or Computer memory types Electrically Erasable Programmable Read Volatile Only Memory, is a non volatile storage chip used in computers and other devices to store • DRAM small amounts of volatile (configuration) data. • eDRAM When larger amounts of more static data are to • SRAM be stored (such as in USB flash drives) other • 1T SRAM memory types like flash memory are more • Upcoming economical. o Z RAM o TTRAM • Historical o Williams tube o Delay line memory o Selectron tube
Non Volatile
• ROM o PROM o EAROM o EPROM o EEPROM o Flash memory • Upcoming o FeRAM o MRAM o PRAM o SONOS o RRAM o NRAM • Historical o Drum memory o Magnetic core memory o Bubble memory
Contents
[hide]
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • 1 Overview • 2 History • 3 Operation o 3.1 Serial bus devices o 3.2 Parallel bus devices • 4 Related types o 4.1 Comparison with EPROM and EEPROM/Flash • 5 EEPROM manufacturers • 6 See also • 7 External links • 8 References
[edit] Overview [edit] History
In 1983, Greek American George Perlegos at Intel developed the Intel 2816, which built on earlier EPROM technology, but used a thin gate oxide layer so that the chip could erase its own bits without requiring a UV source. Perlegos and others later left Intel to form Seeq Technology, which used on device charge pumps to supply the high voltages necessary for programming EEPROMs. [1] [edit] Operation
There are different types of electrical interfaces to EEPROM devices. Main categories of these interface types are :
• Serial bus • Parallel bus
How the device is operated depends on the electrical interface.
[edit] Serial bus devices
Most common serial interface types are SPI, I²C and 1 Wire. These three interfaces require between 2 and 4 controls signals for operation, resulting in a memory device in an 8 pin (or less) package.
The serial EEPROM typically operates in three phases: OP Code Phase, Address Phase and Data Phase. The OP Code is usually the first 8 bits input to the serial input pin of the EEPROM device, followed by 16 to 24 bits of addressing depending on the depth of the device.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Each EEPROM device typically has its own set of OP Code instructions to map to different functions. Some of the common operations on SPI EEPROM devices are:
• Write Enable (WREN) • Write Disable (WRDI) • Read Status Register (RDSR) • Write Status Register (WRSR) • Read Data (READ) • Write Data (WRITE)
Other operations supported by some EEPROM devices are:
• Program • Sector Erase • Chip Erase commands
The final phase of operation is typically the data phase. In case of WRITE, the controller needs to supply data until the chip select is low. In case of read, the controller needs to sample the data every serial clock edge until the chip select is low.
[edit] Parallel bus devices
Parallel EEPROM devices typically have an 8 bit data bus and an address bus wide enough to cover the complete memory. Most devices have chip select and write protect pins. Some microcontrollers also have integrated parallel EEPROM.
Operation of a parallel EEPROM is simple and fast when compared to serial EEPROM, but these devices are larger due to the higher pin count (up to 32 pins or more) and have been decreasing in popularity in favor of Serial EEPROM or Flash. [edit] Related types
Flash memory is a later form of EEPROM. In the industry, there is a convention to reserve the term EEPROM to byte wise writeable memories compared to block wise writable flash memories. EEPROM takes more die area than flash memory for the same capacity because each cell usually needs both a read, write and erase transistor, while in flash memory the erase circuits are shared by large blocks of cells (often 512×8).
Newer non volatile memory technologies such as FeRAM and MRAM are slowly replacing EEPROMs in some applications, but are expected to remain a small fraction of the EEPROM market for the forseeable future.
[edit] Comparison with EPROM and EEPROM/Flash
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 The difference between EPROM and EEPROM lies in the way that the memory programs and erases. EEPROM can be programmed and erased electrically using field emission (more commonly known in the industry as "Fowler Nordheim tunneling").
EPROMs can't be erased electrically, and are programmed via hot carrier injection onto the floating gate. Erase is via an ultraviolet light source, although in practice many EPROMs are encapsulated in plastic that is opaque to UV light, and are "one time programmable".
Most NOR Flash memory is a hybrid style—programming is through Hot carrier injection and erase is through Fowler Nordheim tunneling. [edit] EEPROM manufacturers
• Aplus Flash Technology • Atmel • Hitachi • Infineon • Maxwell Technologies • Microchip Technology • Philips • Renesas Technology • Samsung Electronics • STMicroelectronics • Seiko Instruments [edit] See also
• NVRAM • Flash memory • DataFlash [edit] External links
• EEPROM vs. Other Memory Types [edit] References
Rostky, George (July 2, 2002). "Remembering the PROM knights of Intel". EE Times. Retrieved on February 8, 2007.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Flash memory
From Wikipedia, the free encyclopedia
Jump to: navigation, search Computer memory types Volatile
• DRAM • eDRAM • SRAM • 1T SRAM • Upcoming o Z RAM o TTRAM • Historical o Williams tube o Delay line memory A USB flash drive. The chip on the left is the o Selectron tube flash memory. The microcontroller is on the right. Non Volatile Flash memory is non volatile computer • ROM memory that can be electrically erased and o PROM reprogrammed. It is a technology that is o EAROM primarily used in memory cards, USB flash o EPROM drives (thumb drives, handy drive, memory o EEPROM stick, flash stick, jump drive), which are used o Flash memory for general storage and transfer of data between • Upcoming computers and other digital products. It is a o FeRAM specific type of EEPROM that is erased and o MRAM programmed in large blocks; in early flash the o PRAM entire chip had to be erased at once. Flash o SONOS memory costs far less than byte programmable o RRAM EEPROM and therefore has become the o NRAM dominant technology wherever a significant • Historical amount of non volatile, solid state storage is o Drum memory needed. Examples of applications include PDAs o Magnetic core memory and laptop computers, digital audio players, o Bubble memory digital cameras and mobile phones. It has also gained some popularity in the game console market, where it is often used instead of EEPROMs or battery powered static RAM (SRAM) for game save data.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Contents
[hide]
• 1 Overview • 2 Principles of operation o 2.1 NOR flash o 2.2 NAND flash o 2.3 New designs • 3 History • 4 Limitations • 5 Low level access o 5.1 NOR memories o 5.2 NAND memories o 5.3 Standardization • 6 Understanding the distinction between NOR and NAND flash o 6.1 Endurance • 7 Serial flash o 7.1 Firmware storage • 8 Flash file systems • 9 Capacity • 10 Speed • 11 Flash memory as a replacement for hard drives • 12 See also • 13 External links • 14 References
[edit] Overview
Flash memory is non volatile, which means that it does not need power to maintain the information stored in the chip. In addition, flash memory offers fast read access times (although not as fast as volatile DRAM memory used for main memory in PCs) and better kinetic shock resistance than hard disks. These characteristics explain the popularity of flash memory for applications such as storage on battery powered devices. Another feature of flash memory is that when packaged in a "memory card", it is enormously durable, being able to withstand intense pressure, extremes of temperature and immersion in water.
Although technically a type of EEPROM, the term "EEPROM" is generally used to refer specifically to non flash EEPROM which is eraseable in small blocks, typically bytes. Because an erase cycle is slow, the large size of a flash ROM's erase block can make programming it faster than old style EEPROM. [edit] Principles of operation
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Flash memory stores information in an array of floating gate transistors, called "cells". In traditional single-level cell (SLC) devices, each cell stores only one bit of information. Some newer flash memory, known as multi-level cell (MLC) devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells.
A flash memory cell.
[edit] NOR flash
Programming a NOR memory cell (setting it to logical 0), via hot electron injection.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007
Erasing a NOR memory cell (setting it to logical 1), via quantum tunneling.
In NOR gate flash, each cell resembles a standard MOSFET, except that it has two gates instead of just one. On top is the control gate (CG), as in other MOS transistors, but below this there is a floating gate (FG) insulated all around by an oxide layer. The FG sits between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, any electrons placed on it are trapped there and, under normal conditions, will not discharge for a period of many years. When the FG holds a charge, it screens (partially cancels) the electric field from the CG, which modifies the threshold voltage (VT) of the cell. During read out, a voltage is applied to the CG, and the MOSFET channel will become conducting or remain insulating, depending on the VT of the cell, which is in turn controlled by charge on the FG. The presence or absence of current flow through the MOSFET channel is sensed and forms a binary code, reproducing the stored data. In a multi level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.
A single level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure:
• an elevated on voltage (typically >5 V) is applied to the CG • the channel is now turned on, so electrons can flow between the source and the drain • the source drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called hot electron injection
To erase a NOR flash cell (resetting it to the "1" state), a large voltage of the opposite polarity is applied between the CG and drain, pulling the electrons off the FG through quantum tunneling. Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can only be performed on a block
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 wise basis, that is all the cells in an erase segment must be erased together. Programming of NOR cells, however, can generally be performed one byte or word at a time.
Despite the need for high programming and erasing voltages, virtually all flash chips today require only a single supply voltage, and produce the high voltages on chip via charge pumps.
NOR flash memory wiring and structure on silicon.
[edit] NAND flash
NAND gate flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB interface storage devices known as USB flash drives, as well as most memory card formats available today.
NAND flash memory wiring and structure on silicon.
[edit] New designs
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 As manufacturers increase the density of data storage in flash devices, individual memory cells are shrinking and the number of electrons stored in any cell is becoming very small. Coupling between adjacent floating gates can change the write characteristics of cells, making it increasingly difficult to design flash devices for high data integrity. New designs, such as charge trap flash, attempt to provide better isolation between adjacent cells. [edit] History
Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba in 1984. According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of a flash of a camera. Dr. Masuoka presented the invention at the IEEE 1984 International Electron Devices Meeting (IEDM) held in San Francisco, California. Intel saw the massive potential of the invention and introduced the first commercial NOR type flash chip in 1988.
NOR based flash has long erase and write times, but provides full address and data buses, allowing random access to any memory location. This makes it a suitable replacement for older ROM chips, which are used to store program code that rarely needs to be updated, such as a computer's BIOS or the firmware of set top boxes. Its endurance is 10,000 to 1,000,000 erase cycles. [citation needed] NOR based flash was the basis of early flash based removable media; CompactFlash was originally based on it, though later cards moved to less expensive NAND flash.
Toshiba announced NAND flash at ISSCC in 1989. It has faster erase and write times, and requires a smaller chip area per cell, thus allowing greater storage densities and lower costs per bit than NOR flash; it also has up to ten times the endurance of NOR flash. However, the I/O interface of NAND flash does not provide a random access external address bus. Rather, data must be read on a block wise basis, with typical block sizes of hundreds to thousands of bits. This makes NAND flash unsuitable to replace program ROM, since most microprocessors and microcontrollers cannot directly execute programs stored in memory without random access; however, NAND flash is similar to other secondary storage devices such as hard disks and optical media, and is thus very suitable for use in mass storage devices such as memory cards. The first NAND based removable media format was SmartMedia, and many others have followed, including MultiMediaCard, Secure Digital, Memory Stick and xD Picture Card. A new generation of memory card formats, including RS MMC, miniSD and microSD, and Intelligent Stick, feature extremely small form factors; the microSD card has an area of just over 1.5 cm², with a thickness of less than 1 mm. [edit] Limitations
One limitation of flash memory is that although it can be read or programmed a byte or a word at a time in a random access fashion, it must be erased a "block" at a time. This
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random access read and programming operations, but cannot offer arbitrary random access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over written value's. For example, a nibble value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. Although data structures in flash memory can not be updated in completely general ways, this allows members to be "removed" by marking them as invalid. This technique must be modified somewhat for multi level devices, where one memory cell holds more than one bit.
Another limitation is that flash memory has a finite number of erase write cycles (most commercially available flash products are guaranteed to withstand 1000 write erase cycles for block 0, and no guarantees for other blocks[citation needed]). This effect is partially offset by some chip firmware or file system drivers by counting the writes and dynamically remapping the blocks in order to spread the write operations between the sectors; this technique is called wear levelling. Another mechanism is to perform write verification and remapping to spare sectors in case of write failure, which is named bad block management (BBM). With these mechanisms in place, some industry analysts[1] have calculated that flash memory can be written to at full speed continuously for 51 years before exceeding its write endurance, even if such writes frequently cause the entire disk to be overwritten. This figure (51 years) involved a worst case scenario using specific data parameters and should not be confused with a particular "shelf life" for a flash memory device. The bottom line is that a typical user using a commercial device, such as a camera, with a flash drive will probably not wear out the memory for the effective life of the camera. However, it like any other hardware component can fail. Anyone using flash memory (and any other medium) for critical data would be well advised to backup the data to another device (preferably of a different medium). Many have found it a very fast and reliable for 'read only' operating systems such as thin clients and routers. [edit] Low-level access
The low level interface to flash memory chips usually differs from those of other common types such as DRAM, ROM, and EEPROM, which support random access via externally accessible address buses.
While NOR memory provides an external address bus for read operations (and thus supports random access), unlocking, erasing, and writing NOR memory must proceed on a block by block basis. Typical block sizes are 64, 128, or 256 bytes. With NAND flash memory, all operations must be performed in a block wise fashion: reading, unlocking, erasing, and writing.
[edit] NOR memories
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Reading from NOR flash is similar to reading from random access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly without the need to copy them into RAM. NOR flash chips lack intrinsic bad block management, so when a flash block is worn out, the software or device driver controlling the device must handle this, or the device will cease to work reliably.
When unlocking, erasing or writing NOR memories, special commands are written to the first page of the mapped memory. These commands are defined by the Common Flash memory Interface (CFI) and the flash chips can provide a list of available commands to the physical driver.
Apart from being used as random access ROM, NOR memories can also be used as storage devices. However, NOR flash chips typically have slow write speeds compared with NAND flash.
[edit] NAND memories
NAND flash architecture was introduced by Toshiba in 1989. NAND flash memories cannot provide execute in place due to their different construction principles. These memories are accessed much like block devices such as hard disks or memory cards. The pages are typically 512 or 2,048 bytes in size. Associated with each page are a few bytes (typically 12–16 bytes) that should be used for storage of an error detection and correction checksum.
The pages are typically arranged in blocks. A typical block would be 32 pages of 512 bytes or 64 pages of 2,048 bytes.
While programming is performed on a page basis, erasure can only be performed on a block basis.
NAND devices also require bad block management to be performed by device driver software, or by a separate controller chip (SD cards, for example, include controller circuitry to perform bad block management and wear leveling). When a logical block is accessed by high level software, it is mapped to a physical block by the device driver or controller, and a number of blocks on the flash chip are set aside for storing mapping tables to deal with bad blocks.
The error correcting and detecting checksum will typically correct an error where one bit per 256 bytes is incorrect. When this happens, the block is marked bad in a logical block allocation table, and its undamaged contents are copied to a new block and the logical block allocation table is altered accordingly. If more than one bit in the memory is corrupted, the contents are partly lost, i.e. it is no longer possible to reconstruct the original contents.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Most NAND devices are shipped from the factory with some bad blocks which are typically identified and marked according to a specified bad block marking strategy. By allowing some bad blocks, the manfacturers achieve far higher yields than would be possible if all blocks were tested good. This significantly reduces NAND flash costs and increases the size of the parts.
The first physical block (block 0) is always guaranteed to be readable and free from errors. Hence, all vital pointers for partitioning and bad block management for the device must be located inside this block (typically a pointer to the bad block tables etc). If the device is used for booting a system, this block may contain the master boot record.
When executing software from NAND memories, virtual memory strategies are used: memory contents must first be paged or copied into memory mapped RAM and executed there. A memory management unit (MMU) in the system is helpful, but this can also be accomplished with overlays. For this reason, some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a random access storage area. NAND is best suited to flash devices requiring high capacity data storage. This type of flash architecture combines higher storage space with faster erase, write, and read capabilities over the execute in place advantage of the NOR architecture.
[edit] Standardization
A group called the Open NAND Flash Interface Working Group (ONFI) has developed a standardized low level interface for NAND flash chips. This allows interoperability between conforming NAND devices from different vendors. The ONFI specification version 1.0[2] was released on December 28, 2006. It specifies:
• a standard physical interface (pinout) for NAND flash in TSOP 48, WSOP 48, LGA 52, and BGA 63 packages • a standard command set for reading, writing, and erasing NAND flash chips • a mechanism for self identification (comparable to the Serial Presence Detection feature of SDRAM chips)
The ONFI group is supported by major NAND flash manufacturers, including Intel, Micron Technology, and Sony, as well as by major manufacturers of devices incorporating NAND flash chips.[3]
A group of vendors, including Intel, Dell, and Microsoft formed a Non Volatile Memory Host Controller Interface (NVMHCI) Working Group [4]. The goal of the group is to provide standard software and hardware programming interfaces for nonvolatile memory subsystems, including the "flash cache" device connected to the PCI Express bus. [edit] Understanding the distinction between NOR and NAND flash
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 NOR and NAND flash differ in two important ways:
• the connections of the individual memory cells are different • the interface provided for reading and writing the memory is different (NOR allows random access for reading, NAND allows only block access)
It is important to understand that these two are linked by the design choices made in the development of NAND flash. An important goal of NAND flash development was to reduce the chip area required to implement a given capacity of flash memory, and thereby to reduce cost per bit and increase maximum chip capacity so that flash memory could compete with magnetic storage devices like hard disks.
NOR and NAND flash get their names from the structure of the interconnections between memory cells.[5] In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a NAND gate, and preventing cells from being read and programmed individually: the cells connected in series must be read in series.
When NOR flash was developed, it was envisioned as a more economical and conveniently rewriteable ROM than contemporary EPROM, EAROM, and EEPROM memories. Thus random access reading circuitry was necessary. However, it was expected that NOR flash ROM would be read much more often than written, so the write circuitry included was fairly slow and could only erase in a block wise fashion; random access write circuitry would add to the complexity and cost unnecessarily.
Because of the series connection, a large grid of NAND flash memory cells will occupy only a small fraction of the area of equivalent NOR cells (assuming the same CMOS process resolution, e.g. 130 nm, 90 nm, 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random access of NAND flash memory impossible, but the goal of NAND flash was to replace hard disks, not to replace ROMs.
[edit] Endurance
The endurance of NAND flash is much greater than that of NOR flash (typically 1,000,000 cycles vs. 100,000 cycles). This is because programming and erasure in NOR flash rely on different microscopic processes (hot electron injection and quantum tunneling, respectively), while they are perfectly symmetric in NAND flash (Fowler Nordheim tunneling).[5] The asymmetric nature of NOR flash programming and erasure increases the rate at which memory cells degrade, over many program/erase cycles.
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 The superior symmetric programming method of NAND flash has in fact been adopted in many NOR flash designs, so that some modern NOR chips boast endurance comparable to NAND flash.[5] [edit] Serial flash
Serial flash is a small, low power flash memory that uses a serial interface, typically SPI, for sequential data access. When incorporated into an embedded system, serial flash requires fewer wires on the PCB than parallel flash memories, since it transmits and receives data one bit at a time. This may permit a reduction in board space, power consumption, and total system cost.
There are several reasons why a serial device, with fewer external pins than a parallel device, can significantly reduce overall cost:
• Many ASICs are pad-limited, meaning that the size of the die is constrained by the number of wire bond pads, rather than the complexity and number of gates used for the device logic. Eliminating bond pads thus permits a more compact integrated circuit, on a smaller die; this increases the number of dies that may be fabricated on a wafer, and thus reduces the cost per die. • Reducing the number of external pins also reduces assembly and packaging costs. A serial device may be packaged in a smaller and simpler package than a parallel device. • Smaller and lower pin count packages occupy reduced PCB area. • Lower pin count devices simplify PCB routing.
[edit] Firmware storage
With the increasing speed of modern CPUs, parallel flash devices are often too slow to execute in place program code stored on them. Conversely, modern SRAM offers access times below 10 ns, while DDR2 SDRAM offers access times below 20 ns. Because of this, it is often necessary to shadow code stored in flash into RAM; that is, code must be copied from flash into RAM before execution, so that the CPU may access it at full speed. Device firmware may be stored in a serial flash device, and then copied into SDRAM or SRAM when the device is powered up. [6] Using an external serial flash device rather than on chip flash removes the need for significant process compromise (a process that is good for high speed logic is generally not good for flash and vice versa). Once it is decided to read the firmware in as one big block it is common to add compression to allow a smaller flash chip to be used. Typical applications for serial flash include storing firmware for hard drives, Ethernet controllers, DSL modems, wireless network devices, etc. [edit] Flash file systems
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 Because of the particular characteristics of flash memory, it is best used with specifically designed file systems which spread writes over the media and deal with the long erase times of NOR flash blocks. The basic concept behind flash file systems is: When the flash store is to be updated, the file system will write a new copy of the changed data over to a fresh block, remap the file pointers, then erase the old block later when it has time. One of the earliest flash file systems was Microsoft's FFS2 (presumably preceded by FFS1), for use with MS DOS in the early 1990s. Around 1994, the PCMCIA industry group approved the FTL (Flash Translation Layer) specification, which allowed a flash device to look like a FAT disk, but still have effective wear levelling. Other commercial systems such as FlashFX by Datalight were created to avoid patent concerns with FTL.
JFFS was the first flash specific file system for Linux, but it was quickly superseded by JFFS2, originally developed for NOR flash. Then YAFFS was released in 2003, dealing specifically with NAND flash, and JFFS2 was updated to support NAND flash too. In practice, these filesystems are only used for "Memory Technology Devices" ("MTD"), which are embedded flash memories which do not have a controller. Removable flash media, such as SD and CF cards and USB flash drives, have a controller (often built into the card) to perform wear levelling and error correction, so use of JFFS2 or YAFFS does not add any benefit. These removable flash memory devices are often used with the old FAT filesystem for compatibility with cameras and other portable devices. Controllerless removable flash memory devices also exist; For example, SmartMedia is even electrically compatible with the Toshiba TC58 series of NAND flash chips. [edit] Capacity
Common flash memory parts (individual internal components or "chips") range widely in capacity from kilobits to several gigabits each. Multiple chips are often arrayed to achieve higher capacities for use in devices such as the iPod nano or SanDisk Sansa e200. The capacity of flash chips generally follows Moore's law because they are produced with the same processes used to manufacture other integrated circuits. However, there have also been jumps beyond Moore's law due to innovations in technology.
In 2005, Toshiba and SanDisk developed a NAND flash chip capable of storing 1 GB of data using MLC (multi level cell) technology, capable of storing 2 bits of data per cell. In September 2005, Samsung Electronics announced that it had developed the world’s first 2 GB chip.[7]
In March 2006, Samsung announced flash hard drives with a capacity of 4 GB, essentially the same order of magnitude as smaller laptop hard drives, and in September of 2006, Samsung announced an 8 GB chip produced using a 40 nm manufacturing process.[8]
For some flash memory products such as memory cards and USB drives, as of mid 2006, 256 megabyte and smaller devices have been largely discontinued. 1 GB capacity flash memory has become the normal storage space for people who do not extensively use
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 flash memory, while more and more consumers are adopting 2 GB, 4 GB, or 8 GB flash drives. The highest capacity lays in USB with a current record of 64 GB.[citation needed][9]
Hitachi (formerly the OEM hard disk unit supplying IBM) has a competing hard drive mechanism, the Microdrive, that can fit inside the shell of a type II CompactFlash card. It has a capacity up to 8 GB. BiTMicro offers a 155 GB 3.5 " Solid State disk, named the "Edisk".[10] [edit] Speed
Flash memory cards are available in different speeds. Some are specified the approximate transfer rate of the card such as 2 MB per second, 12 MB per second, etc. The exact speed of these cards depends on which definition of "megabyte" the marketer has chosen to use.
Many cards are simply rated 100x, 130x, 200x, etc. For these cards the base assumption is that 1x is equal to 150 kibibytes per second. This was the speed at which the first CD drives could transfer information, which was adopted as the reference speed for flash memory cards. Thus, when comparing a 100x card to a card capable of 12 MiB per second the following calculations are useful:
150 KiB x 100 = 15000 KiB per second = 14.65 MiB per second.
Therefore, the 100x card is 14.65 MiB per second, which is faster than the card that is measured at 12 MiB per second. [edit] Flash memory as a replacement for hard drives
Main article: Solid state drive
An obvious extension of flash memory would be as a replacement for hard disks. Flash memory does not have the mechanical limitations and latencies of hard drives, so the idea of a solid state drive, or SSD, is attractive when considering speed, noise, power consumption, and reliability.
There remain some aspects of flash based SSD's that make the idea unattractive. Most importantly, the cost per gigabyte of flash memory remains significantly higher than that of platter based hard drives. Although this ratio is decreasing rapidly for flash memory, it is not yet clear that flash memory will catch up to the capacities and affordability offered by platter based storage. Still, research and development is sufficiently vigorous that it is not clear that it will not happen, either.
There is also some concern that the finite number of erase/write cycles of flash memory would render flash memory unable to support an operating system. This seems to be a
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 decreasing issue as warranties on flash based SSD's are approaching those of current hard drives.[11][12]
As of May 24, 2006, South Korean consumer electronics manufacturer Samsung Electronics had released the first flash memory based PCs, the Q1 SSD and Q30 SSD, both of which have 32 GB SSDs.[13]
At the Las Vegas CES 2007 Summit Taiwanese memory company A DATA showcased SSD hard disk drives based on Flash technology in capacities of 32 GB, 64 GB and 128 GB.[14] Sandisk announced an OEM 32 GB 1.8" SSD drive at CES 2007.[15]
The XO 1, developed by the One Laptop Per Child (OLPC) association, uses flash memory rather than a hard drive.
As of June 2007, a South Korean company called Mtron claims the fastest SSD with sequential read/write speeds of 100 MB/80 MB per second.[1]
Rather than entirely replacing the hard drive, hybrid techniques such as hybrid drive and ReadyBoost attempt to combine the advantages of both technologies, using flash as a high speed cache for files on the disk that are often referenced, but rarely modified, such as application and operation system executable files. [edit] See also
• CompactFlash • Wear leveling • DataFlash • Open NAND Flash Interface Working Group • YAFFS [edit] External links
• Open NAND Flash Interface Working Group • Flash vs. Other Memory Types • A Nonvolatile Memory Overview • How Flash Memory Works • SanDisk Flash Memory Plant • What is NAND Flash • NAND Flash Applications • NAND Flash Applications Design Guide from Toshiba (explains the low level details of interfacing with common NAND flash chips) [edit] References
• Digital Memories Survive Extremes
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007 • Flash memory database
1. ^ SSD Myths and Legends 2. ^ http://www.onfi.org/docs/ONFI_1_0_Gold.pdf 3. ^ A list of ONFI members is available at http://www.onfi.org/onfimembers.html. 4. ^ http://www.intel.com/pressroom/archive/releases/20070530corp.htm 5. ^ a b c See pages 5 7 of Toshiba's "NAND Applications Design Guide" under External links. 6. ^ Many serial flash devices implement a bulk read mode and incorporate an internal address counter, so that it is trivial to configure them to transfer their entire contents to RAM on power up. When clocked at 50 MHz, for example, a serial flash could transfer a 64 Mbit firmware image in less than two seconds. 7. ^ http://www.xbitlabs.com/news/memory/display/20050912212649.html 8. ^ http://tgdaily.com/2006/09/11/samsung_40nm_flash/ 9. ^ http://www.pcnation.com/web/details.asp?affid=909&item=H76595 10. ^ http://www.tgdaily.com/2005/09/13/bitmicro_rolls_out_155_gig_solid/ 11. ^ http://www.storagesearch.com/semico art1.html 12. ^ http://www.storagesearch.com/bitmicro art1.html 13. ^ http://www.samsung.com/he/presscenter/pressrelease/pressrelease_20060524_000 0257996.asp 14. ^ Future of Flash revealed 15. ^ SanDisk SSD Solid State Drives
y513719001187192499 from [email protected] was published by D-Publish on August 15, 2007