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DRAM EMAIL GIM Teams!!!/Teaming Issues •Memories in Verilog •Memories on the FPGA

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DRAM EMAIL GIM Teams!!!/Teaming Issues •Memories in Verilog •Memories on the FPGA Memories & More •Overview of Memories •External Memories •SRAM (async, sync) •Flash •DRAM EMAIL GIM teams!!!/teaming Issues •Memories in Verilog •Memories on the FPGA 10/18/18 6.111 Fall 2018 1 Memories: a practical primer • The good news: huge selection of technologies • Small & faster vs. large & slower • Every year capacities go up and prices go down • Almost cost competitive with hard disks: high density, fast flash memories • Non-volatile, read/write, no moving parts! (robust, efficient) • The bad news: perennial system bottleneck • Latencies (access time) haven’t kept pace with cycle times • Separate technology from logic, so must communicate between silicon, so physical limitations (# of pins, R’s and C’s and L’s) limit bandwidths • New hopes: capacitive interconnect, 3D IC’s • Likely the limiting factor in cost & performance of many digital systems: designers spend a lot of time figuring out how to keep memories running at peak bandwidth • “It’s the memory - just add more faster memory” 10/18/18 6.111 Fall 2018 2 How do we Electrically Remember Things? • We can convey/transfer information with voltages that change over time • How can we store information in an electrically accessible manner? • Store in either: • Electric Field • Magnetic Field 10/18/18 6.111 Fall 2018 3 Mostly focus on rewritable • Punched Cards have existed as electromechanical program storage since ~1800s • We’re mostly concerned with rewritable storage mechanisms today (cards were true Computer program in punched card format ROMs) https://en.wiKipedia.org/wiKi/Computer_programming_in_the_ punched_card_era 10/18/18 6.111 Fall 2018 4 Electronic Memories in History http://www.computerhistory.org/timeline/memory-storage/ • Drum Memory: • Information stored magnetically on large rotating metallic cylinder • Could read/write to it • Did not require periodic refresh • Non-volatile (last after power cycles off) 10/18/18 6.111 Fall 2018 5 Delay Line Memory • Early form of FIFO memory (talk about later) • Generate a wave pattern which exists for a few milliseconds in mercury • Recover on the other end and either reload or use • Requires refresh circuitry • Volatile (info lost soon after power cut) 10/18/18 6.111 Fall 2018 6 William’s Tube • Take advantage of non-negligible decay time of phosphors on CRT to store data • Project data image • Little bit later (milliseconds) recover it . • Either use it or reproject it for later use • Requires periodic refresh (obv.) 10/18/18 6.111 Fall 2018 7 Core Memory • MIT! • Store 1’s and 0’s in the magnetic field of small torroids (magnetic cores) • Where the term “core dump” comes from. • Used up until mid 70’s https://en.wikipedia.org/wiki/Magnetic- core_memory#/media/File:KL_Kernspeicher_ • Few on display in fourth Makro_1.jpg floor of 38 • Non volatile! 10/18/18 6.111 Fall 2018 8 Memory Classification & Metrics Read-Write Memory Non-Volatile Read-Only Random Read-Write Sequential Memory Access Memory Access EPROM Mask- SRAM FIFO E2PROM Programmed DRAM FLASH ROM Key Design Metrics: 1. Memory Density (number of bits/mm2) and Size 2. Access Time (time to read or write) and Throughput 3. Power Dissipation 10/18/18 6.111 Fall 2018 9 Memory Array’s (Inspiration in Switches) • If you have 16 switches, you can convey that using 16 independent wires (one-hot encoding) • Alternatively if you assemble in an array/matrix, you can do With correct interfacing you can still with 8 wires (if you add think of this as a 16X1 array of some interfacing switches!!! Even though it isn’t circuitry) • Same situation in memory 10/18/18 6.111 Fall 2018 10 Memory Array Architecture 2LxM memory Small Cells ® small mosfets ® small dV on bit line 2L-K Bit Line Storage Cell Row DeCode AK 2L-K row AK+1 Word Line by Mx2K column AL-1 cell array M*2K Amplify swing to Sense Amps/Driver rail-to-rail amplitude A0 Column Decode AK-1 SeleCts appropriate word (i.e., multiplexer) Input-Output (M bits) 10/18/18 6.111 Fall 2018 11 Using External Memory Devices Write Write enable Tri-state Driver Address Row Decoder Logic Chip Enable Pins … Memory Matrix enable Data Pins in out If enable=0 … Read Write enable Logic out = Z (high Z) Sense Amps/Drivers Output Enable Column Decoder If enable =1 out = in • Address pins drive row and • Output Enable gates the chip’s column decoders tristate driver • Data pins are bidirectional: • Write Enable sets the memory’s shared by reads and writes read/write mode • Chip Enable/Chip Select acts as a Concept of “Data Bus” “master switch” 10/18/18 6.111 Fall 2018 12 MCM6264C 8K x 8 Static RAM Same (bidirectional) data bus used for On the outside: reading and writing 13 Address Chip Enables (E1 and E2) E1 must be low and E2 must be high to Chip Enables E1 enable the chip 8 E2 MCM6264C Data Write Enable (WE) Write Enable WE DQ[7:0] When low (and chip enabled), values on data bus are written to location Output Enable OE selected by address bus Output Enable (OE or G) When low (and chip is enabled), data On the inside: bus is driven with value of selected memory location A2 DQ[7:0] A3 E1 A4 … Memory matrix E2 A5 256 rows A7 32 Column A8 Decoder Row A9 A11 W … G Pinout Sense Amps/Drivers Column Decoder A0 A1 A6 A10 A12 10/18/18 6.111 Fall 2018 13 SRAM 10/18/18 6.111 Fall 2018 14 Static RAM (SRAM) Cell (The 6-T Cell) !" !" Write: Set BL, BL to (0,VDD ) or (VDD,0) then enable WL (= VDD) Read: Disconnect drivers from BL and BL, then enable WL (=VDD). Sense a small change in BL or BL § State held by cross-coupled inverters (M1-M4) § Retains state as long as power supply turned on § Feedback must be overdriven to write into the memory 10/18/18 6.111 Fall 2018 15 Reading an Asynchronous SRAM Address Address Valid Access time (from address valid) E1 Access time (from enable low) OE Bus enable time Bus tristate time (Tristate) Data Data Valid E2 assumed high (enabled), W =1 (read mode) • Read cycle begins when all enable signals (E1, E2, OE) are active • Data is valid after read access time • Access time is indicated by full part number: MCM6264CP-12 à 12ns • Data bus is tristated shortly after OE or E1 goes high 10/18/18 6.111 Fall 2018 16 Address Controlled Reads Address Address 1 Address 2 Address 3 Access time (from address valid) Contamination time E1 OE Bus enable time Bus tristate time Data Data 1 Data 2 Data 3 E2 assumed high (enabled), WE =1 (read mode) • Can perform multiple reads without disabling chip • Data bus follows address bus, after some delay 10/18/18 6.111 Fall 2018 17 Writing to Asynchronous SRAM Address Address Valid Address setup time Address hold time E1 Write pulse width WE Data setup time Data hold time Data Data Valid E2 and OE are held high • Data latched when WE or E1 goes high (or E2 goes low) • Data must be stable at this time • Address must be stable before WE goes low • Write waveforms are more important than read waveforms • Glitches to address can cause writes to random addresses! 10/18/18 6.111 Fall 2018 18 Sample Memory Interface Logic Write cycle Read cycle Clock/E1 OE WE Address Address for write Address for read Data Data for write Data read Write occurs here, when Data can be Drive data bus only E1 goes high latched here VCC when clock is low FPGA E2 • Ensures address are ext_chip_enable Clock E1 stable for writes ext_write_enable Control W SRAM FSM ext_output_enable • Prevents bus G contention (write, read, reset) int_data • Minimum clock Write data D Q Data[7:0] Read data Q D period is twice ext_data Address memory access time D Q Address[12:0] ext_address 10/18/18 6.111 Fall 2018 19 Tristate Data Buses in Verilog CE (active low) OE (active_low) clk int_data Write data D Q ext_data Read data Q D output CE,OE; // these signals are active low inout [7:0] ext_data; inout The reg [7:0] read_data,int_data wire [7:0] write_data; always @(posedge clk) begin int_data <= write_data; read_data <= ext_data; end // Use a tristate driver to set ext_data to a value assign ext_data = (~CE & OE) ? int_data : 8’hZZ; 10/18/18 6.111 Fall 2018 20 Synchronous SRAM Memories • Clocking provides input synchronization and encourages more reliable operation at high speeds Write Row Decoder Row Write Enable Logic Chip Enable … Memory Address matrix Pins Data Pins … Read Sense Amps/Drivers Logic Output Enable Column Decoder long “flow-through” combinational difference between read and write timings creates path creates high CLK-Q delay wasted cycles (“wait states”) R1 R2 W3 R4 W5 CE WE CLK Address A1 A2 A3 A4 A5 Data Q1 Q2 D3 Q4 D5 10/18/18 6.111 Fall 2018 21 ZBT Eliminates the Wait State But we have to wait • The wait state occurs because: for bus to clearL out • On a read, data is available after the clock edge read data • On a write, data is set up before the clock edge • ZBT (“zero bus turnaround”) memories change the rules for writes • On a write, data is set up after the clock edge (so that it is read on the following edge) • Result: no wait states, higher memory throughput R1 R2 W3 R4 W5 CE WE CLK Address A1 A2 A3 A4 A5 Data Q1 Q2 D3 Q4 D5 Write to A3 Data D3 Write to A5 Data D5 requested loaded requested loaded 10/18/18 6.111 Fall 2018 22 Pipelining Allows Faster CLK • Pipeline the memory by registering its output • Good: Greatly reduces CLK-Q delay, allows higher clock (more throughput) • Bad: Introduces an extra cycle before data is available (more latency) ZBT Row Decoder Row Write Write Enable Logic Chip Enable … Memory Address matrix As an example, see Pins Data Pins the CY7C147X ZBT Synchronous SRAM … Read Sense Amps/Drivers Logic Output Enable Column Decoder pipelining register R1 R2 W3 R4 W5 CE WE CLK Address A1 A2 A3 A4 A5 Q Q D Q D Data one-cycle 1 2 3 4 5 latency..
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