DOCSLIB.ORG

DRAM EMAIL GIM Teams!!!/Teaming Issues •Memories in Verilog •Memories on the FPGA

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

Memories & More •Overview of Memories •External Memories •SRAM (async, sync) •Flash •DRAM EMAIL GIM teams!!!/teaming Issues •Memories in Verilog •Memories on the FPGA 10/18/18 6.111 Fall 2018 1 Memories: a practical primer • The good news: huge selection of technologies • Small & faster vs. large & slower • Every year capacities go up and prices go down • Almost cost competitive with hard disks: high density, fast flash memories • Non-volatile, read/write, no moving parts! (robust, efficient) • The bad news: perennial system bottleneck • Latencies (access time) haven’t kept pace with cycle times • Separate technology from logic, so must communicate between silicon, so physical limitations (# of pins, R’s and C’s and L’s) limit bandwidths • New hopes: capacitive interconnect, 3D IC’s • Likely the limiting factor in cost & performance of many digital systems: designers spend a lot of time figuring out how to keep memories running at peak bandwidth • “It’s the memory - just add more faster memory” 10/18/18 6.111 Fall 2018 2 How do we Electrically Remember Things? • We can convey/transfer information with voltages that change over time • How can we store information in an electrically accessible manner? • Store in either: • Electric Field • Magnetic Field 10/18/18 6.111 Fall 2018 3 Mostly focus on rewritable • Punched Cards have existed as electromechanical program storage since ~1800s • We’re mostly concerned with rewritable storage mechanisms today (cards were true Computer program in punched card format ROMs) https://en.wiKipedia.org/wiKi/Computer_programming_in_the_ punched_card_era 10/18/18 6.111 Fall 2018 4 Electronic Memories in History http://www.computerhistory.org/timeline/memory-storage/ • Drum Memory: • Information stored magnetically on large rotating metallic cylinder • Could read/write to it • Did not require periodic refresh • Non-volatile (last after power cycles off) 10/18/18 6.111 Fall 2018 5 Delay Line Memory • Early form of FIFO memory (talk about later) • Generate a wave pattern which exists for a few milliseconds in mercury • Recover on the other end and either reload or use • Requires refresh circuitry • Volatile (info lost soon after power cut) 10/18/18 6.111 Fall 2018 6 William’s Tube • Take advantage of non-negligible decay time of phosphors on CRT to store data • Project data image • Little bit later (milliseconds) recover it . • Either use it or reproject it for later use • Requires periodic refresh (obv.) 10/18/18 6.111 Fall 2018 7 Core Memory • MIT! • Store 1’s and 0’s in the magnetic field of small torroids (magnetic cores) • Where the term “core dump” comes from. • Used up until mid 70’s https://en.wikipedia.org/wiki/Magnetic- core_memory#/media/File:KL_Kernspeicher_ • Few on display in fourth Makro_1.jpg floor of 38 • Non volatile! 10/18/18 6.111 Fall 2018 8 Memory Classification & Metrics Read-Write Memory Non-Volatile Read-Only Random Read-Write Sequential Memory Access Memory Access EPROM Mask- SRAM FIFO E2PROM Programmed DRAM FLASH ROM Key Design Metrics: 1. Memory Density (number of bits/mm2) and Size 2. Access Time (time to read or write) and Throughput 3. Power Dissipation 10/18/18 6.111 Fall 2018 9 Memory Array’s (Inspiration in Switches) • If you have 16 switches, you can convey that using 16 independent wires (one-hot encoding) • Alternatively if you assemble in an array/matrix, you can do With correct interfacing you can still with 8 wires (if you add think of this as a 16X1 array of some interfacing switches!!! Even though it isn’t circuitry) • Same situation in memory 10/18/18 6.111 Fall 2018 10 Memory Array Architecture 2LxM memory Small Cells ® small mosfets ® small dV on bit line 2L-K Bit Line Storage Cell Row DeCode AK 2L-K row AK+1 Word Line by Mx2K column AL-1 cell array M*2K Amplify swing to Sense Amps/Driver rail-to-rail amplitude A0 Column Decode AK-1 SeleCts appropriate word (i.e., multiplexer) Input-Output (M bits) 10/18/18 6.111 Fall 2018 11 Using External Memory Devices Write Write enable Tri-state Driver Address Row Decoder Logic Chip Enable Pins … Memory Matrix enable Data Pins in out If enable=0 … Read Write enable Logic out = Z (high Z) Sense Amps/Drivers Output Enable Column Decoder If enable =1 out = in • Address pins drive row and • Output Enable gates the chip’s column decoders tristate driver • Data pins are bidirectional: • Write Enable sets the memory’s shared by reads and writes read/write mode • Chip Enable/Chip Select acts as a Concept of “Data Bus” “master switch” 10/18/18 6.111 Fall 2018 12 MCM6264C 8K x 8 Static RAM Same (bidirectional) data bus used for On the outside: reading and writing 13 Address Chip Enables (E1 and E2) E1 must be low and E2 must be high to Chip Enables E1 enable the chip 8 E2 MCM6264C Data Write Enable (WE) Write Enable WE DQ[7:0] When low (and chip enabled), values on data bus are written to location Output Enable OE selected by address bus Output Enable (OE or G) When low (and chip is enabled), data On the inside: bus is driven with value of selected memory location A2 DQ[7:0] A3 E1 A4 … Memory matrix E2 A5 256 rows A7 32 Column A8 Decoder Row A9 A11 W … G Pinout Sense Amps/Drivers Column Decoder A0 A1 A6 A10 A12 10/18/18 6.111 Fall 2018 13 SRAM 10/18/18 6.111 Fall 2018 14 Static RAM (SRAM) Cell (The 6-T Cell) !" !" Write: Set BL, BL to (0,VDD ) or (VDD,0) then enable WL (= VDD) Read: Disconnect drivers from BL and BL, then enable WL (=VDD). Sense a small change in BL or BL § State held by cross-coupled inverters (M1-M4) § Retains state as long as power supply turned on § Feedback must be overdriven to write into the memory 10/18/18 6.111 Fall 2018 15 Reading an Asynchronous SRAM Address Address Valid Access time (from address valid) E1 Access time (from enable low) OE Bus enable time Bus tristate time (Tristate) Data Data Valid E2 assumed high (enabled), W =1 (read mode) • Read cycle begins when all enable signals (E1, E2, OE) are active • Data is valid after read access time • Access time is indicated by full part number: MCM6264CP-12 à 12ns • Data bus is tristated shortly after OE or E1 goes high 10/18/18 6.111 Fall 2018 16 Address Controlled Reads Address Address 1 Address 2 Address 3 Access time (from address valid) Contamination time E1 OE Bus enable time Bus tristate time Data Data 1 Data 2 Data 3 E2 assumed high (enabled), WE =1 (read mode) • Can perform multiple reads without disabling chip • Data bus follows address bus, after some delay 10/18/18 6.111 Fall 2018 17 Writing to Asynchronous SRAM Address Address Valid Address setup time Address hold time E1 Write pulse width WE Data setup time Data hold time Data Data Valid E2 and OE are held high • Data latched when WE or E1 goes high (or E2 goes low) • Data must be stable at this time • Address must be stable before WE goes low • Write waveforms are more important than read waveforms • Glitches to address can cause writes to random addresses! 10/18/18 6.111 Fall 2018 18 Sample Memory Interface Logic Write cycle Read cycle Clock/E1 OE WE Address Address for write Address for read Data Data for write Data read Write occurs here, when Data can be Drive data bus only E1 goes high latched here VCC when clock is low FPGA E2 • Ensures address are ext_chip_enable Clock E1 stable for writes ext_write_enable Control W SRAM FSM ext_output_enable • Prevents bus G contention (write, read, reset) int_data • Minimum clock Write data D Q Data[7:0] Read data Q D period is twice ext_data Address memory access time D Q Address[12:0] ext_address 10/18/18 6.111 Fall 2018 19 Tristate Data Buses in Verilog CE (active low) OE (active_low) clk int_data Write data D Q ext_data Read data Q D output CE,OE; // these signals are active low inout [7:0] ext_data; inout The reg [7:0] read_data,int_data wire [7:0] write_data; always @(posedge clk) begin int_data <= write_data; read_data <= ext_data; end // Use a tristate driver to set ext_data to a value assign ext_data = (~CE & OE) ? int_data : 8’hZZ; 10/18/18 6.111 Fall 2018 20 Synchronous SRAM Memories • Clocking provides input synchronization and encourages more reliable operation at high speeds Write Row Decoder Row Write Enable Logic Chip Enable … Memory Address matrix Pins Data Pins … Read Sense Amps/Drivers Logic Output Enable Column Decoder long “flow-through” combinational difference between read and write timings creates path creates high CLK-Q delay wasted cycles (“wait states”) R1 R2 W3 R4 W5 CE WE CLK Address A1 A2 A3 A4 A5 Data Q1 Q2 D3 Q4 D5 10/18/18 6.111 Fall 2018 21 ZBT Eliminates the Wait State But we have to wait • The wait state occurs because: for bus to clearL out • On a read, data is available after the clock edge read data • On a write, data is set up before the clock edge • ZBT (“zero bus turnaround”) memories change the rules for writes • On a write, data is set up after the clock edge (so that it is read on the following edge) • Result: no wait states, higher memory throughput R1 R2 W3 R4 W5 CE WE CLK Address A1 A2 A3 A4 A5 Data Q1 Q2 D3 Q4 D5 Write to A3 Data D3 Write to A5 Data D5 requested loaded requested loaded 10/18/18 6.111 Fall 2018 22 Pipelining Allows Faster CLK • Pipeline the memory by registering its output • Good: Greatly reduces CLK-Q delay, allows higher clock (more throughput) • Bad: Introduces an extra cycle before data is available (more latency) ZBT Row Decoder Row Write Write Enable Logic Chip Enable … Memory Address matrix As an example, see Pins Data Pins the CY7C147X ZBT Synchronous SRAM … Read Sense Amps/Drivers Logic Output Enable Column Decoder pipelining register R1 R2 W3 R4 W5 CE WE CLK Address A1 A2 A3 A4 A5 Q Q D Q D Data one-cycle 1 2 3 4 5 latency..
Recommended publications
  • The Design of a Drum Memory System

    The Design of a Drum Memory System

    Scholars' Mine Masters Theses Student Theses and Dissertations 1967 The design of a drum memory system Frederick W. Lynch Follow this and additional works at: https://scholarsmine.mst.edu/masters_theses Part of the Electrical and Computer Engineering Commons Department: Recommended Citation Lynch, Frederick W., "The design of a drum memory system" (1967). Masters Theses. 5163. https://scholarsmine.mst.edu/masters_theses/5163 This thesis is brought to you by Scholars' Mine, a service of the Missouri S&T Library and Learning Resources. This work is protected by U. S. Copyright Law. Unauthorized use including reproduction for redistribution requires the permission of the copyright holder. For more information, please contact [email protected]. THE DESIGN OF A DRUM MEMORY SYSTEM BY FREDERICK W. LYNCH A l'HESIS 129533 submitted to the faculty of the UNIVERSITY OF MISSOURI AT ROLLA in partial fulfillment of the requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING Rolla, Missouri I"",,--;;'d I ~ 1967 rfJ·.dfl c, I ii ABSTRACT Three methods for obtaining an auxiliary memory for an SeC-6S0 (Scientific Control Corporation) digital computer are presented. A logic design is then developed on the basis of using the drum and write circuits from an available IBM-6S0 digital computer and con­ structing the remaining logic functions. The results of the logic design are the transfer equations necessary to implement the memory system. iii ACKNOWLEDGMENT The author wishes to express his sincere appreciation to his major professor, Dr. James Tracey, for guidance and support in the preparation of this thesis. iv TABLE OF CONTENTS Page ABSTRACT ii ACKNm>JLEDGlVIENT iii LIST OF FIGURES v LIST OF TABLES vi I.
  • Metal Ultrasonic Delay Lines

    Metal Ultrasonic Delay Lines

    Research Paper 2453 rOOmOI of R~eo"h of The NO tiO ~;;:if ~;=asoni;l~~i~;~~~:: Russell W . Mebs, John H. Darr, and John D. Grimsley A study was made of the applicability of a number of metals and a lloys for therm all y stable ultrasonic delay lin es. A preliminary iavestigation was made of different types of pressure holders and ad­ hesi ves for use in crystal t ransducer attachments and of the iafluence of specimen length on attenuation for valious m etals and alloy. The effect of cold-work, annealing, and specimen cross section on attenuation was a lso determined for a representati ve isoelastic alloy. Measurements of temperature variation of signal attenuation, distort ion, a nd delay t im e on a number of assembled delay lines indicated t hat an isoelastic a lloy employing over cured epoxy-resin crystal attachments gave best over-all t ransmission characteristics. No correlation was obtainable between strength and SOLl nd-transmission characteristics with varioLls cemented joints. 1. Introduction variations in pulse attenuation and distortion with acceleration or change of temperature. The ultrasonic delay line has come into wide use Only a general survey will be given of the basic in recent years with the development of radar, com­ theory of ultrasonic transmission as related to delay ~uters , and other electronic devices [1 , 2, 3, 4V It lines of 50 tLsec or less. More comprehensive 's a means for delaying a signal for a predetermined treatments have been given elsewhere [2, 4, and 5]. ~hort period to be accurately reproduced for use at _tn appropriate later instant.
  • Magnetic Storage- Magnetic-Core Memory, Magnetic Tape,RAM

    Magnetic Storage- Magnetic-Core Memory, Magnetic Tape,RAM

    Magnetic storage- From magnetic tape to HDD Juhász Levente 2016.02.24 Table of contents 1. Introduction 2. Magnetic tape 3. Magnetic-core memory 4. Bubble memory 5. Hard disk drive 6. Applications, future prospects 7. References 1. Magnetic storage - introduction Magnetic storage: Recording & storage of data on a magnetised medium A form of „non-volatile” memory Data accessed using read/write heads Widely used for computer data storage, audio and video applications, magnetic stripe cards etc. 1. Magnetic storage - introduction 2. Magnetic tape 1928 Germany: Magnetic tape for audio recording by Fritz Pfleumer • Fe2O3 coating on paper stripes, further developed by AEG & BASF 1951: UNIVAC- first use of magnetic tape for data storage • 12,7 mm Ni-plated brass-phosphorus alloy tape • 128 characters /inch data density • 7000 ch. /s writing speed 2. Magnetic tape 2. Magnetic tape 1950s: IBM : patented magnetic tape technology • 12,7 mm wide magnetic tape on a 26,7 cm reel • 370-730 m long tapes 1980: 1100 m PET –based tape • 18 cm reel for developers • 7, 9 stripe tapes (8 bit + parity) • Capacity up to 140 MB DEC –tapes for personal use 2. Magnetic tape 2014: Sony & IBM recorded 148 Gbit /squareinch tape capacity 185 TB! 2. Magnetic tape Remanent structural change in a magnetic medium Analog or digital recording (binary storage) Longitudinal or perpendicular recording Ni-Fe –alloy core in tape head 2. Magnetic tape Hysteresis in magnetic recording 40-150 kHz bias signal applied to the tape to remove its „magnetic history” and „stir” the magnetization Each recorded signal will encounter the same magnetic condition Current in tape head proportional to the signal to be recorded 2.
  • Influence of U.S. Cryptologic Organizations on the Digital Computer Industry

    Influence of U.S. Cryptologic Organizations on the Digital Computer Industry

    UNCLASSIFIED Influence of U.S. Cryptologic Organizations on the Digital Computer Industry SAMUELS. SNYDER This article was originally published in two parts in the Fall 1977 and Winter 1978 issues o{Cryptologic Spectrum (Vol. 7, No. 4 and Vol. 8, No. 2). INTRODUCTION An unfortunate aspect of historical accounts of computer lore in open sources is the omission - conspicuously to some of us - of mention of the U.S. cryptologic organizations, or of the contributions by these organizations which helped in laying the foundation of the computer industry. NSA, and other cryptologic organizations, have been required over the years to observe a policy of anonymity, and with good reason. But in the age of maturing appreciation of the role of computers in nearly all civilized endeavors, it is time to acknowledge, for the first time, their outstanding contributions to the computer industry. The reader will notice the absence of remarks concerning software efforts by cryptologic organizations. While this side of their operations received its proper share of support, space restrictions preclude its inclusion in this article. Also, the Army and Navy cryptologic services have frequently changed organizational titles throughout the years. Therefore, to avoid confusion in this article, they are, previous to 1945, referred to as "Army," "Navy," "service cryptologic organizations," and the like. Too, NSA's predecessor organization, AFSA, was established in 1949, and NSA in 1952. Consequently, references to "NSA" and "Agency" are, on occasion, used interchangeably, the particular agency referred to depending upon the time period being discussed. EARLY DEVELOPMENTS The development of the U.S. computer industry might have been delayed for years ifit had not been for the stimulus and financial support of the U.S.
  • Computer Peripheral Memory System Forecast

    Computer Peripheral Memory System Forecast

    OF NBS H^^LK,!,, STAND S. TECH PUBLICATIONS | COMPUTER SUici^CZ^i TECHNOLOGY: COMPUTER PERIPHERAL MEMORY SYSTEM FORECAST QC 100 U57 NBS Special Publication 500-45 #500-45 U.S. DEPARTMENT OF COMMERCE 1979 National Bureau of Standards NATIONAL BUREAU OF STANDARDS The National Bureau of Standards' was established by an act of Congress March 3, 1901 . The Bureau's overall goal is to strengthen and advance the Nation's science and technology and facilitate their effective application for public benefit. To this end, the Bureau conducts research and provides: (1) a basis for the Nation's physical measurement system, (2) scientific and technological services for industry and government, (3) a technical basis for equity in trade, and (4) technical services to promote public safety. The Bureau's technical work is performed by the National Measurement Laboratory, the National Engineering Laboratory, and the Institute for Computer Sciences and Technology. THE NATIONAL MEASUREMENT LABORATORY provides the national system of physical and chemical and materials measurement; coordinates the system with measurement systems of other nations and furnishes essential services leading to accurate and uniform physical and chemical measurement throughout the Nation's scientific community, industry, and commerce; conducts materials research leading to improved methods of measurement, standards, and data on the properties of materials needed by industry, commerce, educational institutions, and Government; provides advisory and research services to other Government Agencies; develops, produces, and distributes Standard Reference Materials; and provides calibration services. The Laboratory consists of the following centers: Absolute Physical Quantities^ — Radiation Research — Thermodynamics and Molecular Science — Analytical Chemistry — Materials Science.
  • Memory Krste Asanovic Krste@Eecs.Berkeley.Edu

    Memory Krste Asanovic [email protected]

    CS252 Graduate Computer Architecture Fall 2015 Lecture 11: Memory Krste Asanovic [email protected] http://inst.eecs.berkeley.edu/~cs252/fa15 CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 Last Time in Lecture 10 VLIW Machines § Compiler-controlled stac scheduling § Loop unrolling § SoEware pipelining § Trace scheduling § Rotang register file § Predicaon § Limits of stac scheduling CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 2 Early Read-Only Memory Technologies Punched cards, From early 1700s through Jaquard Loom, Punched paper tape, Babbage, and then IBM instrucCon stream in Harvard Mk 1 Diode Matrix, EDSAC-2 µcode store IBM Balanced Capacitor ROS IBM Card Capacitor ROS CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 3 Early Read/Write Main Memory Technologies Babbage, 1800s: Digits stored on mechanical wheels Williams Tube, Manchester Mark 1, 1947 Mercury Delay Line, Univac 1, 1951 Also, regenerave capacitor memory on Atanasoff-Berry computer, and rotang magneCc drum memory on IBM 650 CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 4 MIT Whirlwind Core Memory CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 5 Core Memory § Core memory was first large scale reliable main memory - invented by Forrester in late 40s/early 50s at MIT for Whirlwind project § Bits stored as magneCzaon polarity on small ferrite cores threaded onto two-dimensional grid of wires § Coincident current pulses on X and Y wires would write cell and also sense original state (destrucCve reads) § Robust, non-volale storage § Used on space shugle computers § Cores threaded onto wires by hand (25 billion a year at peak producCon) § Core access Cme ~ 1µs DEC PDP-8/E Board, 4K words x 12 bits, (1968) CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 6 Semiconductor Memory § Semiconductor memory began to be compeCCve in early 1970s - Intel formed to exploit market for semiconductor memory - Early semiconductor memory was Stac RAM (SRAM).
  • Lecture 8: Main Memory System

    Lecture 8: Main Memory System

    18-740/640 Computer Architecture Lecture 8: Main Memory System Prof. Onur Mutlu Carnegie Mellon University Fall 2015, 9/28/2015 Required Readings Required Reading Assignment: • Sec. 1 & 3 of B. Jacob, “The Memory System: You Can’t Avoid It, You Can’t Ignore It, You Can’t Fake It,” Synthesis Lectures on Computer Architecture, 2009. Recommended References: • O. Mutlu and L. Subramanian, “Research Problems and Opportunities in Memory Systems,” Supercomputing Frontiers and Innovations, 2015. • Lee et al., “Phase Change Technology and the Future of Main Memory,” IEEE Micro, Jan/Feb 2010. • Y. Kim, W. Yang, O. Mutlu, “Ramulator: A Fast and Extensible DRAM Simulator,” IEEE Computer Architecture Letters, May 2015. 2 State-of-the-art in Main Memory… Onur Mutlu and Lavanya Subramanian, "Research Problems and Opportunities in Memory Systems" Invited Article in Supercomputing Frontiers and Innovations (SUPERFRI), 2015. 3 Recommended Readings on DRAM DRAM Organization and Operation Basics Sections 1 and 2 of: Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA 2013. http://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf Sections 1 and 2 of Kim et al., “A Case for Subarray-Level Parallelism (SALP) in DRAM,” ISCA 2012. http://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf DRAM Refresh Basics Sections 1 and 2 of Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012. http://users.ece.cmu.edu/~omutlu/pub/raidr-dram- refresh_isca12.pdf 4 Simulating Main Memory How to evaluate future main memory systems? An open-source simulator and its brief description Yoongu Kim, Weikun Yang, and Onur Mutlu, "Ramulator: A Fast and Extensible DRAM Simulator" IEEE Computer Architecture Letters (CAL), March 2015.
  • Random Access Memory (Ram)

    Random Access Memory (Ram)

    www.studymafia.org A Seminar report On RANDOM ACCESS MEMORY (RAM) Submitted in partial fulfillment of the requirement for the award of degree of Bachelor of Technology in Computer Science SUBMITTED TO: SUBMITTED BY: www.studymafia.org www.studymafia.org www.studymafia.org Acknowledgement I would like to thank respected Mr…….. and Mr. ……..for giving me such a wonderful opportunity to expand my knowledge for my own branch and giving me guidelines to present a seminar report. It helped me a lot to realize of what we study for. Secondly, I would like to thank my parents who patiently helped me as i went through my work and helped to modify and eliminate some of the irrelevant or un-necessary stuffs. Thirdly, I would like to thank my friends who helped me to make my work more organized and well-stacked till the end. Next, I would thank Microsoft for developing such a wonderful tool like MS Word. It helped my work a lot to remain error-free. Last but clearly not the least, I would thank The Almighty for giving me strength to complete my report on time. www.studymafia.org Preface I have made this report file on the topic RANDOM ACCESS MEMORY (RAM); I have tried my best to elucidate all the relevant detail to the topic to be included in the report. While in the beginning I have tried to give a general view about this topic. My efforts and wholehearted co-corporation of each and everyone has ended on a successful note. I express my sincere gratitude to …………..who assisting me throughout the preparation of this topic.
  • History Timeline by Jeff Drobman (C) 2015 === 1889 - Punch Cards - Herman Hollerith (Of IBM Forerunner) Invented "IBM" Punch Cards to Be Used for the 1890 Census

    History Timeline by Jeff Drobman (C) 2015 === 1889 - Punch Cards - Herman Hollerith (Of IBM Forerunner) Invented "IBM" Punch Cards to Be Used for the 1890 Census

    Computer Memory History Timeline by Jeff Drobman (C) 2015 === 1889 - Punch cards - Herman Hollerith (of IBM forerunner) invented "IBM" punch cards to be used for the 1890 census. 1932 - Drum memory 1947 - Delay line memory 1949 - Magnetic CORE memory 1950 - Magnetic TAPE memory 1955 - Magnetic DISK memory - IBM RAMAC was first one 1957 - Plated wire memory 1962 - Thin film memory 1968 (ca) - Paper tape - Had beginnings dating back to 1846, but became widely used with teletype machines such as the Teletype Model 33 ASR, which were adopted early on by minicomputers as a primitive terminal. 1970 - Bubble memory 1970 - DRAM - Invented by Intel, first device was the 1101, organized as 256x1, followed by the 4x larger (1024x1) 1103(A) -- regarded as the world's first commercial DRAM (intro in October 1970). 1971 - Bipolar SRAM - Fairchild 256x1 (note IBM made a 16-bit SRAM in late 1960s. AMD made a second source of a 64x1 SRAM by Fairchild in 1971.) 1971 - EPROM - Invented by Dov Frohman of Intel as the i1702, a 2K-bit (256x8) EPROM. 1971 - "Floppy" disks -- First were 8-inch, hence very flexible ("floppy"). The 8" became commercially available in 1971. 1973 (ca) - Magnetic TAPE CASSETTE memory 1976 - Shugart Associates introduced the first 5¼-inch floppy (flexible) disk drive 1977 - EEPROM - invented by Eli Harari at Hughes - a BYTE erasable device 1979 - CMOS SRAM (static RAM, 4T/6T cell, implemented as a latch) - first introduced by HP then its spinoff as Integrated Device Technology. I believe first devices were 1K (1024x1), and later organized as x4 then x8.
  • History of Digital Storage White Paper

    History of Digital Storage White Paper

    History of Digital Storage Dean Klein Vice President of System Memory Development Micron Technology, Inc. December 15, 2008 Purpose Introduction: Throughout modern history many and various digital The Need to Store Data storage systems have been researched, developed, Since men first scribbled on cave walls, humanity has manufactured, and eventually surpassed in an effort to recognized the instrinic value of information and has address ever-increasing demands for density, operating employed a variety of ways and means to safely store speed, low latency, endurance, and economy.1 This cycle it. The ability to reference numbers for calculation or to of innovation has lead us to a new generation of NAND review information for planning, learning, and action Flash memory-based solid state drives (SSDs) that repre- is fundamental since “all computations, either mental, sent the next evolutionary step in both enterprise and mechanical, or electronic require a storage system of consumer storage applications. some kind, whether the numbers be written on paper, remembered in our brain, counted on the mechanical This paper surveys the memory storage landscape of devices of a gear, punched as holes in paper, or translated the past 50 years—starting at the beginning of digital into electronic circuitry.”2 storage and paying homage to IBM’s groundbreaking RAMAC disk storage unit and StorageTek’s DRAM-based In day-to-day life, this fundamental need to store data SSD; then enumerating the benefits of modern NAND generates innumerable documents, spreadsheets, files, Flash memory and advanced SSDs; and finally looking e-mails, and trillions of other work-related bytes all forward to the near-future possibilities of nonvolatile stored on disks around the globe.
  • The Graphic Display of Computer Memory Data

    The Graphic Display of Computer Memory Data

    University of Windsor Scholarship at UWindsor Electronic Theses and Dissertations Theses, Dissertations, and Major Papers 7-21-1969 The graphic display of computer memory data. Satish P. Agrawal University of Windsor Follow this and additional works at: https://scholar.uwindsor.ca/etd Recommended Citation Agrawal, Satish P., "The graphic display of computer memory data." (1969). Electronic Theses and Dissertations. 6548. https://scholar.uwindsor.ca/etd/6548 This online database contains the full-text of PhD dissertations and Masters’ theses of University of Windsor students from 1954 forward. These documents are made available for personal study and research purposes only, in accordance with the Canadian Copyright Act and the Creative Commons license—CC BY-NC-ND (Attribution, Non-Commercial, No Derivative Works). Under this license, works must always be attributed to the copyright holder (original author), cannot be used for any commercial purposes, and may not be altered. Any other use would require the permission of the copyright holder. Students may inquire about withdrawing their dissertation and/or thesis from this database. For additional inquiries, please contact the repository administrator via email ([email protected]) or by telephone at 519-253-3000ext. 3208. INFORMATION TO USERS This manuscript has been reproduced from the microfilm master. UMI films the text directly from the original or copy submitted. Thus, some thesis and dissertation copies are in typewriter face, while others may be from any type of computer printer. The quality of this reproduction is dependent upon the quality of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleedthrough, substandard margins, and improper alignment can adversely affect reproduction.
  • History of Computer Memory * in 1932 Gustav Tauschek Invents Drum

    History of Computer Memory * in 1932 Gustav Tauschek Invents Drum

    History of Computer Memory * In 1932 Gustav Tauschek invents drum memory in Austria. * 1936 Konrad Zuse applies for a patent for his mechanical memory to be used in his computer. This computer memory is based on sliding metal parts. * 1939 Helmut Schreyer invents a prototype memory using neon lamps. * 1942 The Atanasoff-Berry Computer has 60 50-bit words of memory in the form of capacitors mounted on two revolving drums. For secondary memory it uses punch cards. * 1947 Frederick Viehe of Los Angeles, applies for a patent for an invention that uses magnetic core memory. Magnetic drum memory is independently invented by several people. * 1949 Jay Forrester conceives the idea of magnetic core memory as it is to become commonly used, with a grid of wires used to address the cores. The first practical form manifests in 1952-53 and renders obsolete previous types of computer memory. * 1950 Ferranti Ltd. completes the first commercial computer with 256 40-bit words of main memory and 16K words of drum memory. Only eight were sold. * 1951 Jay Forrester files a patent for matrix core memory. * 1952 The EDVAC computer is completed with 1024 44-bit words of ultrasonic memory. A core memory module is added to the ENIAC computer. * 1955 An Wang was issued U.S. patent #2,708,722 with 34 claims for magnetic memory core. * 1966 Hewlett-Packard releases their HP2116A real-time computer with 8K of memory. The newly formed Intel starts sell a semiconductor chip with 2,000 bits of memory. * 1968 USPTO grants patent 3,387,286 to IBM's Robert Dennard for a one-transistor DRAM cell.