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Memory Krste Asanovic Krste@Eecs.Berkeley.Edu CS252 Graduate Computer Architecture Fall 2015 Lecture 11: Memory Krste Asanovic [email protected] http://inst.eecs.berkeley.edu/~cs252/fa15 CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 Last Time in Lecture 10 VLIW Machines § Compiler-controlled stac scheduling § Loop unrolling § SoEware pipelining § Trace scheduling § Rotang register file § Predicaon § Limits of stac scheduling CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 2 Early Read-Only Memory Technologies Punched cards, From early 1700s through Jaquard Loom, Punched paper tape, Babbage, and then IBM instrucCon stream in Harvard Mk 1 Diode Matrix, EDSAC-2 µcode store IBM Balanced Capacitor ROS IBM Card Capacitor ROS CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 3 Early Read/Write Main Memory Technologies Babbage, 1800s: Digits stored on mechanical wheels Williams Tube, Manchester Mark 1, 1947 Mercury Delay Line, Univac 1, 1951 Also, regenerave capacitor memory on Atanasoff-Berry computer, and rotang magneCc drum memory on IBM 650 CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 4 MIT Whirlwind Core Memory CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 5 Core Memory § Core memory was first large scale reliable main memory - invented by Forrester in late 40s/early 50s at MIT for Whirlwind project § Bits stored as magneCzaon polarity on small ferrite cores threaded onto two-dimensional grid of wires § Coincident current pulses on X and Y wires would write cell and also sense original state (destrucCve reads) § Robust, non-volale storage § Used on space shugle computers § Cores threaded onto wires by hand (25 billion a year at peak producCon) § Core access Cme ~ 1µs DEC PDP-8/E Board, 4K words x 12 bits, (1968) CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 6 Semiconductor Memory § Semiconductor memory began to be compeCCve in early 1970s - Intel formed to exploit market for semiconductor memory - Early semiconductor memory was Stac RAM (SRAM). SRAM cell internals similar to a latch (cross-coupled inverters). § First commercial Dynamic RAM (DRAM) was Intel 1103 - 1Kbit of storage on single chip - charge on a capacitor used to hold value - Value has to be regularly read and wrigen back, hence dynamic Semiconductor memory quickly replaced core in ‘70s CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 7 One-Transistor Dynamic RAM [Dennard, IBM] 1-T DRAM Cell word access transistor TiN top electrode (V ) V REF REF Ta2O5 dielectric bit Storage capacitor (FET gate, trench, stack) poly W boom word electrode line access transistor CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 8 Modern DRAM Cell Structure [Samsung, sub-70nm DRAM, 2004] CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 9 DRAM Conceptual Architecture bit lines Col. Col. 1 2M word lines Row 1 N Row 2N Row Address Decoder Memory cell M (one bit) N+M Column Decoder & Sense Amplifiers Data D § Bits stored in 2-dimensional arrays on chip § Modern chips have around 4-8 logical banks on each chip § each logical bank physically implemented as many smaller arrays CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 10 DRAM Physical Layout Serializer and driver (begin of write data bus) Row logic Column logic local wordline driver stripe Center stripe local wordline (gate poly) master wordline (M2 - Al) 1:8 bitline sense-amplifier stripe local array data lines bitlines (M1 - W) Array block Buffer (bold line) column select line (M3 - Al) master array data lines (M3 - Al) Sub-array Control logic Figure 1. Physical Floorplan oF a DRAM. A DRAM actually contains a very large number oF small DRAMs called sub-arrays. logic includes column address decoding, column redundancy II. DRAM TECHNOLOGY AND ARCHITECTURE and drivers[ Vogelsang For the column, MICRO-2010 ] select lines as well as the DRAMs are commoditized high volume products which secondary sense-ampliFiers which sense or drive the11 array needCS252, Fall 2015, Lecture 11 to have very low manufacturing costs. This© Krste Asanovic, 2015 puts master data lines. The center stripe contains all other logic: signiFicant constraints on the technology and architecture. the data and control pads and interFace, central control logic, The three most important Factors For cost are the cost oF a voltage regulators and pumps oF the power system and waFer, the yield and the die area. Cost oF a waFer can be kept circuitry to support efFicient manuFacturing test. Circuitry low if a simple transistor process and Few metal levels are and buses in the center stripe are usually shared between used. Yield can be optimized by process optimization and by banks to save area. Concurrent operation of banks is optimizing the amount of redundancy. Die area optimization thereFore limited to that portion oF an operation that takes is achieved by keeping the array efFiciency (ratio of cell area place inside a bank. For example the delay between two to total die area) as high as possible. The optimum approach activate commands to diFFerent banks is limited by the time it changes very little even when the cell area is shrunk takes to decode commands and addresses and trigger the significantly over generations. DRAMs today use a transistor command at a bank. Interleaving oF reads and writes From process with Few junction optimizations, poly-Si gates and and to diFFerent banks is limited by data contention on the relatively high threshold voltage to suppress leakage. This shared data bus in the center stripe. Operations inside process is much less expensive than a logic process but also diFFerent banks can take place concurrently; one bank can For much lower perFormance. It requires higher operating example be activating or precharging a wordline while voltages than both high perFormance and low active power another bank is simultaneously streaming data. logic processes. Keeping array efFiciency constant requires The enlargement oF a small part oF an array block at the shrinking the area oF the logic circuits on a DRAM at the right side of Figure 1 shows the hierarchical structure of the same rate as the cell area. This is difFicult as it is easier to array block. Hierarchical wordlines and array data lines shrink the very regular pattern oF the cells than which were First developed in the early 1990s [5], [6] are lithographically more complex circuitry. In addition the now used by all major DRAM vendors. Master wordlines, increasing complexity oF the interface requires more circuit column select lines and master array data lines are the area. interface between the array block and the rest oF the DRAM Figure 1 shows the Floorplan oF a typical modern DDR2 circuitry. Individual cells connect to local wordlines and or DDR3 DRAM and an enlargement of the cell array. The bitlines, bitlines are sensed or driven by bitline sense- eight array blocks correspond to the eight banks oF the amplifiers which connect to column select lines and local DRAM. Row logic to decode the row address, implement array data lines. The circuitry making the connection row redundancy and drive the master wordlines is placed between local lines and master lines is placed in the local between the banks. At the other edge of the banks column wordline driver stripe and bitline sense-ampliFier stripe 364 DRAM Packaging (Laptops/Desktops/Servers) ~7 Clock and control signals DRAM Address lines mulCplexed chip row/column address ~12 Data bus (4b,8b,16b,32b) § DIMM (Dual Inline Memory Module) contains mulCple chips with clock/control/address signals connected in parallel (someCmes need buffers to drive signals to all chips) § Data pins work together to return wide word (e.g., 64-bit data bus using 16x4-bit parts) CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 12 DRAM Packaging, Mobile Devices [ Apple A4 package on circuit board] Two stacked DRAM die Processor plus logic die [ Apple A4 package cross-secon, iFixit 2010 ] CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 13 DRAM OperaVon § Three steps in read/write access to a given bank § Row access (RAS) - decode row address, enable addressed row (oEen mulCple Kb in row) - bitlines share charge with storage cell - small change in voltage detected by sense amplifiers which latch whole row of bits - sense amplifiers drive bitlines full rail to recharge storage cells § Column access (CAS) - decode column address to select small number of sense amplifier latches (4, 8, 16, or 32 bits depending on DRAM package) - on read, send latched bits out to chip pins - on write, change sense amplifier latches which then charge storage cells to required value - can perform mulCple column accesses on same row without another row access (burst mode) § Precharge - charges bit lines to known value, required before next row access § Each step has a latency of around 15-20ns in modern DRAMs § Various DRAM standards (DDR, RDRAM) have different ways of encoding the signals for transmission to the DRAM, but all share same core architecture CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 14 Memory Parameters § Latency - Time from iniCaon to compleCon of one memory read (e.g., in nanoseconds, or in CPU or DRAM clock cycles) § Occupancy - Time that a memory bank is busy with one request - Usually the important parameter for a memory write § Bandwidth - Rate at which requests can be processed (accesses/sec, or GB/s) § All can vary significantly for reads vs. writes, or address, or address history (e.g., open/close page on DRAM bank) CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 15 CS252, Fall 2015, Lecture 11 1000 instrucCons during Cme for one memory access! Four-issue 3GHz superscalar accessing 100ns DRAM could execute 1,200 Performance 100 10 1 1980 1981 1982 Processor-DRAM Gap (latency) 1983 1984 1985 1986 1987 © Krste Asanovic, 2015 µProc 60%/year Time 1988 1989 1990 1991 1992 1993 1994 1995 1996 (growing 50%/yr) Performance Gap: Processor-Memory 1997 DRAM 1998 1999 CPU 2000 7%/year DRAM 16 Physical Size Affects Latency CPU CPU Small Memory Big Memory § Signals have further to travel § Fan out to more locaons CS252, Fall 2015, Lecture 11 © Krste Asanovic, 2015 17 Two predictable properes of memory references: § Temporal Locality: If a locaon is referenced it is likely to be referenced again in the near future.
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